From nobody Sat May 4 21:09:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1621489572; cv=none; d=zohomail.com; s=zohoarc; b=kWgRCGTuvZ6V19bI6ybyyHYVG+b6xPzpW0dGdE61sHrD3FhBOmw9yv5uddeZ4V/2Ir7yyCv8IG25VeLPbXdu7FtXjaN07gpayRDTevLLsgzpZFmsfDm14+ajFMyo+59rCQ+GvwY3c03dg3BwEHkAWF/qXzK+wPvIQTMno+hJ5AA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621489572; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=XDzQxiIkJMMQXzv5cqJjRVSNQK/j+nnZmIfQloT8U3o=; b=DzGPvUpqWyECxjBxD4bdG9ptWqNjndgyYuNXNoUOS12a2Jq8Y3VHwUk73OnM9YQw8SgKJl3Wa2TptvFCHaLaXkufyLPPu55b0LUHPMYEHC7ngL3sjmELshO77zHEM9e+HZYQXU1yLK+F2Qrhq1pBKDG6NJP8ZdT/UnO7eZ1cDU0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16214895723136.20538902904832; Wed, 19 May 2021 22:46:12 -0700 (PDT) Received: from localhost ([::1]:53714 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljbVb-0007yS-8f for importer2@patchew.org; Thu, 20 May 2021 01:46:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60744) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljbTI-0005Aq-El for qemu-devel@nongnu.org; Thu, 20 May 2021 01:43:52 -0400 Received: from mga06.intel.com ([134.134.136.31]:7413) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljbTG-00075Z-Eq for qemu-devel@nongnu.org; Thu, 20 May 2021 01:43:48 -0400 Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2021 22:43:36 -0700 Received: from michael-optiplex-9020.sh.intel.com ([10.239.159.172]) by fmsmga008.fm.intel.com with ESMTP; 19 May 2021 22:43:33 -0700 IronPort-SDR: AzJlXZq+xY1QBc8L7BUIiQ+WEFmWAa1hgPmgAylqq4doTrgVhlCfvjOKkkSfMn+U2jSAhibLK4 i45a+1+FbPig== X-IronPort-AV: E=McAfee;i="6200,9189,9989"; a="262370931" X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="262370931" IronPort-SDR: uGMfOOcozJnBYZqIrDXGgVBRCe/m0H9ZGSCREuEbij73URjdKVHoq9lxMwRibbcacgw04qapq5 v2Rz3mFpBaTg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="440160285" From: Yang Weijiang To: pbonzini@redhat.com, ehabkost@redhat.com, mtosatti@redhat.com, seanjc@google.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v8 1/6] target/i386: Change XSAVE related feature-word names Date: Thu, 20 May 2021 13:57:06 +0800 Message-Id: <1621490231-4765-2-git-send-email-weijiang.yang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> References: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.31; envelope-from=weijiang.yang@intel.com; helo=mga06.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rename XSAVE related feature-words for introducing XSAVES related feature-words. Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 24 ++++++++++++------------ target/i386/cpu.h | 4 ++-- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ad99cad0e7..5c76186883 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1077,7 +1077,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { .cpuid =3D { .eax =3D 6, .reg =3D R_EAX, }, .tcg_features =3D TCG_6_EAX_FEATURES, }, - [FEAT_XSAVE_COMP_LO] =3D { + [FEAT_XSAVE_XCR0_LO] =3D { .type =3D CPUID_FEATURE_WORD, .cpuid =3D { .eax =3D 0xD, @@ -1090,7 +1090,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_M= ASK | XSTATE_PKRU_MASK, }, - [FEAT_XSAVE_COMP_HI] =3D { + [FEAT_XSAVE_XCR0_HI] =3D { .type =3D CPUID_FEATURE_WORD, .cpuid =3D { .eax =3D 0xD, @@ -1519,8 +1519,8 @@ static inline bool accel_uses_host_cpuid(void) =20 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) { - return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 | - cpu->env.features[FEAT_XSAVE_COMP_LO]; + return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | + cpu->env.features[FEAT_XSAVE_XCR0_LO]; } =20 /* Return name of 32-bit register, from a R_* constant */ @@ -4811,8 +4811,8 @@ static const char *x86_cpu_feature_name(FeatureWord w= , int bitnr) /* XSAVE components are automatically enabled by other features, * so return the original feature name instead */ - if (w =3D=3D FEAT_XSAVE_COMP_LO || w =3D=3D FEAT_XSAVE_COMP_HI) { - int comp =3D (w =3D=3D FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr; + if (w =3D=3D FEAT_XSAVE_XCR0_LO || w =3D=3D FEAT_XSAVE_XCR0_HI) { + int comp =3D (w =3D=3D FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; =20 if (comp < ARRAY_SIZE(x86_ext_save_areas) && x86_ext_save_areas[comp].bits) { @@ -5860,8 +5860,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, =20 if (count =3D=3D 0) { *ecx =3D xsave_area_size(x86_cpu_xsave_components(cpu)); - *eax =3D env->features[FEAT_XSAVE_COMP_LO]; - *edx =3D env->features[FEAT_XSAVE_COMP_HI]; + *eax =3D env->features[FEAT_XSAVE_XCR0_LO]; + *edx =3D env->features[FEAT_XSAVE_XCR0_HI]; /* * The initial value of xcr0 and ebx =3D=3D 0, On host without= kvm * commit 412a3c41(e.g., CentOS 6), the ebx's value always =3D= =3D 0 @@ -6431,8 +6431,8 @@ static void x86_cpu_enable_xsave_components(X86CPU *c= pu) uint64_t mask; =20 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { - env->features[FEAT_XSAVE_COMP_LO] =3D 0; - env->features[FEAT_XSAVE_COMP_HI] =3D 0; + env->features[FEAT_XSAVE_XCR0_LO] =3D 0; + env->features[FEAT_XSAVE_XCR0_HI] =3D 0; return; } =20 @@ -6444,8 +6444,8 @@ static void x86_cpu_enable_xsave_components(X86CPU *c= pu) } } =20 - env->features[FEAT_XSAVE_COMP_LO] =3D mask; - env->features[FEAT_XSAVE_COMP_HI] =3D mask >> 32; + env->features[FEAT_XSAVE_XCR0_LO] =3D mask; + env->features[FEAT_XSAVE_XCR0_HI] =3D mask >> 32; } =20 /***** Steps involved on loading and filtering CPUID data diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 570f916878..84cb6adcaa 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -526,8 +526,8 @@ typedef enum FeatureWord { FEAT_SVM, /* CPUID[8000_000A].EDX */ FEAT_XSAVE, /* CPUID[EAX=3D0xd,ECX=3D1].EAX */ FEAT_6_EAX, /* CPUID[6].EAX */ - FEAT_XSAVE_COMP_LO, /* CPUID[EAX=3D0xd,ECX=3D0].EAX */ - FEAT_XSAVE_COMP_HI, /* CPUID[EAX=3D0xd,ECX=3D0].EDX */ + FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=3D0xd,ECX=3D0].EAX */ + FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=3D0xd,ECX=3D0].EDX */ FEAT_ARCH_CAPABILITIES, FEAT_CORE_CAPABILITY, FEAT_PERF_CAPABILITIES, --=20 2.26.2 From nobody Sat May 4 21:09:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1621489563; cv=none; d=zohomail.com; s=zohoarc; b=LkEnttlb6WDIND9jPRCw6nIOUChNMr4fJdpkR7Vbl9v7Kom+aiIO+/eOxXmCzF+xd++UWDjFElqu0rKdyd45G0tLI6Z4enS64AeaQViT27SeXtIcaSm4BEc9xZxt7Mx7WBIAp4SWkONEeHBfjIp+xJYzyiaXYJkUlEJPpqb3gsw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621489563; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=c4rQYXYRpb8EfVUS1hNYxi6hnO91IC4G11/XlTb8qVM=; b=n76puTOtp9e7gv+dQlLN8LBxCsICJFRA2kqNM4Wwd2UR1kty7qK8SChM4NxEmoDElZeY2SJbkzJcViyhT4r/TWeiSDcsS7TbyH0N8sjysoJD/Vzl8XIRLf3e03H24pKbdZYmdgTA+jZVXhF+mxSsRipR21O9MhRTOYC8IuPlEJQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1621489563928923.4400132476765; Wed, 19 May 2021 22:46:03 -0700 (PDT) Received: from localhost ([::1]:53358 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljbVS-0007je-Q1 for importer2@patchew.org; Thu, 20 May 2021 01:46:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60686) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljbTE-00055R-Af for qemu-devel@nongnu.org; Thu, 20 May 2021 01:43:44 -0400 Received: from mga06.intel.com ([134.134.136.31]:7415) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljbTB-00077a-3L for qemu-devel@nongnu.org; Thu, 20 May 2021 01:43:44 -0400 Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2021 22:43:38 -0700 Received: from michael-optiplex-9020.sh.intel.com ([10.239.159.172]) by fmsmga008.fm.intel.com with ESMTP; 19 May 2021 22:43:36 -0700 IronPort-SDR: koB/Bo5SQBLg3kGrUP5a6vm4HnQJFzzjOpgHwZcO9oLyxfV2wnIi2CGT6q2DigH76AIc+vPWvH KtD9QU5CIqTg== X-IronPort-AV: E=McAfee;i="6200,9189,9989"; a="262370935" X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="262370935" IronPort-SDR: X046M9kit6O+KxosRLzmdIpqGw7kIR0IPI+3yCpsCuxmdVSCNn2vqSQLT3FBAhMFdV/cbZvV/v V2jOpawWE8tQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="440160296" From: Yang Weijiang To: pbonzini@redhat.com, ehabkost@redhat.com, mtosatti@redhat.com, seanjc@google.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v8 2/6] target/i386: Enable XSS feature CPUID enumeration Date: Thu, 20 May 2021 13:57:07 +0800 Message-Id: <1621490231-4765-3-git-send-email-weijiang.yang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> References: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.31; envelope-from=weijiang.yang@intel.com; helo=mga06.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently, CPUID.(EAX=3D0DH,ECX=3D01H) doesn't enumerate features in XSS properly, so enable the support. XCR0 bits indicate user-mode XSAVE components, and XSS bits indicate supervisor-mode XSAVE components. Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 68 +++++++++++++++++++++++++++++++++++++++-------- target/i386/cpu.h | 9 +++++++ 2 files changed, 66 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5c76186883..d74d68e319 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1062,6 +1062,24 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { }, .tcg_features =3D TCG_XSAVE_FEATURES, }, + [FEAT_XSAVE_XSS_LO] =3D { + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { + .eax =3D 0xD, + .needs_ecx =3D true, + .ecx =3D 1, + .reg =3D R_ECX, + }, + }, + [FEAT_XSAVE_XSS_HI] =3D { + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { + .eax =3D 0xD, + .needs_ecx =3D true, + .ecx =3D 1, + .reg =3D R_EDX + }, + }, [FEAT_6_EAX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -1453,6 +1471,9 @@ typedef struct ExtSaveArea { uint32_t offset, size; } ExtSaveArea; =20 +/* CPUID feature bits available in XSS */ +#define CPUID_XSTATE_XSS_MASK 0 + static const ExtSaveArea x86_ext_save_areas[] =3D { [XSTATE_FP_BIT] =3D { /* x87 FP state component is always enabled if XSAVE is supported = */ @@ -1498,15 +1519,18 @@ static const ExtSaveArea x86_ext_save_areas[] =3D { .size =3D sizeof(XSavePKRU) }, }; =20 -static uint32_t xsave_area_size(uint64_t mask) +static uint32_t xsave_area_size(uint64_t mask, bool compacted) { + uint64_t ret =3D x86_ext_save_areas[0].size; + const ExtSaveArea *esa; + uint32_t offset =3D 0; int i; - uint64_t ret =3D 0; =20 - for (i =3D 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { - const ExtSaveArea *esa =3D &x86_ext_save_areas[i]; + for (i =3D 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { + esa =3D &x86_ext_save_areas[i]; if ((mask >> i) & 1) { - ret =3D MAX(ret, esa->offset + esa->size); + offset =3D compacted ? ret : esa->offset; + ret =3D MAX(ret, offset + esa->size); } } return ret; @@ -1517,7 +1541,7 @@ static inline bool accel_uses_host_cpuid(void) return kvm_enabled() || hvf_enabled(); } =20 -static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) +static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) { return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | cpu->env.features[FEAT_XSAVE_XCR0_LO]; @@ -1532,6 +1556,12 @@ static const char *get_register_name_32(unsigned int= reg) return x86_reg_info_32[reg].name; } =20 +static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) +{ + return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | + cpu->env.features[FEAT_XSAVE_XSS_LO]; +} + /* * Returns the set of feature flags that are supported and migratable by * QEMU, for a given FeatureWord. @@ -5859,7 +5889,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, } =20 if (count =3D=3D 0) { - *ecx =3D xsave_area_size(x86_cpu_xsave_components(cpu)); + *ecx =3D xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), f= alse); *eax =3D env->features[FEAT_XSAVE_XCR0_LO]; *edx =3D env->features[FEAT_XSAVE_XCR0_HI]; /* @@ -5868,14 +5898,25 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, * even through guest update xcr0, this will crash some legacy= guest * (e.g., CentOS 6), So set ebx =3D=3D ecx to workaroud it. */ - *ebx =3D kvm_enabled() ? *ecx : xsave_area_size(env->xcr0); + *ebx =3D kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, fal= se); } else if (count =3D=3D 1) { + uint64_t xstate =3D x86_cpu_xsave_xcr0_components(cpu) | + x86_cpu_xsave_xss_components(cpu); + *eax =3D env->features[FEAT_XSAVE]; + *ebx =3D xsave_area_size(xstate, true); + *ecx =3D env->features[FEAT_XSAVE_XSS_LO]; + *edx =3D env->features[FEAT_XSAVE_XSS_HI]; } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { - if ((x86_cpu_xsave_components(cpu) >> count) & 1) { - const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; + const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; + + if ((x86_cpu_xsave_xcr0_components(cpu) >> count) & 1) { *eax =3D esa->size; *ebx =3D esa->offset; + } else if ((x86_cpu_xsave_xss_components(cpu) >> count) & 1) { + *eax =3D esa->size; + *ebx =3D 0; + *ecx =3D 1; } } break; @@ -6206,6 +6247,9 @@ static void x86_cpu_reset(DeviceState *dev) } for (i =3D 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa =3D &x86_ext_save_areas[i]; + if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { + continue; + } if (env->features[esa->feature] & esa->bits) { xcr0 |=3D 1ull << i; } @@ -6444,8 +6488,10 @@ static void x86_cpu_enable_xsave_components(X86CPU *= cpu) } } =20 - env->features[FEAT_XSAVE_XCR0_LO] =3D mask; + env->features[FEAT_XSAVE_XCR0_LO] =3D mask & CPUID_XSTATE_XCR0_MASK; env->features[FEAT_XSAVE_XCR0_HI] =3D mask >> 32; + env->features[FEAT_XSAVE_XSS_LO] =3D mask & CPUID_XSTATE_XSS_MASK; + env->features[FEAT_XSAVE_XSS_HI] =3D mask >> 32; } =20 /***** Steps involved on loading and filtering CPUID data diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 84cb6adcaa..42f835d455 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -503,6 +503,13 @@ typedef enum X86Seg { #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) =20 +/* CPUID feature bits available in XCR0 */ +#define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ + XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \ + XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK |= \ + XSTATE_ZMM_Hi256_MASK | \ + XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK) + /* CPUID feature words */ typedef enum FeatureWord { FEAT_1_EDX, /* CPUID[1].EDX */ @@ -541,6 +548,8 @@ typedef enum FeatureWord { FEAT_VMX_BASIC, FEAT_VMX_VMFUNC, FEAT_14_0_ECX, + FEAT_XSAVE_XSS_LO, /* CPUID[EAX=3D0xd,ECX=3D1].ECX */ + FEAT_XSAVE_XSS_HI, /* CPUID[EAX=3D0xd,ECX=3D1].EDX */ FEATURE_WORDS, } FeatureWord; =20 --=20 2.26.2 From nobody Sat May 4 21:09:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1621489567; cv=none; d=zohomail.com; s=zohoarc; b=HCRdITdiNSlAta+sUj1Hdf2U7LM2HErgnp6+nitMCQmNmgdubq59AqKX+4u0GL3dt5BFEO8Eh64CQOymWV0poM1RN7kW6nTRhsisNoLpkoYddCSuHKMKUFEb3NW7LXrS4KKv5GGqRl2Z/ibptoyB0S9bRkqwqjPQDGCGomK5qio= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621489567; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=FcgXh/5ZLkg6gqoR/K978alvP4C44NXYKohs5cuR3C4=; b=XJvgQ0Dj8/k4q/wksJBBGKsJtU5+v4rWXEw6Zy/B3TD+TCpUjKLLt6yk8jX+EIHm5DBsOR/TWWfVOzg94UziVV6zmCaOEaWPK48cFK9qskHh2qy3rqy+hS6b1eyAJCtAP6IVtkJ5sHCBVk9ICnoF0fCq/d/NW07pkmNM8Vvn+sI= ARC-Authentication-Results: i=1; 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Thu, 20 May 2021 01:43:45 -0400 Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2021 22:43:41 -0700 Received: from michael-optiplex-9020.sh.intel.com ([10.239.159.172]) by fmsmga008.fm.intel.com with ESMTP; 19 May 2021 22:43:38 -0700 IronPort-SDR: 0YcZntxZmMWRXg8pRQQm0s7XZMDFAX7yp5qF5sOeoLj9p8PNgeq6Fjx8BLVVMLvNEcSh3U2Z7r 0NhFSf9HeipQ== X-IronPort-AV: E=McAfee;i="6200,9189,9989"; a="262370940" X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="262370940" IronPort-SDR: ar0N9UY+xr+HJvOfO2f4rKmGcGWNRQKYWaLSpahhINj89QNu6AMCJASfI73y9NJnpau60EGe0A iKFoBQEL3N9A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="440160306" From: Yang Weijiang To: pbonzini@redhat.com, ehabkost@redhat.com, mtosatti@redhat.com, seanjc@google.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v8 3/6] target/i386: Enable XSAVES support for CET states Date: Thu, 20 May 2021 13:57:08 +0800 Message-Id: <1621490231-4765-4-git-send-email-weijiang.yang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> References: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.31; envelope-from=weijiang.yang@intel.com; helo=mga06.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" CET Shadow Stack(SHSTK) and Indirect Branch Tracking(IBT) are enumerated via CPUID.(EAX=3D07H,ECX=3D0H):ECX[bit 7] and EDX[bit 20] respectively. Two CET bits (bit 11 and 12) are defined in MSR_IA32_XSS for XSAVES. They correspond to CET states in user and supervisor mode respectively. Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 42 +++++++++++++++++++++++++++++++++++++++++- target/i386/cpu.h | 21 +++++++++++++++++++++ 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d74d68e319..bae827c8d5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1064,6 +1064,16 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { }, [FEAT_XSAVE_XSS_LO] =3D { .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "cet-u", + "cet-s", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, .cpuid =3D { .eax =3D 0xD, .needs_ecx =3D true, @@ -1472,7 +1482,7 @@ typedef struct ExtSaveArea { } ExtSaveArea; =20 /* CPUID feature bits available in XSS */ -#define CPUID_XSTATE_XSS_MASK 0 +#define CPUID_XSTATE_XSS_MASK (XSTATE_CET_U_MASK) =20 static const ExtSaveArea x86_ext_save_areas[] =3D { [XSTATE_FP_BIT] =3D { @@ -1517,6 +1527,19 @@ static const ExtSaveArea x86_ext_save_areas[] =3D { { .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, .offset =3D offsetof(X86XSaveArea, pkru_state), .size =3D sizeof(XSavePKRU) }, + [XSTATE_CET_U_BIT] =3D { + .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_CET_SHSTK, + /* + * The features enabled in XSS MSR always use compacted format + * to store the data, in this case .offset =3D=3D 0. And CET bits + * fall into this category. + */ + .offset =3D 0, + .size =3D sizeof(XSavesCETU) }, + [XSTATE_CET_S_BIT] =3D { + .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_CET_SHSTK, + .offset =3D 0, + .size =3D sizeof(XSavesCETS) }, }; =20 static uint32_t xsave_area_size(uint64_t mask, bool compacted) @@ -6486,6 +6509,23 @@ static void x86_cpu_enable_xsave_components(X86CPU *= cpu) if (env->features[esa->feature] & esa->bits) { mask |=3D (1ULL << i); } + + /* + * Both CET SHSTK and IBT feature requires XSAVES support, but two + * features can be controlled independently by kernel, and we only + * have one correlated bit set in x86_ext_save_areas, so if either + * of two features is enabled, we set the XSAVES support bit to ma= ke + * the enabled feature work. + */ + if (i =3D=3D XSTATE_CET_U_BIT || i =3D=3D XSTATE_CET_S_BIT) { + uint64_t ecx =3D env->features[FEAT_7_0_ECX]; + uint64_t edx =3D env->features[FEAT_7_0_EDX]; + + if ((ecx & CPUID_7_0_ECX_CET_SHSTK) || + (edx & CPUID_7_0_EDX_CET_IBT)) { + mask |=3D (1ULL << i); + } + } } =20 env->features[FEAT_XSAVE_XCR0_LO] =3D mask & CPUID_XSTATE_XCR0_MASK; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 42f835d455..593a2d6823 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -492,6 +492,8 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_BIT 6 #define XSTATE_Hi16_ZMM_BIT 7 #define XSTATE_PKRU_BIT 9 +#define XSTATE_CET_U_BIT 11 +#define XSTATE_CET_S_BIT 12 =20 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) @@ -502,6 +504,8 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) +#define XSTATE_CET_U_MASK (1ULL << XSTATE_CET_U_BIT) +#define XSTATE_CET_S_MASK (1ULL << XSTATE_CET_S_BIT) =20 /* CPUID feature bits available in XCR0 */ #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ @@ -761,6 +765,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_WAITPKG (1U << 5) /* Additional AVX-512 Vector Byte Manipulation Instruction */ #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) +/* CET SHSTK feature */ +#define CPUID_7_0_ECX_CET_SHSTK (1U << 7) /* Galois Field New Instructions */ #define CPUID_7_0_ECX_GFNI (1U << 8) /* Vector AES Instructions */ @@ -800,6 +806,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_SERIALIZE (1U << 14) /* TSX Suspend Load Address Tracking instruction */ #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) +/* CET IBT feature */ +#define CPUID_7_0_EDX_CET_IBT (1U << 20) /* AVX512_FP16 instruction */ #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) /* Speculation Control */ @@ -1301,6 +1309,19 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; =20 +/* Ext. save area 11: User mode CET state */ +typedef struct XSavesCETU { + uint64_t u_cet; + uint64_t user_ssp; +} XSavesCETU; + +/* Ext. save area 12: Supervisor mode CET state */ +typedef struct XSavesCETS { + uint64_t kernel_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; +} XSavesCETS; + typedef struct X86XSaveArea { X86LegacyXSaveArea legacy; X86XSaveHeader header; --=20 2.26.2 From nobody Sat May 4 21:09:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1621489691; cv=none; d=zohomail.com; s=zohoarc; b=Nwl35JV3JirpFkbf9ujTYukEDTNsobeDg5LbEl7s/izVGjk3XaKeW1T6dr2cPRxVSNMKFkLxFgGjkfBX+x3Ni5bYelq2Oe8UYyfVUQCSrEtaKUi+RCPPiapib4vyQUc9RJCv8v18NC10yMTt38W1633RCKKwdln2Ci2L/nZnlm8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621489691; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=ego3tbyTWXRqy+GT55GEYaifJbIstETdW4R8TsmvVUI=; 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Thu, 20 May 2021 01:43:46 -0400 Received: from mga06.intel.com ([134.134.136.31]:7415) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljbTE-00077a-MK for qemu-devel@nongnu.org; Thu, 20 May 2021 01:43:46 -0400 Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2021 22:43:43 -0700 Received: from michael-optiplex-9020.sh.intel.com ([10.239.159.172]) by fmsmga008.fm.intel.com with ESMTP; 19 May 2021 22:43:41 -0700 IronPort-SDR: Z4iMP8S+p3zzXYvz6P51qn0OCQn700k+q+6SCNnxS8nf0sRKCP4N1oAkFm2e5G9szgAMYBfsIL RAfOsW/ngHhQ== X-IronPort-AV: E=McAfee;i="6200,9189,9989"; a="262370945" X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="262370945" IronPort-SDR: kUWUdVz29IpXvn1TqHpyOANO0kYGRazOo1r3HFzgR4yb2K4zpycet0W62eKR93ufGbYfkuSzAk X2Z+SO93Sz3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="440160315" From: Yang Weijiang To: pbonzini@redhat.com, ehabkost@redhat.com, mtosatti@redhat.com, seanjc@google.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v8 4/6] target/i386: Add user-space MSR access interface for CET Date: Thu, 20 May 2021 13:57:09 +0800 Message-Id: <1621490231-4765-5-git-send-email-weijiang.yang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> References: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.31; envelope-from=weijiang.yang@intel.com; helo=mga06.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" CET states are divided into user-mode and supervisor-mode states, MSR_KVM_GUEST_SSP holds current SHSTK pointer in use, MSR_IA32_U_CET and MSR_IA32_PL3_SSP are for user-mode states, others are for supervisor-mode states. Expose access according to current CET supported bits in CPUID and XSS. Signed-off-by: Yang Weijiang --- target/i386/cpu.h | 18 +++++++++++ target/i386/kvm/kvm.c | 72 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 593a2d6823..a5bb049d4e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -483,6 +483,15 @@ typedef enum X86Seg { #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 #define MSR_IA32_VMX_VMFUNC 0x00000491 =20 +#define MSR_IA32_U_CET 0x000006a0 +#define MSR_IA32_S_CET 0x000006a2 +#define MSR_IA32_PL0_SSP 0x000006a4 +#define MSR_IA32_PL1_SSP 0x000006a5 +#define MSR_IA32_PL2_SSP 0x000006a6 +#define MSR_IA32_PL3_SSP 0x000006a7 +#define MSR_IA32_SSP_TBL 0x000006a8 +#define MSR_KVM_GUEST_SSP 0x4b564d08 + #define XSTATE_FP_BIT 0 #define XSTATE_SSE_BIT 1 #define XSTATE_YMM_BIT 2 @@ -1601,6 +1610,15 @@ typedef struct CPUX86State { =20 uintptr_t retaddr; =20 + uint64_t u_cet; + uint64_t s_cet; + uint64_t pl0_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; + uint64_t pl3_ssp; + uint64_t ssp_tbl; + uint64_t guest_ssp; + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 7fe9f52710..c36ff7ffec 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -3047,6 +3047,30 @@ static int kvm_put_msrs(X86CPU *cpu, int level) } } =20 + if (((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) || + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)) && + (env->features[FEAT_XSAVE_XSS_LO] & XSTATE_CET_U_MASK)) { + kvm_msr_entry_add(cpu, MSR_IA32_U_CET, env->u_cet); + kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, env->pl3_ssp); + } + + if (env->features[FEAT_XSAVE_XSS_LO] & XSTATE_CET_S_MASK) { + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) { + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, env->pl0_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, env->pl1_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, env->pl2_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_SSP_TBL, env->ssp_tbl); + } + + kvm_msr_entry_add(cpu, MSR_IA32_S_CET, env->s_cet); + } + + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) && + (env->features[FEAT_XSAVE_XSS_LO] & (XSTATE_CET_U_MASK | + XSTATE_CET_S_MASK))) { + kvm_msr_entry_add(cpu, MSR_KVM_GUEST_SSP, env->guest_ssp); + } + return kvm_buf_set_msrs(cpu); } =20 @@ -3369,6 +3393,30 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 + if (((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) || + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)) && + (env->features[FEAT_XSAVE_XSS_LO] & XSTATE_CET_U_MASK)) { + kvm_msr_entry_add(cpu, MSR_IA32_U_CET, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, 0); + } + + if (env->features[FEAT_XSAVE_XSS_LO] & XSTATE_CET_S_MASK) { + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) { + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_SSP_TBL, 0); + } + + kvm_msr_entry_add(cpu, MSR_IA32_S_CET, 0); + } + + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) && + (env->features[FEAT_XSAVE_XSS_LO] & (XSTATE_CET_U_MASK | + XSTATE_CET_S_MASK))) { + kvm_msr_entry_add(cpu, MSR_KVM_GUEST_SSP, 0); + } + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; @@ -3658,6 +3706,30 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] =3D msrs[i]= .data; break; + case MSR_IA32_U_CET: + env->u_cet =3D msrs[i].data; + break; + case MSR_IA32_S_CET: + env->s_cet =3D msrs[i].data; + break; + case MSR_IA32_PL0_SSP: + env->pl0_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL1_SSP: + env->pl1_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL2_SSP: + env->pl2_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL3_SSP: + env->pl3_ssp =3D msrs[i].data; + break; + case MSR_IA32_SSP_TBL: + env->ssp_tbl =3D msrs[i].data; + break; + case MSR_KVM_GUEST_SSP: + env->guest_ssp =3D msrs[i].data; + break; } } =20 --=20 2.26.2 From nobody Sat May 4 21:09:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; 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Wed, 19 May 2021 22:49:12 -0700 (PDT) Received: from localhost ([::1]:35168 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljbYV-00067h-SC for importer2@patchew.org; Thu, 20 May 2021 01:49:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljbTM-0005DA-M8 for qemu-devel@nongnu.org; Thu, 20 May 2021 01:43:52 -0400 Received: from mga06.intel.com ([134.134.136.31]:7413) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljbTI-00075Z-PJ for qemu-devel@nongnu.org; Thu, 20 May 2021 01:43:52 -0400 Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2021 22:43:46 -0700 Received: from michael-optiplex-9020.sh.intel.com ([10.239.159.172]) by fmsmga008.fm.intel.com with ESMTP; 19 May 2021 22:43:44 -0700 IronPort-SDR: zvxsxowZnXSbSNbsKaka1LGPgVNRWuP/cX2k0zisKgpDNZ0671vEYw4ekMqLtUJiKMvkoUrwwL dSKji7RQK/2A== X-IronPort-AV: E=McAfee;i="6200,9189,9989"; a="262370947" X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="262370947" IronPort-SDR: cZqagD11VLjzvRbUJKGY9KOcyv4K/5+8Y9LtWZYrUvk5ioCiMlyXY9HtqzEq7i5y3jXfHMf0u9 rQwx8W9shfKQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="440160324" From: Yang Weijiang To: pbonzini@redhat.com, ehabkost@redhat.com, mtosatti@redhat.com, seanjc@google.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v8 5/6] target/i386: Add CET state support for guest migration Date: Thu, 20 May 2021 13:57:10 +0800 Message-Id: <1621490231-4765-6-git-send-email-weijiang.yang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> References: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.31; envelope-from=weijiang.yang@intel.com; helo=mga06.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Save the MSRs being used on source machine and restore them on destination machine. Signed-off-by: Yang Weijiang --- target/i386/machine.c | 161 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 161 insertions(+) diff --git a/target/i386/machine.c b/target/i386/machine.c index 137604ddb8..4d63340931 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1000,6 +1000,159 @@ static const VMStateDescription vmstate_umwait =3D { } }; =20 +static bool u_cet_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->u_cet !=3D 0; +} + +static const VMStateDescription vmstate_u_cet =3D { + .name =3D "cpu/u_cet", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D u_cet_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.u_cet, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool s_cet_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->s_cet !=3D 0; +} + +static const VMStateDescription vmstate_s_cet =3D { + .name =3D "cpu/s_cet", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D s_cet_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.s_cet, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pl0_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->pl0_ssp !=3D 0; +} + +static const VMStateDescription vmstate_pl0_ssp =3D { + .name =3D "cpu/pl0_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pl0_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl0_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pl1_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->pl1_ssp !=3D 0; +} + +static const VMStateDescription vmstate_pl1_ssp =3D { + .name =3D "cpu/pl1_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pl1_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl1_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pl2_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->pl2_ssp !=3D 0; +} + +static const VMStateDescription vmstate_pl2_ssp =3D { + .name =3D "cpu/pl2_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pl2_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl2_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + + +static bool pl3_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->pl3_ssp !=3D 0; +} + +static const VMStateDescription vmstate_pl3_ssp =3D { + .name =3D "cpu/pl3_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pl3_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl3_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool ssp_tbl_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->ssp_tbl !=3D 0; +} + +static const VMStateDescription vmstate_ssp_tbl =3D { + .name =3D "cpu/ssp_tbl", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D ssp_tbl_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.ssp_tbl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool guest_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->guest_ssp !=3D 0; +} + +static const VMStateDescription vmstate_guest_ssp =3D { + .name =3D "cpu/guest_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D guest_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.guest_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + static bool pkru_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -1531,6 +1684,14 @@ VMStateDescription vmstate_x86_cpu =3D { &vmstate_nested_state, #endif &vmstate_msr_tsx_ctrl, + &vmstate_u_cet, + &vmstate_s_cet, + &vmstate_pl0_ssp, + &vmstate_pl1_ssp, + &vmstate_pl2_ssp, + &vmstate_pl3_ssp, + &vmstate_ssp_tbl, + &vmstate_guest_ssp, NULL } }; --=20 2.26.2 From nobody Sat May 4 21:09:43 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1621489689; cv=none; d=zohomail.com; s=zohoarc; b=WsidKJ/RYP/v08s8cA+WrVrxBVAwsPZWUH8giYLjw2pqK9UzrPzIw7HG/swEVdYmPvVJSPbO2SaA1ndp90gaAm4SaVZv+xeHkPkiVWbxAna5edgo38XnrK1mgRIJIl8uoJxPcp9wgfAzsC1Fr5FvXw52jMZC0vVh2k65d5zpWGg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Thu, 20 May 2021 01:43:52 -0400 Received: from mga06.intel.com ([134.134.136.31]:7428) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljbTJ-0007Ed-VL for qemu-devel@nongnu.org; Thu, 20 May 2021 01:43:52 -0400 Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2021 22:43:49 -0700 Received: from michael-optiplex-9020.sh.intel.com ([10.239.159.172]) by fmsmga008.fm.intel.com with ESMTP; 19 May 2021 22:43:46 -0700 IronPort-SDR: E+Nv6HkK62VuO+3ouN9HIzsALySHqVrO/yHBT5gu/uyhfBDh4/Ne+vco88GGZxcP4hjcXdPkYt kakgQQXgpy+g== X-IronPort-AV: E=McAfee;i="6200,9189,9989"; a="262370953" X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="262370953" IronPort-SDR: l86XHgvatcBptmpFu20V5aILv2evHBb0zd6N8/ETmsvws9g1pH0G5RhSv3WcxZrVL91D2+7ULl R0J8GxBjTG+g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="440160347" From: Yang Weijiang To: pbonzini@redhat.com, ehabkost@redhat.com, mtosatti@redhat.com, seanjc@google.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v8 6/6] target/i386: Advise CET bits in CPU/MSR feature words Date: Thu, 20 May 2021 13:57:11 +0800 Message-Id: <1621490231-4765-7-git-send-email-weijiang.yang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> References: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.31; envelope-from=weijiang.yang@intel.com; helo=mga06.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" CET SHSTK and IBT feature are enumerated via CPUID.(EAX=3D07H,ECX=3D0H):ECX= [bit 7] and EDX[bit 20]. CET state load/restore at vmentry/vmexit are enabled via VMX_ENTRY_CTLS[bit 20] and VMX_EXIT_CTLS[bit 28]. Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index bae827c8d5..b432b681d8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -958,7 +958,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, "avx512vbmi", "umip", "pku", - NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, + NULL /* ospke */, "waitpkg", "avx512vbmi2", "shstk", "gfni", "vaes", "vpclmulqdq", "avx512vnni", "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, @@ -981,7 +981,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { "avx512-vp2intersect", NULL, "md-clear", NULL, NULL, NULL, "serialize", NULL, "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, - NULL, NULL, NULL, "avx512-fp16", + "ibt", NULL, NULL, "avx512-fp16", NULL, NULL, "spec-ctrl", "stibp", NULL, "arch-capabilities", "core-capability", "ssbd", }, @@ -1243,7 +1243,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { "vmx-exit-save-efer", "vmx-exit-load-efer", "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, - NULL, "vmx-exit-load-pkrs", NULL, NULL, + "vmx-exit-save-cet-ctl", "vmx-exit-load-pkrs", NULL, NULL, }, .msr =3D { .index =3D MSR_IA32_VMX_TRUE_EXIT_CTLS, @@ -1258,7 +1258,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { NULL, "vmx-entry-ia32e-mode", NULL, NULL, NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat",= "vmx-entry-load-efer", "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NUL= L, - NULL, NULL, "vmx-entry-load-pkrs", NULL, + "vmx-entry-load-cet-ctl", NULL, "vmx-entry-load-pkrs", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, --=20 2.26.2