From nobody Thu Jul 10 00:53:14 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=ispras.ru ARC-Seal: i=1; a=rsa-sha256; t=1674544410; cv=none; d=zohomail.com; s=zohoarc; b=gjDbb3wXKpM/51ZwMnKcD1awVVOy2lVOI4c18bB2sTYjx2ab8RJZwnUgqQ7L0E0gKfGxMiZ7pdKlDC2tG2Jy0D8WtaH6nLCGQhbFmpPtBUWQDTJO2PmtrzO4EodtoipQaAXvLIiEUM2XIINKFWWxHwPIgXDH+X1uV6OYB/jdGZs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674544410; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JDkSTOF4ZSccLuN0+D1LwxUKAELn+F8RW9JWW5Fjo0U=; b=TWLsGJIvEnnS+NWMdArB2fwb839HLUoBbeIv++L8Jv0f/yMzgjCpjMGYNJGhqUs4vEv6L2VxDVPMjyKxHZTG/q/fWjJKEDt8fgukrxJGJaU9uYDTdNx4NU6KGRLjYEcHlfTMcuT5hFD5eIWkN4lIDTYpnBA+PHqtXVD8MBbvquE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674544410354858.5336106645449; Mon, 23 Jan 2023 23:13:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKDUW-0003LB-AS; Tue, 24 Jan 2023 02:13:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKDUH-0002i2-C9 for qemu-devel@nongnu.org; Tue, 24 Jan 2023 02:13:00 -0500 Received: from mail.ispras.ru ([83.149.199.84]) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKDUF-0002pn-6e for qemu-devel@nongnu.org; Tue, 24 Jan 2023 02:12:57 -0500 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id 373D744C1024; Tue, 24 Jan 2023 07:12:51 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru 373D744C1024 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1674544371; bh=JDkSTOF4ZSccLuN0+D1LwxUKAELn+F8RW9JWW5Fjo0U=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=EkxvzW62HRNLsBzx7+cUJckTCmHqlSuYZ8TtSFuc277ZGRcaECrD6VzM751q+ok8I 4wDZGRyaKwrNX/j6sA1+n5VvSswfXQbdxB+O5usMOvYMNrcp8NL2fxur9PMID+gRWl EvprApzQ2N/AjFPqsmNLKIlyKlpKdcHJ6BhOQIYI= Subject: [PATCH v2 5/5] target/avr: enable icount mode From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, mrolnik@gmail.com, philmd@linaro.org, richard.henderson@linaro.org Date: Tue, 24 Jan 2023 10:12:51 +0300 Message-ID: <167454437102.3686700.12946995765767009502.stgit@pasha-ThinkPad-X280> In-Reply-To: <167454434356.3686700.6888237867240722060.stgit@pasha-ThinkPad-X280> References: <167454434356.3686700.6888237867240722060.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ispras.ru) X-ZM-MESSAGEID: 1674544411790100001 Icount mode requires correct can_do_io flag management for checking that IO operations are performed only in the last TB instruction. This patch sets this flag before every helper which can lead to virtual hardware access. It enables deterministic execution in icount mode for AVR. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Richard Henderson --- target/avr/translate.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index 40b15d116e..ee137dfe54 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1406,6 +1406,10 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *= a) { TCGv temp =3D tcg_const_i32(a->reg); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(temp, cpu_env, temp); tcg_gen_andi_tl(temp, temp, 1 << a->bit); ctx->skip_cond =3D TCG_COND_EQ; @@ -1424,6 +1428,10 @@ static bool trans_SBIS(DisasContext *ctx, arg_SBIS *= a) { TCGv temp =3D tcg_const_i32(a->reg); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(temp, cpu_env, temp); tcg_gen_andi_tl(temp, temp, 1 << a->bit); ctx->skip_cond =3D TCG_COND_NE; @@ -1621,6 +1629,9 @@ static TCGv gen_get_zaddr(DisasContext *ctx, bool ram) static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) { if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_fullwr(cpu_env, data, addr); } else { tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] =3D data = */ @@ -1630,6 +1641,9 @@ static void gen_data_store(DisasContext *ctx, TCGv da= ta, TCGv addr) static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_fullrd(data, cpu_env, addr); } else { tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data =3D mem[addr]= */ @@ -2335,6 +2349,10 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a) TCGv Rd =3D cpu_r[a->rd]; TCGv port =3D tcg_const_i32(a->imm); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(Rd, cpu_env, port); =20 tcg_temp_free_i32(port); @@ -2351,6 +2369,10 @@ static bool trans_OUT(DisasContext *ctx, arg_OUT *a) TCGv Rd =3D cpu_r[a->rd]; TCGv port =3D tcg_const_i32(a->imm); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_outb(cpu_env, port, Rd); =20 tcg_temp_free_i32(port); @@ -2651,6 +2673,10 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a) TCGv data =3D tcg_temp_new_i32(); TCGv port =3D tcg_const_i32(a->reg); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(data, cpu_env, port); tcg_gen_ori_tl(data, data, 1 << a->bit); gen_helper_outb(cpu_env, port, data); @@ -2670,6 +2696,10 @@ static bool trans_CBI(DisasContext *ctx, arg_CBI *a) TCGv data =3D tcg_temp_new_i32(); TCGv port =3D tcg_const_i32(a->reg); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(data, cpu_env, port); tcg_gen_andi_tl(data, data, ~(1 << a->bit)); gen_helper_outb(cpu_env, port, data);