From nobody Sat Jul 12 15:36:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486020445821406.9186784246141; Wed, 1 Feb 2017 23:27:25 -0800 (PST) Received: from localhost ([::1]:55025 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZBnf-0002yp-Pl for importer@patchew.org; Thu, 02 Feb 2017 02:27:23 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52801) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZ9kJ-00080n-Em for qemu-devel@nongnu.org; Thu, 02 Feb 2017 00:15:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cZ9kC-0004Ka-9Q for qemu-devel@nongnu.org; Thu, 02 Feb 2017 00:15:47 -0500 Received: from ozlabs.org ([103.22.144.67]:58631) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cZ9kB-0004HD-9P; Thu, 02 Feb 2017 00:15:39 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vDSqb0ppxz9sNH; Thu, 2 Feb 2017 16:15:03 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1486012507; bh=qOfva8E/krGdgpGb6NkZPFF27fhn+GA5DDzNstIaa6g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fT12HUVka4YSLpKu6ITz+cJMHxcMgj0qIBEWUuvPAeey5djMBvX7398HMEAVh8pq7 I0PXEAitidIyQtG3wA6LbwYC0XvMa/F3SX2qDRO8IWjpmoNJG6rzePAKH5TTcczkYH gk2kIVvR8emaPvEtoqGWfJEobhJRNA+tSIKrpnOU= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 2 Feb 2017 16:14:39 +1100 Message-Id: <20170202051445.5735-102-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170202051445.5735-1-david@gibson.dropbear.id.au> References: <20170202051445.5735-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 101/107] target-ppc: Add xststdc[sp, dp, qp] instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, thuth@redhat.com, Nikunj A Dadhania , qemu-devel@nongnu.org, mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Nikunj A Dadhania xststdcsp: VSX Scalar Test Data Class Single-Precision xststdcdp: VSX Scalar Test Data Class Double-Precision xststdcqp: VSX Scalar Test Data Class Quad-Precision Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 66 ++++++++++++++++++++++++++++++++-= ---- target/ppc/helper.h | 3 ++ target/ppc/internal.h | 1 + target/ppc/translate/vsx-impl.inc.c | 3 ++ target/ppc/translate/vsx-ops.inc.c | 4 +++ 5 files changed, 69 insertions(+), 8 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 45bc93c..9f5cafd 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3196,17 +3196,22 @@ void helper_xvxsigsp(CPUPPCState *env, uint32_t opc= ode) * fld - vsr_t field (VsrD(*) or VsrW(*)) * tfld - target vsr_t field (VsrD(*) or VsrW(*)) * fld_max - target field max + * scrf - set result in CR and FPCC */ -#define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max) \ +#define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max, scrf) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ ppc_vsr_t xt, xb; \ uint32_t i, sign, dcmx; \ - uint32_t match =3D 0; \ + uint32_t cc, match =3D 0; \ \ getVSR(xbn, &xb, env); \ - memset(&xt, 0, sizeof(xt)); \ - dcmx =3D DCMX_XV(opcode); \ + if (!scrf) { \ + memset(&xt, 0, sizeof(xt)); \ + dcmx =3D DCMX_XV(opcode); \ + } else { \ + dcmx =3D DCMX(opcode); \ + } \ \ for (i =3D 0; i < nels; i++) { \ sign =3D tp##_is_neg(xb.fld); \ @@ -3219,11 +3224,56 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ } else if (tp##_is_zero_or_denormal(xb.fld)) { \ match =3D extract32(dcmx, 0 + !sign, 1); \ } \ - xt.tfld =3D match ? fld_max : 0; \ + \ + if (scrf) { \ + cc =3D sign << CRF_LT_BIT | match << CRF_EQ_BIT; \ + env->fpscr &=3D ~(0x0F << FPSCR_FPRF); \ + env->fpscr |=3D cc << FPSCR_FPRF; \ + env->crf[BF(opcode)] =3D cc; \ + } else { \ + xt.tfld =3D match ? fld_max : 0; \ + } \ match =3D 0; \ } \ - putVSR(xT(opcode), &xt, env); \ + if (!scrf) { \ + putVSR(xT(opcode), &xt, env); \ + } \ } =20 -VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MA= X) -VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MA= X) +VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MA= X, 0) +VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MA= X, 0) +VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1) +VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1) + +void helper_xststdcsp(CPUPPCState *env, uint32_t opcode) +{ + ppc_vsr_t xb; + uint32_t dcmx, sign, exp; + uint32_t cc, match =3D 0, not_sp =3D 0; + + getVSR(xB(opcode), &xb, env); + dcmx =3D DCMX(opcode); + exp =3D (xb.VsrD(0) >> 52) & 0x7FF; + + sign =3D float64_is_neg(xb.VsrD(0)); + if (float64_is_any_nan(xb.VsrD(0))) { + match =3D extract32(dcmx, 6, 1); + } else if (float64_is_infinity(xb.VsrD(0))) { + match =3D extract32(dcmx, 4 + !sign, 1); + } else if (float64_is_zero(xb.VsrD(0))) { + match =3D extract32(dcmx, 2 + !sign, 1); + } else if (float64_is_zero_or_denormal(xb.VsrD(0)) || + (exp > 0 && exp < 0x381)) { + match =3D extract32(dcmx, 0 + !sign, 1); + } + + not_sp =3D !float64_eq(xb.VsrD(0), + float32_to_float64( + float64_to_float32(xb.VsrD(0), &env->fp_statu= s), + &env->fp_status), &env->fp_status); + + cc =3D sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT; + env->fpscr &=3D ~(0x0F << FPSCR_FPRF); + env->fpscr |=3D cc << FPSCR_FPRF; + env->crf[BF(opcode)] =3D cc; +} diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 165e4a5..85af9df 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -451,6 +451,9 @@ DEF_HELPER_2(xscvuxdsp, void, env, i32) DEF_HELPER_2(xscvsxdsp, void, env, i32) DEF_HELPER_2(xscvudqp, void, env, i32) DEF_HELPER_2(xscvuxddp, void, env, i32) +DEF_HELPER_2(xststdcsp, void, env, i32) +DEF_HELPER_2(xststdcdp, void, env, i32) +DEF_HELPER_2(xststdcqp, void, env, i32) DEF_HELPER_2(xsrdpi, void, env, i32) DEF_HELPER_2(xsrdpic, void, env, i32) DEF_HELPER_2(xsrdpim, void, env, i32) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 4c3811a..5a2fd68 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -198,6 +198,7 @@ EXTRACT_HELPER(UIM, 16, 2); EXTRACT_HELPER(SHW, 8, 2); EXTRACT_HELPER(SP, 19, 2); EXTRACT_HELPER(IMM8, 11, 8); +EXTRACT_HELPER(DCMX, 16, 7); EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6); =20 typedef union _ppc_vsr_t { diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index adb6fc7..a44c003 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -850,6 +850,9 @@ GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) +GEN_VSX_HELPER_2(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300) +GEN_VSX_HELPER_2(xststdcdp, 0x14, 0x16, 0, PPC2_ISA300) +GEN_VSX_HELPER_2(xststdcqp, 0x04, 0x16, 0, PPC2_ISA300) =20 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-= ops.inc.c index 6dd5d72..7dc9f6f 100644 --- a/target/ppc/translate/vsx-ops.inc.c +++ b/target/ppc/translate/vsx-ops.inc.c @@ -126,6 +126,10 @@ GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE,= PPC2_ISA300), GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001), #endif =20 +GEN_XX2FORM(xststdcdp, 0x14, 0x16, PPC2_ISA300), +GEN_XX2FORM(xststdcsp, 0x14, 0x12, PPC2_ISA300), +GEN_VSX_XFORM_300(xststdcqp, 0x04, 0x16, 0x00000001), + GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300), GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300), GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300), --=20 2.9.3