From nobody Sat Jul 12 15:04:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 14860132286810.8488102160346216; Wed, 1 Feb 2017 21:27:08 -0800 (PST) Received: from localhost ([::1]:54261 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZ9vG-0001DE-Qu for importer@patchew.org; Thu, 02 Feb 2017 00:27:06 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50930) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZ9ja-00073i-Tl for qemu-devel@nongnu.org; Thu, 02 Feb 2017 00:15:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cZ9jX-0003Ox-OD for qemu-devel@nongnu.org; Thu, 02 Feb 2017 00:15:02 -0500 Received: from ozlabs.org ([103.22.144.67]:59755) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cZ9jW-0003Md-UC; Thu, 02 Feb 2017 00:14:59 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vDSqK4Tbpz9s7M; Thu, 2 Feb 2017 16:14:51 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1486012493; bh=9qp/CSYARDCjuKBhRz70c5dqeNIxcuLWZ/4Z2iMpM6Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p9ogwmOJHBfXv+1qJ2agAqHfABh+ofwNjUcZBN1IOBUJeNcSfCAYsP6f9/+ChJFQH rv/1FDsbruRwgzigG+/iXmM3oS8Nt1b3atyPJsHU7tH/KqhppwP95j2Qj4FosVyJtm AC6UfAYS7h8xshVQNjffXxEguIDf/4XzBdAWC8Gg= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 2 Feb 2017 16:13:01 +1100 Message-Id: <20170202051445.5735-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170202051445.5735-1-david@gibson.dropbear.id.au> References: <20170202051445.5735-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 003/107] target-ppc: rename CRF_* defines as CRF_*_BIT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, thuth@redhat.com, Nikunj A Dadhania , qemu-devel@nongnu.org, mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Nikunj A Dadhania Add _BIT to CRF_[GT,LT,EQ_SO] and introduce CRF_[GT,LT,EQ,SO] for usage without shifts in the code. This would simplify the code. Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/cpu.h | 21 +++++++++++++-------- target/ppc/int_helper.c | 30 +++++++++++++++--------------- target/ppc/translate.c | 14 +++++++------- 3 files changed, 35 insertions(+), 30 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2a50c43..b6782ba 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1301,14 +1301,19 @@ static inline int cpu_mmu_index (CPUPPCState *env, = bool ifetch) =20 /*************************************************************************= ****/ /* CRF definitions */ -#define CRF_LT 3 -#define CRF_GT 2 -#define CRF_EQ 1 -#define CRF_SO 0 -#define CRF_CH (1 << CRF_LT) -#define CRF_CL (1 << CRF_GT) -#define CRF_CH_OR_CL (1 << CRF_EQ) -#define CRF_CH_AND_CL (1 << CRF_SO) +#define CRF_LT_BIT 3 +#define CRF_GT_BIT 2 +#define CRF_EQ_BIT 1 +#define CRF_SO_BIT 0 +#define CRF_LT (1 << CRF_LT_BIT) +#define CRF_GT (1 << CRF_GT_BIT) +#define CRF_EQ (1 << CRF_EQ_BIT) +#define CRF_SO (1 << CRF_SO_BIT) +/* For SPE extensions */ +#define CRF_CH (1 << CRF_LT_BIT) +#define CRF_CL (1 << CRF_GT_BIT) +#define CRF_CH_OR_CL (1 << CRF_EQ_BIT) +#define CRF_CH_AND_CL (1 << CRF_SO_BIT) =20 /* XER definitions */ #define XER_SO 31 diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 1871792..fbc84e2 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -157,7 +157,7 @@ uint64_t helper_divde(CPUPPCState *env, uint64_t rau, u= int64_t rbu, uint32_t oe) =20 uint32_t helper_cmpeqb(target_ulong ra, target_ulong rb) { - return hasvalue(rb, ra) ? 1 << CRF_GT : 0; + return hasvalue(rb, ra) ? CRF_GT : 0; } =20 #undef pattern @@ -2531,9 +2531,9 @@ static void bcd_put_digit(ppc_avr_t *bcd, uint8_t dig= it, int n) static int bcd_cmp_zero(ppc_avr_t *bcd) { if (bcd->u64[HI_IDX] =3D=3D 0 && (bcd->u64[LO_IDX] >> 4) =3D=3D 0) { - return 1 << CRF_EQ; + return CRF_EQ; } else { - return (bcd_get_sgn(bcd) =3D=3D 1) ? 1 << CRF_GT : 1 << CRF_LT; + return (bcd_get_sgn(bcd) =3D=3D 1) ? CRF_GT : CRF_LT; } } =20 @@ -2645,25 +2645,25 @@ uint32_t helper_bcdadd(ppc_avr_t *r, ppc_avr_t *a,= ppc_avr_t *b, uint32_t ps) if (sgna =3D=3D sgnb) { result.u8[BCD_DIG_BYTE(0)] =3D bcd_preferred_sgn(sgna, ps); zero =3D bcd_add_mag(&result, a, b, &invalid, &overflow); - cr =3D (sgna > 0) ? 1 << CRF_GT : 1 << CRF_LT; + cr =3D (sgna > 0) ? CRF_GT : CRF_LT; } else if (bcd_cmp_mag(a, b) > 0) { result.u8[BCD_DIG_BYTE(0)] =3D bcd_preferred_sgn(sgna, ps); zero =3D bcd_sub_mag(&result, a, b, &invalid, &overflow); - cr =3D (sgna > 0) ? 1 << CRF_GT : 1 << CRF_LT; + cr =3D (sgna > 0) ? CRF_GT : CRF_LT; } else { result.u8[BCD_DIG_BYTE(0)] =3D bcd_preferred_sgn(sgnb, ps); zero =3D bcd_sub_mag(&result, b, a, &invalid, &overflow); - cr =3D (sgnb > 0) ? 1 << CRF_GT : 1 << CRF_LT; + cr =3D (sgnb > 0) ? CRF_GT : CRF_LT; } } =20 if (unlikely(invalid)) { result.u64[HI_IDX] =3D result.u64[LO_IDX] =3D -1; - cr =3D 1 << CRF_SO; + cr =3D CRF_SO; } else if (overflow) { - cr |=3D 1 << CRF_SO; + cr |=3D CRF_SO; } else if (zero) { - cr =3D 1 << CRF_EQ; + cr =3D CRF_EQ; } =20 *r =3D result; @@ -2713,7 +2713,7 @@ uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, ui= nt32_t ps) cr =3D bcd_cmp_zero(&ret); =20 if (unlikely(invalid)) { - cr =3D 1 << CRF_SO; + cr =3D CRF_SO; } =20 *r =3D ret; @@ -2743,11 +2743,11 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, = uint32_t ps) cr =3D bcd_cmp_zero(b); =20 if (ox_flag) { - cr |=3D 1 << CRF_SO; + cr |=3D CRF_SO; } =20 if (unlikely(invalid)) { - cr =3D 1 << CRF_SO; + cr =3D CRF_SO; } =20 *r =3D ret; @@ -2791,7 +2791,7 @@ uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, ui= nt32_t ps) cr =3D bcd_cmp_zero(&ret); =20 if (unlikely(invalid)) { - cr =3D 1 << CRF_SO; + cr =3D CRF_SO; } =20 *r =3D ret; @@ -2830,11 +2830,11 @@ uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, = uint32_t ps) cr =3D bcd_cmp_zero(b); =20 if (ox_flag) { - cr |=3D 1 << CRF_SO; + cr |=3D CRF_SO; } =20 if (unlikely(invalid)) { - cr =3D 1 << CRF_SO; + cr =3D CRF_SO; } =20 *r =3D ret; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 8c99ea3..e55a5dc 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -612,17 +612,17 @@ static inline void gen_op_cmp(TCGv arg0, TCGv arg1, i= nt s, int crf) =20 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); tcg_gen_trunc_tl_i32(t1, t0); - tcg_gen_shli_i32(t1, t1, CRF_LT); + tcg_gen_shli_i32(t1, t1, CRF_LT_BIT); tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); =20 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); tcg_gen_trunc_tl_i32(t1, t0); - tcg_gen_shli_i32(t1, t1, CRF_GT); + tcg_gen_shli_i32(t1, t1, CRF_GT_BIT); tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); =20 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); tcg_gen_trunc_tl_i32(t1, t0); - tcg_gen_shli_i32(t1, t1, CRF_EQ); + tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT); tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); =20 tcg_temp_free(t0); @@ -748,7 +748,7 @@ static void gen_cmprb(DisasContext *ctx) tcg_gen_and_i32(src2lo, src2lo, src2hi); tcg_gen_or_i32(crf, crf, src2lo); } - tcg_gen_shli_i32(crf, crf, CRF_GT); + tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); tcg_temp_free_i32(src1); tcg_temp_free_i32(src2); tcg_temp_free_i32(src2lo); @@ -2997,7 +2997,7 @@ static void gen_conditional_store(DisasContext *ctx, = TCGv EA, tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); l1 =3D gen_new_label(); tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); + tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop); gen_set_label(l1); tcg_gen_movi_tl(cpu_reserve, -1); @@ -3091,7 +3091,7 @@ static void gen_stqcx_(DisasContext *ctx) tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); l1 =3D gen_new_label(); tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); + tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); =20 if (unlikely(ctx->le_mode)) { gpr1 =3D cpu_gpr[reg + 1]; @@ -4272,7 +4272,7 @@ static void gen_slbfee_(DisasContext *ctx) l2 =3D gen_new_label(); tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); + tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); tcg_gen_br(l2); gen_set_label(l1); tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); --=20 2.9.3