[Qemu-devel] [PATCH v3 00/16] target-m68k: implement 680x0 FPU

Laurent Vivier posted 16 patches 7 years, 2 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20170207005930.28327-1-laurent@vivier.eu
Test checkpatch failed
Test docker passed
Test s390x passed
There is a newer version of this series
configure                  |    2 +-
fpu/softfloat-specialize.h |   34 +-
fpu/softfloat.c            |   31 ++
gdb-xml/m68k-fp.xml        |   21 +
include/fpu/softfloat.h    |   15 -
target/m68k/Makefile.objs  |    2 +-
target/m68k/cpu.c          |   13 +-
target/m68k/cpu.h          |   75 ++-
target/m68k/fpu_helper.c   |  972 ++++++++++++++++++++++++++++++++
target/m68k/helper.c       |  165 +++---
target/m68k/helper.h       |   73 ++-
target/m68k/qregs.def      |    4 +-
target/m68k/translate.c    | 1318 +++++++++++++++++++++++++++++++++-----------
13 files changed, 2254 insertions(+), 471 deletions(-)
create mode 100644 gdb-xml/m68k-fp.xml
create mode 100644 target/m68k/fpu_helper.c
[Qemu-devel] [PATCH v3 00/16] target-m68k: implement 680x0 FPU
Posted by Laurent Vivier 7 years, 2 months ago
This series modifies the original ColdFire FPU implementation
to use floatx80 instead of float64 internally as this
is the native datatype for 680x0. I didn't keep the float64
type for ColdFire, but if someone thinks it's required I
can update this series in this way.

The series also adds the FPU status and control registers and
several floating point instructions.

The floatx80 datatype used here is not exactly the same as the
one used by 680x0 for its extended precision data type, because
normally the signaling bit of 680x0 NAN is the MSB of the mantissa
minus one and in floatx80 it is the MSB.

We also add the gdb server parts to read the new FPU registers.
A strange thing happens here: while the gdb client running remotely
from a debian etch-m68k has no issue working with 96bit FPU registers
(the 680x0 extended precision data type), new gdbs (from a debian unstable
and gdb for cross-compiled environment) don't expect this FPU registers
size. But it seems like a bug in gdb, not in this implementation.

After this series is applied, qemu-m68k can run a debian etch-m68k
or a debian unstable chroot.

v3:
    fix fsave opcode
    Add comment to define "unnormalized" number
    Correctly define pickNaN()

v2:
    complete rework of the series
    force single precision in ColdFire mode
    add "forced" precision instructions (fsmove, fdmove, fsadd, ...)
    fixed Fcc.

Laurent Vivier (16):
  softfloat: define 680x0 specific values
  softloat: disable floatx80_invalid_encoding() for m68k
  target-m68k: move FPU helpers to fpu_helper.c
  target-m68k: define ext_opsize
  target-m68k: use floatx80 internally
  target-m68k: add FPCR and FPSR
  target-m68k: manage FPU exceptions
  target-m68k: define 96bit FP registers for gdb on 680x0
  target-m68k: add fmovem
  target-m68k: add fscc.
  target-m68k: add fmovecr
  target-m68k: add fscale, fgetman, fgetexp and fmod
  target-m68k: add fsglmul and fsgldiv
  target-m68k: add explicit single and double precision operations
  target-m68k: add more FPU instructions
  target-m68k: add fsincos

 configure                  |    2 +-
 fpu/softfloat-specialize.h |   34 +-
 fpu/softfloat.c            |   31 ++
 gdb-xml/m68k-fp.xml        |   21 +
 include/fpu/softfloat.h    |   15 -
 target/m68k/Makefile.objs  |    2 +-
 target/m68k/cpu.c          |   13 +-
 target/m68k/cpu.h          |   75 ++-
 target/m68k/fpu_helper.c   |  972 ++++++++++++++++++++++++++++++++
 target/m68k/helper.c       |  165 +++---
 target/m68k/helper.h       |   73 ++-
 target/m68k/qregs.def      |    4 +-
 target/m68k/translate.c    | 1318 +++++++++++++++++++++++++++++++++-----------
 13 files changed, 2254 insertions(+), 471 deletions(-)
 create mode 100644 gdb-xml/m68k-fp.xml
 create mode 100644 target/m68k/fpu_helper.c

-- 
2.9.3


Re: [Qemu-devel] [PATCH v3 00/16] target-m68k: implement 680x0 FPU
Posted by no-reply@patchew.org 7 years, 2 months ago
Hi,

Your series seems to have some coding style problems. See output below for
more information:

Type: series
Subject: [Qemu-devel] [PATCH v3 00/16] target-m68k: implement 680x0 FPU
Message-id: 20170207005930.28327-1-laurent@vivier.eu

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20170207005930.28327-1-laurent@vivier.eu -> patchew/20170207005930.28327-1-laurent@vivier.eu
Switched to a new branch 'test'
24fef09 target-m68k: add fsincos
31936e6 target-m68k: add more FPU instructions
04f5a29 target-m68k: add explicit single and double precision operations
8117b9d target-m68k: add fsglmul and fsgldiv
a11400e target-m68k: add fscale, fgetman, fgetexp and fmod
22a8624 target-m68k: add fmovecr
85d9833 target-m68k: add fscc.
403aa87 target-m68k: add fmovem
f53725e target-m68k: define 96bit FP registers for gdb on 680x0
0a01215 target-m68k: manage FPU exceptions
194d954 target-m68k: add FPCR and FPSR
2ae3010 target-m68k: use floatx80 internally
7833d24 target-m68k: define ext_opsize
971c3fd target-m68k: move FPU helpers to fpu_helper.c
214af1e softloat: disable floatx80_invalid_encoding() for m68k
71a3a80 softfloat: define 680x0 specific values

=== OUTPUT BEGIN ===
Checking PATCH 1/16: softfloat: define 680x0 specific values...
Checking PATCH 2/16: softloat: disable floatx80_invalid_encoding() for m68k...
Checking PATCH 3/16: target-m68k: move FPU helpers to fpu_helper.c...
Checking PATCH 4/16: target-m68k: define ext_opsize...
Checking PATCH 5/16: target-m68k: use floatx80 internally...
ERROR: storage class should be at the beginning of the declaration
#457: FILE: target/m68k/translate.c:39:
+#define DEFF96(name, offset) static TCGv_i32 QREG_##name##H; \

total: 1 errors, 0 warnings, 1204 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 6/16: target-m68k: add FPCR and FPSR...
Checking PATCH 7/16: target-m68k: manage FPU exceptions...
Checking PATCH 8/16: target-m68k: define 96bit FP registers for gdb on 680x0...
Checking PATCH 9/16: target-m68k: add fmovem...
Checking PATCH 10/16: target-m68k: add fscc....
Checking PATCH 11/16: target-m68k: add fmovecr...
Checking PATCH 12/16: target-m68k: add fscale, fgetman, fgetexp and fmod...
Checking PATCH 13/16: target-m68k: add fsglmul and fsgldiv...
Checking PATCH 14/16: target-m68k: add explicit single and double precision operations...
Checking PATCH 15/16: target-m68k: add more FPU instructions...
Checking PATCH 16/16: target-m68k: add fsincos...
=== OUTPUT END ===

Test command exited with code: 1


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