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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=66.111.4.223; envelope-from=david.edmondson@oracle.com; helo=forward1-smtp.messagingengine.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, Marcelo Tosatti , Richard Henderson , David Edmondson , Babu Moger , Paolo Bonzini Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Declare and use manifest constants for the XSAVE state component offsets. Signed-off-by: David Edmondson --- target/i386/cpu.h | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e6836393f7..1fb732f366 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1305,6 +1305,22 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; =20 +#define XSAVE_FCW_FSW_OFFSET 0x000 +#define XSAVE_FTW_FOP_OFFSET 0x004 +#define XSAVE_CWD_RIP_OFFSET 0x008 +#define XSAVE_CWD_RDP_OFFSET 0x010 +#define XSAVE_MXCSR_OFFSET 0x018 +#define XSAVE_ST_SPACE_OFFSET 0x020 +#define XSAVE_XMM_SPACE_OFFSET 0x0a0 +#define XSAVE_XSTATE_BV_OFFSET 0x200 +#define XSAVE_AVX_OFFSET 0x240 +#define XSAVE_BNDREG_OFFSET 0x3c0 +#define XSAVE_BNDCSR_OFFSET 0x400 +#define XSAVE_OPMASK_OFFSET 0x440 +#define XSAVE_ZMM_HI256_OFFSET 0x480 +#define XSAVE_HI16_ZMM_OFFSET 0x680 +#define XSAVE_PKRU_OFFSET 0xa80 + typedef struct X86XSaveArea { X86LegacyXSaveArea legacy; X86XSaveHeader header; @@ -1325,19 +1341,19 @@ typedef struct X86XSaveArea { XSavePKRU pkru_state; } X86XSaveArea; =20 -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) !=3D 0x240); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) !=3D XSAVE_AVX_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) !=3D 0x100); -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) !=3D 0x3c0); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) !=3D XSAVE_BNDREG_O= FFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) !=3D 0x40); -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) !=3D 0x400); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) !=3D XSAVE_BNDCSR_O= FFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) !=3D 0x40); -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) !=3D 0x440); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) !=3D XSAVE_OPMASK_O= FFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) !=3D 0x40); -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) !=3D 0x480); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) !=3D XSAVE_ZMM_H= I256_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) !=3D 0x200); -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) !=3D 0x680); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) !=3D XSAVE_HI16_Z= MM_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) !=3D 0x400); -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) !=3D 0xA80); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) !=3D XSAVE_PKRU_OFFSE= T); QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); =20 typedef enum TPRAccess { --=20 2.30.2 From nobody Wed May 8 08:49:21 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1621523014; cv=none; d=zohomail.com; s=zohoarc; b=Js4PQ02KYkLnzwmLHnCAzyG3Lm1az165S56Q+XE4WzbVxUvTms5Hdr+FbpJwVBPoNfd7BE9sMkUPW6VsA52BdmEl+Av2C9BkLvy+V6Lej4DbQMMTEO55po6yp4HtlvQKydzs2tfm1sN2PnV9ewIXpslKHUe7zu9fo5IXDzKJcl8= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=66.111.4.223; envelope-from=david.edmondson@oracle.com; helo=forward1-smtp.messagingengine.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665, UNPARSEABLE_RELAY=0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, Marcelo Tosatti , Richard Henderson , David Edmondson , Babu Moger , Paolo Bonzini Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Where existing constants for XSAVE offsets exists, use them. Signed-off-by: David Edmondson --- target/i386/kvm/kvm.c | 56 ++++++++++++++----------------------------- 1 file changed, 18 insertions(+), 38 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index d972eb4705..aff0774fef 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2397,44 +2397,24 @@ static int kvm_put_fpu(X86CPU *cpu) return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu); } =20 -#define XSAVE_FCW_FSW 0 -#define XSAVE_FTW_FOP 1 -#define XSAVE_CWD_RIP 2 -#define XSAVE_CWD_RDP 4 -#define XSAVE_MXCSR 6 -#define XSAVE_ST_SPACE 8 -#define XSAVE_XMM_SPACE 40 -#define XSAVE_XSTATE_BV 128 -#define XSAVE_YMMH_SPACE 144 -#define XSAVE_BNDREGS 240 -#define XSAVE_BNDCSR 256 -#define XSAVE_OPMASK 272 -#define XSAVE_ZMM_Hi256 288 -#define XSAVE_Hi16_ZMM 416 -#define XSAVE_PKRU 672 - -#define XSAVE_BYTE_OFFSET(word_offset) \ - ((word_offset) * sizeof_field(struct kvm_xsave, region[0])) - -#define ASSERT_OFFSET(word_offset, field) \ - QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) !=3D \ - offsetof(X86XSaveArea, field)) - -ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw); -ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw); -ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip); -ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp); -ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr); -ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs); -ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs); -ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv); -ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state); -ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state); -ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state); -ASSERT_OFFSET(XSAVE_OPMASK, opmask_state); -ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state); -ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state); -ASSERT_OFFSET(XSAVE_PKRU, pkru_state); +#define ASSERT_OFFSET(offset, field) \ + QEMU_BUILD_BUG_ON(offset !=3D offsetof(X86XSaveArea, field)) + +ASSERT_OFFSET(XSAVE_FCW_FSW_OFFSET, legacy.fcw); +ASSERT_OFFSET(XSAVE_FTW_FOP_OFFSET, legacy.ftw); +ASSERT_OFFSET(XSAVE_CWD_RIP_OFFSET, legacy.fpip); +ASSERT_OFFSET(XSAVE_CWD_RDP_OFFSET, legacy.fpdp); +ASSERT_OFFSET(XSAVE_MXCSR_OFFSET, legacy.mxcsr); +ASSERT_OFFSET(XSAVE_ST_SPACE_OFFSET, legacy.fpregs); +ASSERT_OFFSET(XSAVE_XMM_SPACE_OFFSET, legacy.xmm_regs); +ASSERT_OFFSET(XSAVE_XSTATE_BV_OFFSET, header.xstate_bv); +ASSERT_OFFSET(XSAVE_AVX_OFFSET, avx_state); +ASSERT_OFFSET(XSAVE_BNDREG_OFFSET, bndreg_state); +ASSERT_OFFSET(XSAVE_BNDCSR_OFFSET, bndcsr_state); +ASSERT_OFFSET(XSAVE_OPMASK_OFFSET, opmask_state); +ASSERT_OFFSET(XSAVE_ZMM_HI256_OFFSET, zmm_hi256_state); +ASSERT_OFFSET(XSAVE_HI16_ZMM_OFFSET, hi16_zmm_state); +ASSERT_OFFSET(XSAVE_PKRU_OFFSET, pkru_state); =20 static int kvm_put_xsave(X86CPU *cpu) { --=20 2.30.2 From nobody Wed May 8 08:49:21 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1621523264; cv=none; d=zohomail.com; s=zohoarc; b=CNjIXb9qQNRAk+fcDIFVU1fLgwg2Tm2Ynz2FQvvgkADvz3Ul26lFRguNfv8ZbIA8ASUJuwq2D67lC5A7tmEQbswbDP5CeEqRsbr1R1LYZbNxMqwmK08qqw5lvlx0mBJPNBqUiGDxaagB7dFl2rGjgxcEv4P2aR0ngeJbtA+tMB8= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=66.111.4.223; envelope-from=david.edmondson@oracle.com; helo=forward1-smtp.messagingengine.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, Marcelo Tosatti , Richard Henderson , David Edmondson , Babu Moger , Paolo Bonzini Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Replace the hard-coded size of offsets or structure elements with defined constants or sizeof(). Signed-off-by: David Edmondson --- target/i386/cpu.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1fb732f366..0bb365bddf 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1329,7 +1329,13 @@ typedef struct X86XSaveArea { =20 /* AVX State: */ XSaveAVX avx_state; - uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; + + /* Ensure that XSaveBNDREG is properly aligned. */ + uint8_t padding[XSAVE_BNDREG_OFFSET + - sizeof(X86LegacyXSaveArea) + - sizeof(X86XSaveHeader) + - sizeof(XSaveAVX)]; + /* MPX State: */ XSaveBNDREG bndreg_state; XSaveBNDCSR bndcsr_state; --=20 2.30.2 From nobody Wed May 8 08:49:21 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1621523433; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=66.111.4.223; envelope-from=david.edmondson@oracle.com; helo=forward1-smtp.messagingengine.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, Marcelo Tosatti , Richard Henderson , David Edmondson , Babu Moger , Paolo Bonzini Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Move Intel specific components of X86XSaveArea into a sub-union. Signed-off-by: David Edmondson --- target/i386/cpu.c | 12 ++++---- target/i386/cpu.h | 55 +++++++++++++++++++++--------------- target/i386/kvm/kvm.c | 12 ++++---- target/i386/tcg/fpu_helper.c | 12 ++++---- target/i386/xsave_helper.c | 24 ++++++++-------- 5 files changed, 63 insertions(+), 52 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c496bfa1c2..4f481691b4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1418,27 +1418,27 @@ static const ExtSaveArea x86_ext_save_areas[] =3D { .size =3D sizeof(XSaveAVX) }, [XSTATE_BNDREGS_BIT] =3D { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_MPX, - .offset =3D offsetof(X86XSaveArea, bndreg_state), + .offset =3D offsetof(X86XSaveArea, intel.bndreg_state), .size =3D sizeof(XSaveBNDREG) }, [XSTATE_BNDCSR_BIT] =3D { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_MPX, - .offset =3D offsetof(X86XSaveArea, bndcsr_state), + .offset =3D offsetof(X86XSaveArea, intel.bndcsr_state), .size =3D sizeof(XSaveBNDCSR) }, [XSTATE_OPMASK_BIT] =3D { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, - .offset =3D offsetof(X86XSaveArea, opmask_state), + .offset =3D offsetof(X86XSaveArea, intel.opmask_state), .size =3D sizeof(XSaveOpmask) }, [XSTATE_ZMM_Hi256_BIT] =3D { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, - .offset =3D offsetof(X86XSaveArea, zmm_hi256_state), + .offset =3D offsetof(X86XSaveArea, intel.zmm_hi256_state), .size =3D sizeof(XSaveZMM_Hi256) }, [XSTATE_Hi16_ZMM_BIT] =3D { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, - .offset =3D offsetof(X86XSaveArea, hi16_zmm_state), + .offset =3D offsetof(X86XSaveArea, intel.hi16_zmm_state), .size =3D sizeof(XSaveHi16_ZMM) }, [XSTATE_PKRU_BIT] =3D { .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, - .offset =3D offsetof(X86XSaveArea, pkru_state), + .offset =3D offsetof(X86XSaveArea, intel.pkru_state), .size =3D sizeof(XSavePKRU) }, }; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0bb365bddf..f1ce4e3008 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1330,36 +1330,47 @@ typedef struct X86XSaveArea { /* AVX State: */ XSaveAVX avx_state; =20 - /* Ensure that XSaveBNDREG is properly aligned. */ - uint8_t padding[XSAVE_BNDREG_OFFSET - - sizeof(X86LegacyXSaveArea) - - sizeof(X86XSaveHeader) - - sizeof(XSaveAVX)]; - - /* MPX State: */ - XSaveBNDREG bndreg_state; - XSaveBNDCSR bndcsr_state; - /* AVX-512 State: */ - XSaveOpmask opmask_state; - XSaveZMM_Hi256 zmm_hi256_state; - XSaveHi16_ZMM hi16_zmm_state; - /* PKRU State: */ - XSavePKRU pkru_state; + union { + struct { + /* Ensure that XSaveBNDREG is properly aligned. */ + uint8_t padding[XSAVE_BNDREG_OFFSET + - sizeof(X86LegacyXSaveArea) + - sizeof(X86XSaveHeader) + - sizeof(XSaveAVX)]; + + /* MPX State: */ + XSaveBNDREG bndreg_state; + XSaveBNDCSR bndcsr_state; + /* AVX-512 State: */ + XSaveOpmask opmask_state; + XSaveZMM_Hi256 zmm_hi256_state; + XSaveHi16_ZMM hi16_zmm_state; + /* PKRU State: */ + XSavePKRU pkru_state; + } intel; + }; } X86XSaveArea; =20 -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) !=3D XSAVE_AVX_OFFSET); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) + !=3D XSAVE_AVX_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) !=3D 0x100); -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) !=3D XSAVE_BNDREG_O= FFSET); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, intel.bndreg_state) + !=3D XSAVE_BNDREG_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) !=3D 0x40); -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) !=3D XSAVE_BNDCSR_O= FFSET); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, intel.bndcsr_state) + !=3D XSAVE_BNDCSR_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) !=3D 0x40); -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) !=3D XSAVE_OPMASK_O= FFSET); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, intel.opmask_state) + !=3D XSAVE_OPMASK_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) !=3D 0x40); -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) !=3D XSAVE_ZMM_H= I256_OFFSET); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, intel.zmm_hi256_state) + !=3D XSAVE_ZMM_HI256_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) !=3D 0x200); -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) !=3D XSAVE_HI16_Z= MM_OFFSET); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, intel.hi16_zmm_state) + !=3D XSAVE_HI16_ZMM_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) !=3D 0x400); -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) !=3D XSAVE_PKRU_OFFSE= T); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, intel.pkru_state) + !=3D XSAVE_PKRU_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); =20 typedef enum TPRAccess { diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index aff0774fef..417776a635 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2409,12 +2409,12 @@ ASSERT_OFFSET(XSAVE_ST_SPACE_OFFSET, legacy.fpregs); ASSERT_OFFSET(XSAVE_XMM_SPACE_OFFSET, legacy.xmm_regs); ASSERT_OFFSET(XSAVE_XSTATE_BV_OFFSET, header.xstate_bv); ASSERT_OFFSET(XSAVE_AVX_OFFSET, avx_state); -ASSERT_OFFSET(XSAVE_BNDREG_OFFSET, bndreg_state); -ASSERT_OFFSET(XSAVE_BNDCSR_OFFSET, bndcsr_state); -ASSERT_OFFSET(XSAVE_OPMASK_OFFSET, opmask_state); -ASSERT_OFFSET(XSAVE_ZMM_HI256_OFFSET, zmm_hi256_state); -ASSERT_OFFSET(XSAVE_HI16_ZMM_OFFSET, hi16_zmm_state); -ASSERT_OFFSET(XSAVE_PKRU_OFFSET, pkru_state); +ASSERT_OFFSET(XSAVE_BNDREG_OFFSET, intel.bndreg_state); +ASSERT_OFFSET(XSAVE_BNDCSR_OFFSET, intel.bndcsr_state); +ASSERT_OFFSET(XSAVE_OPMASK_OFFSET, intel.opmask_state); +ASSERT_OFFSET(XSAVE_ZMM_HI256_OFFSET, intel.zmm_hi256_state); +ASSERT_OFFSET(XSAVE_HI16_ZMM_OFFSET, intel.hi16_zmm_state); +ASSERT_OFFSET(XSAVE_PKRU_OFFSET, intel.pkru_state); =20 static int kvm_put_xsave(X86CPU *cpu) { diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 1b30f1bb73..fba2de5b04 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -2637,13 +2637,13 @@ static void do_xsave(CPUX86State *env, target_ulong= ptr, uint64_t rfbm, do_xsave_sse(env, ptr, ra); } if (opt & XSTATE_BNDREGS_MASK) { - do_xsave_bndregs(env, ptr + XO(bndreg_state), ra); + do_xsave_bndregs(env, ptr + XO(intel.bndreg_state), ra); } if (opt & XSTATE_BNDCSR_MASK) { - do_xsave_bndcsr(env, ptr + XO(bndcsr_state), ra); + do_xsave_bndcsr(env, ptr + XO(intel.bndcsr_state), ra); } if (opt & XSTATE_PKRU_MASK) { - do_xsave_pkru(env, ptr + XO(pkru_state), ra); + do_xsave_pkru(env, ptr + XO(intel.pkru_state), ra); } =20 /* Update the XSTATE_BV field. */ @@ -2836,7 +2836,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr= , uint64_t rfbm) } if (rfbm & XSTATE_BNDREGS_MASK) { if (xstate_bv & XSTATE_BNDREGS_MASK) { - do_xrstor_bndregs(env, ptr + XO(bndreg_state), ra); + do_xrstor_bndregs(env, ptr + XO(intel.bndreg_state), ra); env->hflags |=3D HF_MPX_IU_MASK; } else { memset(env->bnd_regs, 0, sizeof(env->bnd_regs)); @@ -2845,7 +2845,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr= , uint64_t rfbm) } if (rfbm & XSTATE_BNDCSR_MASK) { if (xstate_bv & XSTATE_BNDCSR_MASK) { - do_xrstor_bndcsr(env, ptr + XO(bndcsr_state), ra); + do_xrstor_bndcsr(env, ptr + XO(intel.bndcsr_state), ra); } else { memset(&env->bndcs_regs, 0, sizeof(env->bndcs_regs)); } @@ -2854,7 +2854,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr= , uint64_t rfbm) if (rfbm & XSTATE_PKRU_MASK) { uint64_t old_pkru =3D env->pkru; if (xstate_bv & XSTATE_PKRU_MASK) { - do_xrstor_pkru(env, ptr + XO(pkru_state), ra); + do_xrstor_pkru(env, ptr + XO(intel.pkru_state), ra); } else { env->pkru =3D 0; } diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c index 818115e7d2..97dbab85d1 100644 --- a/target/i386/xsave_helper.c +++ b/target/i386/xsave_helper.c @@ -31,16 +31,16 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea = *buf) sizeof env->fpregs); xsave->legacy.mxcsr =3D env->mxcsr; xsave->header.xstate_bv =3D env->xstate_bv; - memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs, + memcpy(&xsave->intel.bndreg_state.bnd_regs, env->bnd_regs, sizeof env->bnd_regs); - xsave->bndcsr_state.bndcsr =3D env->bndcs_regs; - memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs, + xsave->intel.bndcsr_state.bndcsr =3D env->bndcs_regs; + memcpy(&xsave->intel.opmask_state.opmask_regs, env->opmask_regs, sizeof env->opmask_regs); =20 for (i =3D 0; i < CPU_NB_REGS; i++) { uint8_t *xmm =3D xsave->legacy.xmm_regs[i]; uint8_t *ymmh =3D xsave->avx_state.ymmh[i]; - uint8_t *zmmh =3D xsave->zmm_hi256_state.zmm_hi256[i]; + uint8_t *zmmh =3D xsave->intel.zmm_hi256_state.zmm_hi256[i]; stq_p(xmm, env->xmm_regs[i].ZMM_Q(0)); stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1)); stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2)); @@ -52,9 +52,9 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *b= uf) } =20 #ifdef TARGET_X86_64 - memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16], + memcpy(&xsave->intel.hi16_zmm_state.hi16_zmm, &env->xmm_regs[16], 16 * sizeof env->xmm_regs[16]); - memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru); + memcpy(&xsave->intel.pkru_state, &env->pkru, sizeof env->pkru); #endif =20 } @@ -83,16 +83,16 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSa= veArea *buf) memcpy(env->fpregs, &xsave->legacy.fpregs, sizeof env->fpregs); env->xstate_bv =3D xsave->header.xstate_bv; - memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs, + memcpy(env->bnd_regs, &xsave->intel.bndreg_state.bnd_regs, sizeof env->bnd_regs); - env->bndcs_regs =3D xsave->bndcsr_state.bndcsr; - memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs, + env->bndcs_regs =3D xsave->intel.bndcsr_state.bndcsr; + memcpy(env->opmask_regs, &xsave->intel.opmask_state.opmask_regs, sizeof env->opmask_regs); =20 for (i =3D 0; i < CPU_NB_REGS; i++) { const uint8_t *xmm =3D xsave->legacy.xmm_regs[i]; const uint8_t *ymmh =3D xsave->avx_state.ymmh[i]; - const uint8_t *zmmh =3D xsave->zmm_hi256_state.zmm_hi256[i]; + const uint8_t *zmmh =3D xsave->intel.zmm_hi256_state.zmm_hi256[i]; env->xmm_regs[i].ZMM_Q(0) =3D ldq_p(xmm); env->xmm_regs[i].ZMM_Q(1) =3D ldq_p(xmm+8); env->xmm_regs[i].ZMM_Q(2) =3D ldq_p(ymmh); @@ -104,9 +104,9 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSa= veArea *buf) } =20 #ifdef TARGET_X86_64 - memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm, + memcpy(&env->xmm_regs[16], &xsave->intel.hi16_zmm_state.hi16_zmm, 16 * sizeof env->xmm_regs[16]); - memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru); + memcpy(&env->pkru, &xsave->intel.pkru_state, sizeof env->pkru); #endif =20 } --=20 2.30.2 From nobody Wed May 8 08:49:21 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1621523376; cv=none; d=zohomail.com; s=zohoarc; b=dA137LmWtjSUNSpe6Lk7XR1rhO62q2EoVv9pZyz1jISTpKOMTwtdk0PLB6KXi6ailohNprIqSa5d+NrMsRbTASwQkKaI5i1Xf/nfEXiW9Hc+8FDOY0vTjRwRa23eo+I/4cNZ7EOZ0YGEy5sE441pfoTgspHcTl5mkywua+TFDio= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621523376; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=66.111.4.223; envelope-from=david.edmondson@oracle.com; helo=forward1-smtp.messagingengine.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, Marcelo Tosatti , Richard Henderson , David Edmondson , Babu Moger , Paolo Bonzini Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" AMD stores the pkru_state at a different offset to Intel. Signed-off-by: David Edmondson --- target/i386/cpu.h | 17 +++++++++++++++-- target/i386/kvm/kvm.c | 3 ++- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f1ce4e3008..99f0d5d851 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1319,7 +1319,8 @@ typedef struct XSavePKRU { #define XSAVE_OPMASK_OFFSET 0x440 #define XSAVE_ZMM_HI256_OFFSET 0x480 #define XSAVE_HI16_ZMM_OFFSET 0x680 -#define XSAVE_PKRU_OFFSET 0xa80 +#define XSAVE_INTEL_PKRU_OFFSET 0xa80 +#define XSAVE_AMD_PKRU_OFFSET 0x980 =20 typedef struct X86XSaveArea { X86LegacyXSaveArea legacy; @@ -1348,6 +1349,16 @@ typedef struct X86XSaveArea { /* PKRU State: */ XSavePKRU pkru_state; } intel; + struct { + /* Ensure that XSavePKRU is properly aligned. */ + uint8_t padding[XSAVE_AMD_PKRU_OFFSET + - sizeof(X86LegacyXSaveArea) + - sizeof(X86XSaveHeader) + - sizeof(XSaveAVX)]; + + /* PKRU State: */ + XSavePKRU pkru_state; + } amd; }; } X86XSaveArea; =20 @@ -1370,7 +1381,9 @@ QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, intel.hi16_z= mm_state) !=3D XSAVE_HI16_ZMM_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) !=3D 0x400); QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, intel.pkru_state) - !=3D XSAVE_PKRU_OFFSET); + !=3D XSAVE_INTEL_PKRU_OFFSET); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, amd.pkru_state) + !=3D XSAVE_AMD_PKRU_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); =20 typedef enum TPRAccess { diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 417776a635..9dd7db060d 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2414,7 +2414,8 @@ ASSERT_OFFSET(XSAVE_BNDCSR_OFFSET, intel.bndcsr_state= ); ASSERT_OFFSET(XSAVE_OPMASK_OFFSET, intel.opmask_state); ASSERT_OFFSET(XSAVE_ZMM_HI256_OFFSET, intel.zmm_hi256_state); ASSERT_OFFSET(XSAVE_HI16_ZMM_OFFSET, intel.hi16_zmm_state); -ASSERT_OFFSET(XSAVE_PKRU_OFFSET, intel.pkru_state); +ASSERT_OFFSET(XSAVE_INTEL_PKRU_OFFSET, intel.pkru_state); +ASSERT_OFFSET(XSAVE_AMD_PKRU_OFFSET, amd.pkru_state); =20 static int kvm_put_xsave(X86CPU *cpu) { --=20 2.30.2 From nobody Wed May 8 08:49:21 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=66.111.4.223; envelope-from=david.edmondson@oracle.com; helo=forward1-smtp.messagingengine.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, Marcelo Tosatti , Richard Henderson , David Edmondson , Babu Moger , Paolo Bonzini Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" AMD stores the pkru_state at a different offset to Intel, so update the CPUID leaf which indicates such. Signed-off-by: David Edmondson --- target/i386/cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4f481691b4..9340a477a3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1397,7 +1397,7 @@ typedef struct ExtSaveArea { uint32_t offset, size; } ExtSaveArea; =20 -static const ExtSaveArea x86_ext_save_areas[] =3D { +static ExtSaveArea x86_ext_save_areas[] =3D { [XSTATE_FP_BIT] =3D { /* x87 FP state component is always enabled if XSAVE is supported = */ .feature =3D FEAT_1_ECX, .bits =3D CPUID_EXT_XSAVE, @@ -6088,6 +6088,11 @@ static void x86_cpu_filter_features(X86CPU *cpu, boo= l verbose) mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INT= EL_PT, prefix); } } + + if (IS_AMD_CPU(env)) { + x86_ext_save_areas[XSTATE_PKRU_BIT].offset =3D + offsetof(X86XSaveArea, amd.pkru_state); + } } =20 static void x86_cpu_hyperv_realize(X86CPU *cpu) --=20 2.30.2 From nobody Wed May 8 08:49:21 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=66.111.4.223; envelope-from=david.edmondson@oracle.com; helo=forward1-smtp.messagingengine.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, Marcelo Tosatti , Richard Henderson , David Edmondson , Babu Moger , Paolo Bonzini Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" On AMD CPUs, ensure to save/load only the relevant XSAVE state. Signed-off-by: David Edmondson --- target/i386/tcg/fpu_helper.c | 12 +++++-- target/i386/xsave_helper.c | 70 ++++++++++++++++++++++-------------- 2 files changed, 54 insertions(+), 28 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index fba2de5b04..f1d4704b34 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -2643,7 +2643,11 @@ static void do_xsave(CPUX86State *env, target_ulong = ptr, uint64_t rfbm, do_xsave_bndcsr(env, ptr + XO(intel.bndcsr_state), ra); } if (opt & XSTATE_PKRU_MASK) { - do_xsave_pkru(env, ptr + XO(intel.pkru_state), ra); + if (IS_AMD_CPU(env)) { + do_xsave_pkru(env, ptr + XO(amd.pkru_state), ra); + } else { + do_xsave_pkru(env, ptr + XO(intel.pkru_state), ra); + } } =20 /* Update the XSTATE_BV field. */ @@ -2854,7 +2858,11 @@ void helper_xrstor(CPUX86State *env, target_ulong pt= r, uint64_t rfbm) if (rfbm & XSTATE_PKRU_MASK) { uint64_t old_pkru =3D env->pkru; if (xstate_bv & XSTATE_PKRU_MASK) { - do_xrstor_pkru(env, ptr + XO(intel.pkru_state), ra); + if (IS_AMD_CPU(env)) { + do_xrstor_pkru(env, ptr + XO(amd.pkru_state), ra); + } else { + do_xrstor_pkru(env, ptr + XO(intel.pkru_state), ra); + } } else { env->pkru =3D 0; } diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c index 97dbab85d1..6b4501cf29 100644 --- a/target/i386/xsave_helper.c +++ b/target/i386/xsave_helper.c @@ -10,6 +10,7 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *b= uf) { CPUX86State *env =3D &cpu->env; X86XSaveArea *xsave =3D buf; + const bool is_amd =3D IS_AMD_CPU(env); =20 uint16_t cwd, swd, twd; int i; @@ -31,30 +32,38 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea = *buf) sizeof env->fpregs); xsave->legacy.mxcsr =3D env->mxcsr; xsave->header.xstate_bv =3D env->xstate_bv; - memcpy(&xsave->intel.bndreg_state.bnd_regs, env->bnd_regs, - sizeof env->bnd_regs); - xsave->intel.bndcsr_state.bndcsr =3D env->bndcs_regs; - memcpy(&xsave->intel.opmask_state.opmask_regs, env->opmask_regs, - sizeof env->opmask_regs); + if (!is_amd) { + memcpy(&xsave->intel.bndreg_state.bnd_regs, env->bnd_regs, + sizeof env->bnd_regs); + xsave->intel.bndcsr_state.bndcsr =3D env->bndcs_regs; + memcpy(&xsave->intel.opmask_state.opmask_regs, env->opmask_regs, + sizeof env->opmask_regs); + } =20 for (i =3D 0; i < CPU_NB_REGS; i++) { uint8_t *xmm =3D xsave->legacy.xmm_regs[i]; uint8_t *ymmh =3D xsave->avx_state.ymmh[i]; - uint8_t *zmmh =3D xsave->intel.zmm_hi256_state.zmm_hi256[i]; stq_p(xmm, env->xmm_regs[i].ZMM_Q(0)); stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1)); stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2)); stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3)); - stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4)); - stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5)); - stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6)); - stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7)); + if (!is_amd) { + uint8_t *zmmh =3D xsave->intel.zmm_hi256_state.zmm_hi256[i]; + stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4)); + stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5)); + stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6)); + stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7)); + } } =20 #ifdef TARGET_X86_64 - memcpy(&xsave->intel.hi16_zmm_state.hi16_zmm, &env->xmm_regs[16], - 16 * sizeof env->xmm_regs[16]); - memcpy(&xsave->intel.pkru_state, &env->pkru, sizeof env->pkru); + if (is_amd) { + memcpy(&xsave->amd.pkru_state, &env->pkru, sizeof env->pkru); + } else { + memcpy(&xsave->intel.hi16_zmm_state.hi16_zmm, &env->xmm_regs[16], + 16 * sizeof env->xmm_regs[16]); + memcpy(&xsave->intel.pkru_state, &env->pkru, sizeof env->pkru); + } #endif =20 } @@ -64,6 +73,7 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSave= Area *buf) =20 CPUX86State *env =3D &cpu->env; const X86XSaveArea *xsave =3D buf; + const bool is_amd =3D IS_AMD_CPU(env); =20 int i; uint16_t cwd, swd, twd; @@ -83,30 +93,38 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSa= veArea *buf) memcpy(env->fpregs, &xsave->legacy.fpregs, sizeof env->fpregs); env->xstate_bv =3D xsave->header.xstate_bv; - memcpy(env->bnd_regs, &xsave->intel.bndreg_state.bnd_regs, - sizeof env->bnd_regs); - env->bndcs_regs =3D xsave->intel.bndcsr_state.bndcsr; - memcpy(env->opmask_regs, &xsave->intel.opmask_state.opmask_regs, - sizeof env->opmask_regs); + if (!is_amd) { + memcpy(env->bnd_regs, &xsave->intel.bndreg_state.bnd_regs, + sizeof env->bnd_regs); + env->bndcs_regs =3D xsave->intel.bndcsr_state.bndcsr; + memcpy(env->opmask_regs, &xsave->intel.opmask_state.opmask_regs, + sizeof env->opmask_regs); + } =20 for (i =3D 0; i < CPU_NB_REGS; i++) { const uint8_t *xmm =3D xsave->legacy.xmm_regs[i]; const uint8_t *ymmh =3D xsave->avx_state.ymmh[i]; - const uint8_t *zmmh =3D xsave->intel.zmm_hi256_state.zmm_hi256[i]; env->xmm_regs[i].ZMM_Q(0) =3D ldq_p(xmm); env->xmm_regs[i].ZMM_Q(1) =3D ldq_p(xmm+8); env->xmm_regs[i].ZMM_Q(2) =3D ldq_p(ymmh); env->xmm_regs[i].ZMM_Q(3) =3D ldq_p(ymmh+8); - env->xmm_regs[i].ZMM_Q(4) =3D ldq_p(zmmh); - env->xmm_regs[i].ZMM_Q(5) =3D ldq_p(zmmh+8); - env->xmm_regs[i].ZMM_Q(6) =3D ldq_p(zmmh+16); - env->xmm_regs[i].ZMM_Q(7) =3D ldq_p(zmmh+24); + if (!is_amd) { + const uint8_t *zmmh =3D xsave->intel.zmm_hi256_state.zmm_hi256= [i]; + env->xmm_regs[i].ZMM_Q(4) =3D ldq_p(zmmh); + env->xmm_regs[i].ZMM_Q(5) =3D ldq_p(zmmh+8); + env->xmm_regs[i].ZMM_Q(6) =3D ldq_p(zmmh+16); + env->xmm_regs[i].ZMM_Q(7) =3D ldq_p(zmmh+24); + } } =20 #ifdef TARGET_X86_64 - memcpy(&env->xmm_regs[16], &xsave->intel.hi16_zmm_state.hi16_zmm, - 16 * sizeof env->xmm_regs[16]); - memcpy(&env->pkru, &xsave->intel.pkru_state, sizeof env->pkru); + if (is_amd) { + memcpy(&env->pkru, &xsave->amd.pkru_state, sizeof env->pkru); + } else { + memcpy(&env->xmm_regs[16], &xsave->intel.hi16_zmm_state.hi16_zmm, + 16 * sizeof env->xmm_regs[16]); + memcpy(&env->pkru, &xsave->intel.pkru_state, sizeof env->pkru); + } #endif =20 } --=20 2.30.2