From nobody Fri May 3 03:51:12 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1621524982; cv=none; d=zohomail.com; s=zohoarc; b=QQA9YB46zXBQyt85m8DAZHcX/W4KMSDcj6MnftgBQrjYlVLdxtYiKGP2fudANvuleJTyaUPM4CVPYFzO0O2Riisuq59oW/hCNwRSD+y9bHmDHwCbhDUS5zhreT1bFA6qwbD/bsJ7G+3NrYa92ZMn8tHhAkXS49Mko82LLjAhbiE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621524982; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DnbJwhTPFVUYyLIk68eWKoH+oBvtevWOvwYTKcV4l1s=; b=nFpynW87Jk66awAvsc9Rd4CjpceBkOdDdn1PVazTNxWafrM2gYryOi4CT5JtfIxVu4/T+X0iQkzbSx5V/FDciGtfvWc0L0tlkGk1UbM5X4xk3aQY0ueP1h1zdA3pi40MByWH+jqjooGS0G9lxqpLMae3HGE1MTX7B4SBrngl5rE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1621524982812525.6799764052299; Thu, 20 May 2021 08:36:22 -0700 (PDT) Received: from localhost ([::1]:53114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljkij-0007mF-Pf for importer2@patchew.org; Thu, 20 May 2021 11:36:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49574) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljkbO-0007ns-Uf for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:47 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:35438) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljkbM-0000dy-5h for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:46 -0400 Received: by mail-wr1-x435.google.com with SMTP id a4so18143059wrr.2 for ; Thu, 20 May 2021 08:28:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm3916126wrv.39.2021.05.20.08.28.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 08:28:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DnbJwhTPFVUYyLIk68eWKoH+oBvtevWOvwYTKcV4l1s=; b=L4DnhIB3svIofXAgpA318UFWOvnhwsrRI0h1TdkUhsRL3HiQrI70S/wvTslhiD8XGn c049/S7gDtBVKsonySz209zRJzE6VeMbLh2UHfbGkjp+zvH6Y9Rcrh4zngZRIs+T95FR AovXAagxmolPrGQpph0F6JUCCHC3GqCCnKAbsx15eIy0INi8XrH4AjSqtfwOsnjEpVf6 P3FgnK+I2n+BeNgMGhB6sT5dHILTmITXlz3jleuJv6xEq7wCBPbyo5FuC1ZhZ31viPvU UX5W4g3En/SHEA4vVm6zLzW1cFtxanCJVrsiOdVXmGXZG7yJegfPcAKGgz0KicoMRyAs 1jrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DnbJwhTPFVUYyLIk68eWKoH+oBvtevWOvwYTKcV4l1s=; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add the isar feature check functions we will need for v8.1M MVE: * a check for MVE present: this corresponds to the pseudocode's CheckDecodeFaults(ExtType_Mve) * a check for the optional floating-point part of MVE: this corresponds to CheckDecodeFaults(ExtType_MveFp) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 616b3932534..d037f5530fc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3801,6 +3801,28 @@ static inline bool isar_feature_aa32_fp16_arith(cons= t ARMISARegisters *id) } } =20 +static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) +{ + /* + * Return true if MVE is supported (either integer or floating point). + * We must check for M-profile as the MVFR1 field means something + * else for A-profile. + */ + return isar_feature_aa32_mprofile(id) && + FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; +} + +static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) +{ + /* + * Return true if MVE is supported (either integer or floating point). + * We must check for M-profile as the MVFR1 field means something + * else for A-profile. + */ + return isar_feature_aa32_mprofile(id) && + FIELD_EX32(id->mvfr1, MVFR1, MVE) >=3D 2; +} + static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) { /* --=20 2.20.1 From nobody Fri May 3 03:51:12 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1621524871; cv=none; d=zohomail.com; s=zohoarc; b=BgGjKGwgPixW/VNF09brBAxS2QQM9xb8KEs/y5R+Y1sSYsZwV9QFCtDqa/JEDN5la9EXI8T/w9nnrSia7RXWOUzr4p2yTC7POSHYpmYtI7bWg6I9OlxPmjZOp/nUvvCm4DxW+Qf54ZkDiWX0uNI5n6x+55nEJoN2CFdrZAhefiI= ARC-Message-Signature: i=1; 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Thu, 20 May 2021 11:34:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49584) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljkbP-0007of-BT for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:47 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:36853) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljkbN-0000eC-3s for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:47 -0400 Received: by mail-wr1-x436.google.com with SMTP id c14so16321109wrx.3 for ; Thu, 20 May 2021 08:28:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm3916126wrv.39.2021.05.20.08.28.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 08:28:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=n9p8pwMQumtdp/ZJ3zle1+NP3mYs3Ow9NwHjhceO1EI=; b=n8P1asFLSIAnOGCd12KUnDnQixup+dyPgnetfxege+3L+qcw9yd/zTN98KnM4J4w7z 9nX/zyfBH0gAX7OzatbfkEuzn/sVFe8qMsrPau++X85ip5j2e1VS/tRBCxu3FhJZeE+f yMNn/wc9Nrr62N/d1VeQcHbVogE6pcpDJON3IsApFpZaa6YZt4X3JIBwC2jgVimrendr VBQQkxsAmVhdFOOJr23nnszwzjaMRc+Yu32QWhWMM2libzd90qIKYVKO/W9mhyn36Q5i hYJ2fLLaNq0G+8nr3PgY1w3jKLuMq7IVcB7eR7mTcinesnMQodw4aQ5HdGBILiQ9h6hM NHbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n9p8pwMQumtdp/ZJ3zle1+NP3mYs3Ow9NwHjhceO1EI=; b=btsws9YAJwfjpoS1xpxGtX6ZA1t062Z3lUnciP3vO4rennFcWSmBmavPXf9QbX1EL5 2qWyu8ySTyC63fIYIsz6fKM+e0rFycVl/5375znMabPKMW8aWNeOhXwF37WeTjOqFF83 wQ2s7QMrDdpwWbFrTJTnApCb8G08Lho177pq46gfNentBUhXF1Nhch+fMGbNf5cJ+zJn BAqI7MBf7BtepD2Y/IdL57GBS5pfCxTxvkcb3zG7CbK2iZe5b+I6SZV3ICgooROl0Dtq W2ZniC2uVYZdZlNCy8yehwPEGYdHpQtDpPc/w7LJ+qU/gQ5QeSdgKcDqVtU1tv6hncy9 USqQ== X-Gm-Message-State: AOAM533sMVhlqBTCuzAV0dh8PNMcvZ1P0OIQTd3sDbQdUo0TYzHXLwM+ uDWGb7CMvtESgUPWplm7jhCvgw== X-Google-Smtp-Source: ABdhPJxraS84MoszFAYtMRiPN6MfwyuuZCIYhkLQz5GtrMOJeJk/LbcsRMkm2Airt9ULOdg6VIU9oQ== X-Received: by 2002:a5d:58d0:: with SMTP id o16mr4895414wrf.420.1621524523763; Thu, 20 May 2021 08:28:43 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/9] target/arm: Update feature checks for insns which are "MVE or FP" Date: Thu, 20 May 2021 16:28:33 +0100 Message-Id: <20210520152840.24453-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210520152840.24453-1-peter.maydell@linaro.org> References: <20210520152840.24453-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Some v8M instructions are present if either the floating point extension or MVE is implemented. Update our implementation of them to check for MVE as well as for FP. This is all the insns which use CheckDecodeFaults(ExtType_MveOrFp) or CheckDecodeFaults(ExtType_MveOrDpFp) in their pseudocode, which are essentially the loads and stores, moves and sysreg accesses, except for VMOV_reg_sp and VMOV_reg_dp, which we handle in subsequent patches because they need a refactor to provide a place to put the new MVE check. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.c | 48 +++++++++++++++++++++++--------------- 1 file changed, 29 insertions(+), 19 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 3da84f30a01..2202f8985d2 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -543,11 +543,16 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMO= V_to_gp *a) /* VMOV scalar to general purpose register */ TCGv_i32 tmp; =20 - /* SIZE =3D=3D MO_32 is a VFP instruction; otherwise NEON. */ - if (a->size =3D=3D MO_32 - ? !dc_isar_feature(aa32_fpsp_v2, s) - : !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; + /* + * SIZE =3D=3D MO_32 is a VFP instruction; otherwise NEON. MVE has + * all sizes, whether the CPU has fp or not. + */ + if (!dc_isar_feature(aa32_mve, s)) { + if (a->size =3D=3D MO_32 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } } =20 /* UNDEF accesses to D16-D31 if they don't exist */ @@ -571,11 +576,16 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_V= MOV_from_gp *a) /* VMOV general purpose register to scalar */ TCGv_i32 tmp; =20 - /* SIZE =3D=3D MO_32 is a VFP instruction; otherwise NEON. */ - if (a->size =3D=3D MO_32 - ? !dc_isar_feature(aa32_fpsp_v2, s) - : !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; + /* + * SIZE =3D=3D MO_32 is a VFP instruction; otherwise NEON. MVE has + * all sizes, whether the CPU has fp or not. + */ + if (!dc_isar_feature(aa32_mve, s)) { + if (a->size =3D=3D MO_32 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } } =20 /* UNDEF accesses to D16-D31 if they don't exist */ @@ -671,7 +681,7 @@ typedef enum FPSysRegCheckResult { =20 static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno) { - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return FPSysRegCheckFailed; } =20 @@ -1254,7 +1264,7 @@ static bool trans_VMOV_single(DisasContext *s, arg_VM= OV_single *a) { TCGv_i32 tmp; =20 - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1287,7 +1297,7 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMO= V_64_sp *a) { TCGv_i32 tmp; =20 - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1329,7 +1339,7 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMO= V_64_dp *a) * floating point register. Note that this does not require support * for double precision arithmetic. */ - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1368,7 +1378,7 @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_V= LDR_VSTR_sp *a) uint32_t offset; TCGv_i32 addr, tmp; =20 - if (!dc_isar_feature(aa32_fp16_arith, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1403,7 +1413,7 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_V= LDR_VSTR_sp *a) uint32_t offset; TCGv_i32 addr, tmp; =20 - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1439,7 +1449,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_dp *a) TCGv_i64 tmp; =20 /* Note that this does not require support for double arithmetic. */ - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1479,7 +1489,7 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_V= LDM_VSTM_sp *a) TCGv_i32 addr, tmp; int i, n; =20 - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1557,7 +1567,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) int i, n; =20 /* Note that this does not require support for double arithmetic. */ - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 --=20 2.20.1 From nobody Fri May 3 03:51:12 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1621525136; cv=none; d=zohomail.com; s=zohoarc; b=KlmRvAzBXFUhU20qKMVy3OW8FQOgeLLFNe0rxI4K4Xiq/iN2aKNejVjCRYQsBUdTLbLLnc9PSHpM6rD3xENbhw3upVvGTknjOCmJNpYupB/CFTOfupwuxPn2WinQ4grauo66VbZEp8kPPFMKvEF3cENybofJLNIIyucww20yfrk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621525136; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iTEJUgdnofezBKJEQUNY/AOGiONLkshkAXK+NJ4lu5o=; b=nkD+1knNTOmsZLw6wN/XOHn0LX/nZU8hoOXiETtsBMrsvdE7cATHXHSJ0Aw/3wTgGmTomzhqSLZ/pY7enkBzPpSYD2SG9VO2wcDLfuo6DhFlUURx1t8HVjfYgnjspFsYUqmwsZ9dBYaYQ3JZRzSu0oQF7th6x68c5m13430bWpE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1621525136889231.91175035639208; Thu, 20 May 2021 08:38:56 -0700 (PDT) Received: from localhost ([::1]:33644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljklD-0005I1-SL for importer2@patchew.org; Thu, 20 May 2021 11:38:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljkbQ-0007sQ-Jl for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:48 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:38814) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljkbN-0000eJ-RG for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:48 -0400 Received: by mail-wr1-x42d.google.com with SMTP id j14so16366992wrq.5 for ; Thu, 20 May 2021 08:28:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm3916126wrv.39.2021.05.20.08.28.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 08:28:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iTEJUgdnofezBKJEQUNY/AOGiONLkshkAXK+NJ4lu5o=; b=rA9L1IWEdQz6kRbbzmoSooSzA92L02WPC9zEgHfrLfaVYd0vQSH60iccARN20e8n+p tnb04dfNU9jMPc0cJ3rK4oNKQX6W2+TtU7ZxfsIIbXJ9pmDaEBnDvmX6kxwir1ZKHBfX eFZ2PuAfOTA0SINxFfefiCYJvU57w4Ht7jZioaZBF7bcY19rLrvfQGHksxmwKy853o1j pKDNnqr8A+5lZOVYz7JkFFgXmRIPXEyMxf+7oaQatDAnUScHCO2e++RsL9kui8hpr6yY Yi7AyqYVVKh8JDKWDQIAtTlLQV4tvaHh/WwPD+yI4RVsPOtsEUJ3F1yOGVLCnKqAivi3 2emQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iTEJUgdnofezBKJEQUNY/AOGiONLkshkAXK+NJ4lu5o=; b=byAHomcU3aVnun0rz3j8hbunjS6c6JxXw9zTN8/ucxB2XviK8qG1ujPzT9YIDnVJVD N9pydXw4UqVvhY8ExGHDvJIGM2hjYEDJMZEgo0bSMyvjoHMzHKGVX6YdBhXYDdSgQ4CU BxM7QXaq0p9kO9DmKdF1Sfw9MbVI4YuALxq9gYBh/C/IwlL6rZgYGkmHl4COiCs7PxoS +f5sZdpgc4tyN2Nnnkv6eyAD6H7Yb4nXRjlTbls1T1+H/Xc7PcSSBJgidEghuFBuognk J9gqnnwJxef6Dw6Uzy9QPF+HfX7sYuY0SQpmiZZFlxvMD3liO5fBsLfGsZEVfObCq+V3 VQ/g== X-Gm-Message-State: AOAM530vXTxrPo9ZbK6Sg1bNfsxzZNNQGseBD69Ie592ZABpxgiHcjcn rMEDKl2AMhJ8z6klKvbB0hwoqA== X-Google-Smtp-Source: ABdhPJzAyBsXOiy9eWYpeAO+zzu2krdOv41qgJdxDZ/U5OHsrwTX5MVuVtFVDy5OSV4k2lU0gJxwmA== X-Received: by 2002:adf:e384:: with SMTP id e4mr4806630wrm.347.1621524524477; Thu, 20 May 2021 08:28:44 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/9] target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp Date: Thu, 20 May 2021 16:28:34 +0100 Message-Id: <20210520152840.24453-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210520152840.24453-1-peter.maydell@linaro.org> References: <20210520152840.24453-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The do_vfp_2op_sp() and do_vfp_2op_dp() functions currently check whether floating point is supported via the aa32_fpdp_v2 and aa32_fpsp_v2 isar checks. For v8.1M MVE support, the VMOV_reg trans functions (but not any of the others) need to update this to also allow the insn if MVE is implemented. Move the check out of the do_ function and into its callsites (which are all implemented via the DO_VFP_2OP macro), so we have a place to change the check for the VMOV insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 2202f8985d2..89246a284aa 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -1925,9 +1925,7 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i32 f0, fd; =20 - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } + /* Note that the caller must check the aa32_fpsp_v2 feature. */ =20 if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { @@ -2002,6 +2000,8 @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) */ TCGv_i32 f0; =20 + /* Note that the caller must check the aa32_fp16_arith feature */ + if (!dc_isar_feature(aa32_fp16_arith, s)) { return false; } @@ -2030,9 +2030,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i64 f0, fd; =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } + /* Note that the caller must check the aa32_fpdp_v2 feature. */ =20 /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { @@ -2810,23 +2808,26 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_= VMOV_imm_dp *a) return true; } =20 -#define DO_VFP_2OP(INSN, PREC, FN) \ +#define DO_VFP_2OP(INSN, PREC, FN, CHECK) \ static bool trans_##INSN##_##PREC(DisasContext *s, \ arg_##INSN##_##PREC *a) \ { \ + if (!dc_isar_feature(CHECK, s)) { \ + return false; \ + } \ return do_vfp_2op_##PREC(s, FN, a->vd, a->vm); \ } =20 -DO_VFP_2OP(VMOV_reg, sp, tcg_gen_mov_i32) -DO_VFP_2OP(VMOV_reg, dp, tcg_gen_mov_i64) +DO_VFP_2OP(VMOV_reg, sp, tcg_gen_mov_i32, aa32_fpsp_v2) +DO_VFP_2OP(VMOV_reg, dp, tcg_gen_mov_i64, aa32_fpdp_v2) =20 -DO_VFP_2OP(VABS, hp, gen_helper_vfp_absh) -DO_VFP_2OP(VABS, sp, gen_helper_vfp_abss) -DO_VFP_2OP(VABS, dp, gen_helper_vfp_absd) +DO_VFP_2OP(VABS, hp, gen_helper_vfp_absh, aa32_fp16_arith) +DO_VFP_2OP(VABS, sp, gen_helper_vfp_abss, aa32_fpsp_v2) +DO_VFP_2OP(VABS, dp, gen_helper_vfp_absd, aa32_fpdp_v2) =20 -DO_VFP_2OP(VNEG, hp, gen_helper_vfp_negh) -DO_VFP_2OP(VNEG, sp, gen_helper_vfp_negs) -DO_VFP_2OP(VNEG, dp, gen_helper_vfp_negd) +DO_VFP_2OP(VNEG, hp, gen_helper_vfp_negh, aa32_fp16_arith) +DO_VFP_2OP(VNEG, sp, gen_helper_vfp_negs, aa32_fpsp_v2) +DO_VFP_2OP(VNEG, dp, gen_helper_vfp_negd, aa32_fpdp_v2) =20 static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm) { @@ -2843,9 +2844,9 @@ static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm) gen_helper_vfp_sqrtd(vd, vm, cpu_env); } =20 -DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp) -DO_VFP_2OP(VSQRT, sp, gen_VSQRT_sp) -DO_VFP_2OP(VSQRT, dp, gen_VSQRT_dp) +DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp, aa32_fp16_arith) +DO_VFP_2OP(VSQRT, sp, gen_VSQRT_sp, aa32_fpsp_v2) +DO_VFP_2OP(VSQRT, dp, gen_VSQRT_dp, aa32_fpdp_v2) =20 static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a) { --=20 2.20.1 From nobody Fri May 3 03:51:12 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1621524809; cv=none; d=zohomail.com; s=zohoarc; b=V1rNv8VnfXRZlrcQhTRbr9pQ+K//3UHFVERMO6Gjhgag/7l3I++zp8+2F9Ik6BHy8iXb5TF8V1h5lW9c9BxgVsj/alTVzBGmudMsMEuhwQi/jxtIca+XVEARck130OIM6MmWxDGlYs/x+DnX5eRgZA3hduEXz75LIXUevz9+Hdc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm3916126wrv.39.2021.05.20.08.28.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 08:28:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xk/LgAvvnfOjfZuNtHdhra7NwJBtH4H6uF2mN72rtJ0=; b=wUsRTHRsgrBJtxJn7OetEzWjkrUZh+C8fneyqAFZWp8r1jQgAFBQLC6E/2GzSGbwVm DIcZlH2Pwr88wmOxj+EemsCwgm3fqVv0q0Rzydgyj3KnBvN2xsZJG/TwHCblz32sbq+I RmmHNcV+FqR1pD/OcoGP+Zej18KaQ480imWrNphOHOYijFoWevjejir+iqeAa3gEZZZF 9MTCOMo3NsSPEwyw0of8pxVkBvlTfu3a1POyvNB00d+2laZ3N0DFwbljJEymgmfsMrtd fIoVMpeoNwOgdgEzWwYLxMTpuCYbHN9grX3OzXmAlJUEg3jX39bv3xOIFfCt4jobrPe8 75Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xk/LgAvvnfOjfZuNtHdhra7NwJBtH4H6uF2mN72rtJ0=; b=GVkJ9f2EBg9IMNVwj9fV6M4qqEkLqFHsFLmgm5ItoabCw6g3fZMIc4z5Z8vyD8pEEQ Xgw2vlUo4puy0X67P7Cb7ht9Pv74XWr7z94SjKYCGs0aNgxBYIqV5GttRzPFNzh0Iltm SajnlodiwjRPMV9Y7w/fV/gEix8s3YJNVDnOO2lc/JOQw1hwUAsTVP1EAYsxiORI9uab MV4MudK7LYlr+PN2W3b2JK/1BM0vqBPPJlYFOipsqB+yU9lCMuVBNbRKg+lCEtBL3MAM sOIP8ExhX5FJ9QHKvdpcpPeuhPTsaKuhqLRcJnrFxZV15T4K1KbupEwayMs3Q8ETz6oT ul0g== X-Gm-Message-State: AOAM531PzKOrB0+0GzkUoeF9OQV8n0oXyFFgJbM2fBMgRtC2HngQ85Q7 LufFk9Mdvh+RN2ZR2oLJ7qIoUCxW9TYDiQFX X-Google-Smtp-Source: ABdhPJyOx/wlAJZhrp0GO5I7vWQOHxnsHalaR/CFRRH2c93Ud7735K30uc0L8aW0S+VInkH9a5xXag== X-Received: by 2002:a05:6000:1c1:: with SMTP id t1mr4863891wrx.421.1621524525310; Thu, 20 May 2021 08:28:45 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/9] target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp Date: Thu, 20 May 2021 16:28:35 +0100 Message-Id: <20210520152840.24453-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210520152840.24453-1-peter.maydell@linaro.org> References: <20210520152840.24453-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Split out the handling of VMOV_reg_sp and VMOV_reg_dp so that we can permit the insns if either FP or MVE are present. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 89246a284aa..ac5832a4ed5 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -2818,8 +2818,19 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_V= MOV_imm_dp *a) return do_vfp_2op_##PREC(s, FN, a->vd, a->vm); \ } =20 -DO_VFP_2OP(VMOV_reg, sp, tcg_gen_mov_i32, aa32_fpsp_v2) -DO_VFP_2OP(VMOV_reg, dp, tcg_gen_mov_i64, aa32_fpdp_v2) +#define DO_VFP_VMOV(INSN, PREC, FN) \ + static bool trans_##INSN##_##PREC(DisasContext *s, \ + arg_##INSN##_##PREC *a) \ + { \ + if (!dc_isar_feature(aa32_fp##PREC##_v2, s) && \ + !dc_isar_feature(aa32_mve, s)) { \ + return false; \ + } \ + return do_vfp_2op_##PREC(s, FN, a->vd, a->vm); \ + } + +DO_VFP_VMOV(VMOV_reg, sp, tcg_gen_mov_i32) +DO_VFP_VMOV(VMOV_reg, dp, tcg_gen_mov_i64) =20 DO_VFP_2OP(VABS, hp, gen_helper_vfp_absh, aa32_fp16_arith) DO_VFP_2OP(VABS, sp, gen_helper_vfp_abss, aa32_fpsp_v2) --=20 2.20.1 From nobody Fri May 3 03:51:13 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1621525157; cv=none; d=zohomail.com; s=zohoarc; b=Lq4uSecKtC4hy5vHQyRUtB0peHno3wN5CtljDKe75zgflWY5uixHKwl8nkL8YI6QhrC+TWrzXLE9fEym7jd6WNHNztz1aNMJwzNIJqfrKF4E0bL8qBGWIlJejUsIBPqc/Af9t7Td7+hVakBTRuhHyVnXfKMbOaDEuAkc7TIc+uI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621525157; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Kn3QkvhPIEBYzulaH/PbJ8DasheOBiuundvI2boBDto=; b=YXi78cWzOVAnQc49R7gMG/RTj1vSI0gpmtfH7jCWoYgXFDILTN8wQ9tMGahtN9zh1f5K+Hzat3J5aDpWVx1QD9Rj/Wzjk4MLMsC6wrayJWKMkiSgf2L2+357dA7llzfegyfbZQV7bctdigkXYNmNT7PAreFLQfROdzoCcCvzp20= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1621525157018417.1300520955933; Thu, 20 May 2021 08:39:17 -0700 (PDT) Received: from localhost ([::1]:34516 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljklX-0005rR-Ql for importer2@patchew.org; Thu, 20 May 2021 11:39:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljkbS-00080L-Ke for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:50 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:36511) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljkbP-0000g8-MU for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:50 -0400 Received: by mail-wm1-x32e.google.com with SMTP id n17-20020a7bc5d10000b0290169edfadac9so5701290wmk.1 for ; Thu, 20 May 2021 08:28:47 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm3916126wrv.39.2021.05.20.08.28.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 08:28:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Kn3QkvhPIEBYzulaH/PbJ8DasheOBiuundvI2boBDto=; b=qyzc2Mpj5+XhPWOzuw0+RbtK2QCHdDQHMJD7NT29FDS1ANQqgW/0f5j80+yj9hjjEW nSjSom3wSBxc519uZXu6yVAS9z2Nh6+jmSkBjKwLBzr9ivdKxjq5MCR84h0r+ESbP75i FjbZ0Ck9mTsQCPfu1BdzTNCzUz7ENwlKdkn6yC3wYlCY7LF5eMv2tMQoejWmhoxZ9tOm nJCKjgzPukmo6c1sT4wZftiMD951yD+68EJcGTt1efMHGfScBJ6ANp+ClqBUM/9zA0De cQ6dpg92KOkvhBK/BjTKU8Fd0e4nxBgTBz1YNw9aqYUsQlo3PHxCqESSn6c/LjnyfEQ/ dnSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kn3QkvhPIEBYzulaH/PbJ8DasheOBiuundvI2boBDto=; b=sKZD+rSocWjxpjXdxdd58k5ZATwtJjNE33g3tN4g9OacBEAhWbR4OzEVodDThR1kBh XU3Vx0jH/ji42YYXzCepAXIRd9vf7FW3kZvECcuhFpDs4JlwpR3xBey6hovj6T/a1gQ9 d9Gx4ok6gBAZyyBdeb0cZ3hd35VGnqAYk/KYeylQNSckMG4Nui+Is+JKygEzIWEFqr1p 5YHYuH9n2C9Hqnd7SOEFvMWVmg1IslveiDfHoJEyyKpDfgvz420XrkPJaxxnvXawQ5B7 NnrAfUvjz2waXs9MVqRJLyM6DMuWI9ltB2yN7yhUfiZlP2y6EjeQnkUmKYCWvV79ZvBQ oO0A== X-Gm-Message-State: AOAM53117rQSEuV5UyPxChMdHDqhx11OU4NOGzlWyRDggyFMbEstZzU3 xMMIsyh1oqZkqXfOLhhOLgt/szVoeH8I6xQR X-Google-Smtp-Source: ABdhPJye3Uj8lof/Cmg4MM737t1gvcHD7Mgmbw8fkHeXJfS9AU4haJvpBggJppUt9WgkG+0vdCzalQ== X-Received: by 2002:a1c:7313:: with SMTP id d19mr4294854wmb.14.1621524526146; Thu, 20 May 2021 08:28:46 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/9] target/arm: Fix return values in fp_sysreg_checks() Date: Thu, 20 May 2021 16:28:36 +0100 Message-Id: <20210520152840.24453-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210520152840.24453-1-peter.maydell@linaro.org> References: <20210520152840.24453-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The fp_sysreg_checks() function is supposed to be returning an FPSysRegCheckResult, which is an enum with three possible values. However, three places in the function "return false" (a hangover from a previous iteration of the design where the function just returned a bool). Make these return FPSysRegCheckFailed instead (for no functional change, since both false and FPSysRegCheckFailed are zero). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index ac5832a4ed5..791c4f5f70b 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -691,16 +691,16 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasCont= ext *s, int regno) break; case ARM_VFP_FPSCR_NZCVQC: if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { - return false; + return FPSysRegCheckFailed; } break; case ARM_VFP_FPCXT_S: case ARM_VFP_FPCXT_NS: if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { - return false; + return FPSysRegCheckFailed; } if (!s->v8m_secure) { - return false; + return FPSysRegCheckFailed; } break; default: --=20 2.20.1 From nobody Fri May 3 03:51:13 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1621525007; cv=none; d=zohomail.com; s=zohoarc; b=hzRRE1iUWSsd5GRXg/DcGlEPppcDzdCA+auXZVvhf1bchqMCxZiifUg0PnHxba0Ktm90SrliG9PFQ980rOpTekKvNS9HKtc2axoiDHHTOttP4FbqB/C3CyuYvTQyzHM68hAy5tCvrGJyZjOZclu9Yd0JuanPWEJuI/WBkHPL2q8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621525007; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1oOgxL2tL4yDEyW5l0fIMivAaVwszzcwhe2CoFdgg/Y=; b=VjFpN0LU3WPwzXIITCBKOtpgrd7dJYoflGX8xZTFhOtOxbd0YAPpyzUArK2xk1zgh8NFRpCjvRVfeCEJOM2zFhsEyFrjxfVIzh1mvQud5tGhPdF4uo8HulHH9RhWU0rUMlck+YCLNMASQ5yAzAP+yPOljFT22olhDJvTyAvrwmI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1621525007307578.4181745020647; Thu, 20 May 2021 08:36:47 -0700 (PDT) Received: from localhost ([::1]:55738 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljkj8-0001Di-7v for importer2@patchew.org; Thu, 20 May 2021 11:36:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljkbS-00080E-IG for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:50 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:38816) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljkbQ-0000gT-A5 for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:50 -0400 Received: by mail-wm1-x32f.google.com with SMTP id u4-20020a05600c00c4b02901774b80945cso5677336wmm.3 for ; Thu, 20 May 2021 08:28:47 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm3916126wrv.39.2021.05.20.08.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 08:28:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1oOgxL2tL4yDEyW5l0fIMivAaVwszzcwhe2CoFdgg/Y=; b=LEGNv2wXcG7PQKl5P4q2u5e4ezxAdwLoApRXP5TP/AKv5OUsizDaLCKISyYSWGOPIH Q+9qo7suJjWnRtb8n3Gk7QxZ21iSd0p1B5Lit80b3uIMH262SK/uAegLx13HTsmS4vkU V3LNnRVO6pIaO7MZ2XUF1PEOGoK+8n2S21SQOHXFXqAyQficzVn9I4U78idTFR/igEq7 39okDVf1SPJZ7SPTqCxNUjIJTD9Ay21hUIMLmU8RJSXOTBl4hl82ObS8+/UsTed7/A8N qF0jvj14fVWbied4Go7PoUpwGuUWuDJyJK5vDG3kD7Sk8K1SNiMl3SZBs8Rmqpf+gFaQ s2OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1oOgxL2tL4yDEyW5l0fIMivAaVwszzcwhe2CoFdgg/Y=; b=i77FzOrp2+ieVkq/uG/FCrvMAmROUSBFMnzQlfc1OlTkU9tctRCZXXrMdlRXw3TG1V vtPwSrDW3fLXFbuLXD0ZRjTtQ5uRClJMES8ZkrZauv2DZlL+ORA1geDoUoZ6kL1u5FeC OSarNBiGsQN7TMQwZ+7h3tTRqMBwkAAlkrjcP4gVceBbK9P/0if5zPnas+T+q3JwpZav 6+bpspyUIZwnOAt9RflgV6/4j3qJnUi5/JLRg2/TpMCunMFIuwojSnMQtRKR7X2Tavpk L57HZmtxzaI+KefCLJnZS82GZ/mvisXZRaVS3/Ycc6wMTjH/ZzovPxwj9ZvpofLOT4jP mcxw== X-Gm-Message-State: AOAM531vG+oU2kOdAOj4mKqCP6InuYJpS3UShoRav5gOYF1PXw+ruFd+ 6bCtPwxk+BNHEYzwIqLIeCFLzZE6EQ+fxeWR X-Google-Smtp-Source: ABdhPJwTXYYnTh81t3G0ZtduBJ8sd1GXkMvW0fiymzD9PZ6LqC4H6rye2c+yEFwlFF3SsTWgJ+NOoA== X-Received: by 2002:a1c:bcc3:: with SMTP id m186mr4254834wmf.74.1621524526974; Thu, 20 May 2021 08:28:46 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 6/9] target/arm: Implement M-profile VPR register Date: Thu, 20 May 2021 16:28:37 +0100 Message-Id: <20210520152840.24453-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210520152840.24453-1-peter.maydell@linaro.org> References: <20210520152840.24453-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" If MVE is implemented for an M-profile CPU then it has a VPR register, which tracks predication information. Implement the read and write handling of this register, and the migration of its state. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 6 ++++++ target/arm/machine.c | 19 +++++++++++++++++++ target/arm/translate-vfp.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d037f5530fc..b0237f0dc83 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -564,6 +564,7 @@ typedef struct CPUARMState { uint32_t cpacr[M_REG_NUM_BANKS]; uint32_t nsacr; int ltpsize; + uint32_t vpr; } v7m; =20 /* Information associated with an exception about to be taken: @@ -1760,6 +1761,11 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1) R_V7M_FPCCR_UFRDY_MASK | \ R_V7M_FPCCR_ASPEN_MASK) =20 +/* v7M VPR bits */ +FIELD(V7M_VPR, P0, 0, 16) +FIELD(V7M_VPR, MASK01, 16, 4) +FIELD(V7M_VPR, MASK23, 20, 4) + /* * System register ID fields. */ diff --git a/target/arm/machine.c b/target/arm/machine.c index 6ad1d306b12..62a71a3b640 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -318,6 +318,24 @@ static const VMStateDescription vmstate_m_fp =3D { } }; =20 +static bool mve_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + return cpu_isar_feature(aa32_mve, cpu); +} + +static const VMStateDescription vmstate_m_mve =3D { + .name =3D "cpu/m/mve", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D mve_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(env.v7m.vpr, ARMCPU), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_m =3D { .name =3D "cpu/m", .version_id =3D 4, @@ -344,6 +362,7 @@ static const VMStateDescription vmstate_m =3D { &vmstate_m_other_sp, &vmstate_m_v8m, &vmstate_m_fp, + &vmstate_m_mve, NULL } }; diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 791c4f5f70b..2316e105acc 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -703,6 +703,12 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasConte= xt *s, int regno) return FPSysRegCheckFailed; } break; + case ARM_VFP_VPR: + case ARM_VFP_P0: + if (!dc_isar_feature(aa32_mve, s)) { + return FPSysRegCheckFailed; + } + break; default: return FPSysRegCheckFailed; } @@ -817,6 +823,25 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int= regno, tcg_temp_free_i32(sfpa); break; } + case ARM_VFP_VPR: + /* Behaves as NOP if not privileged */ + if (IS_USER(s)) { + break; + } + tmp =3D loadfn(s, opaque); + store_cpu_field(tmp, v7m.vpr); + break; + case ARM_VFP_P0: + { + TCGv_i32 vpr; + tmp =3D loadfn(s, opaque); + vpr =3D load_cpu_field(v7m.vpr); + tcg_gen_deposit_i32(vpr, vpr, tmp, + R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); + store_cpu_field(vpr, v7m.vpr); + tcg_temp_free_i32(tmp); + break; + } default: g_assert_not_reached(); } @@ -935,6 +960,19 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int = regno, tcg_temp_free_i32(fpscr); break; } + case ARM_VFP_VPR: + /* Behaves as NOP if not privileged */ + if (IS_USER(s)) { + break; + } + tmp =3D load_cpu_field(v7m.vpr); + storefn(s, opaque, tmp); + break; + case ARM_VFP_P0: + tmp =3D load_cpu_field(v7m.vpr); + tcg_gen_extract_i32(tmp, tmp, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LEN= GTH); + storefn(s, opaque, tmp); + break; default: g_assert_not_reached(); } --=20 2.20.1 From nobody Fri May 3 03:51:13 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1621525091; cv=none; d=zohomail.com; s=zohoarc; b=IYXw/c5Vvbgj0JFxQFGXvQ8hxXEdgh11YiYDuNx14T8aO8qU83de7DPcgvkq766LBrhFa1N3j0EYWNqI9AlTXj/CQQv9cLpWIlUfC3kPx3UWXCf4yfw8BiIX/4uBM7eAaefFIWi5t+4FSPqHTx0AY0xhgebMhsKbX+DtW5I54ts= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621525091; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UgJyl6SmpghGPffAzR64zbb98zEqURj95gernOR9oB4=; b=fguldwPA3H3i5JMTHw6v+rd3abMJjOj12uog2N7yENqZbBQ7RA9ds0r/44Csi+Pq1jDdx/RAIdRXjyB0vb15GJm2my5h/B01SLSe7Bi9RYHtUUsI2+HFVXzrcgT/ms9j/Fwm4zt7xBI9SPPCvp74KThLgl0owB9olShnxMPgtrA= ARC-Authentication-Results: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm3916126wrv.39.2021.05.20.08.28.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 08:28:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UgJyl6SmpghGPffAzR64zbb98zEqURj95gernOR9oB4=; b=ltOff0KfVmFfHNnp9Q6l6JrPCOGaOOzh1ZotQ/fmpAcmhFRPxxhQeN/IGm+Dqnz/gE /ux3Ic6wIt7MLuQFWRRwsHS4L2RQzEqI7Ol3RgB9wrxTIwYIBRMf0Hu1DTGngjubYL7Z /fzLLbi+zkVqK/GJ2loXtIu4UmwNztUgvDyRTfqPQuQY7+GCi3VIYWIhTbio1N0s8ByP cC10blu4mFbs6PVjpGPy5P/ML1sVh9CrsFrSLcYVEDbUJi52MXQdZT9Jg5mv47Nq1x6v vOOgynulybouxM31s2BYBDybNmXOLm5VyD5Df0uPQJdGKw0kU16D2jNUndyvJM8sJ1Ia Jv8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UgJyl6SmpghGPffAzR64zbb98zEqURj95gernOR9oB4=; b=RKpwko5scy//F16ubgKASMFkRooVTdTW7GMvFW/xFdPissIHYr1MlMR6QdDUK51RuG In9QhRB0aS9CDYSJ6ZPqkEtjYNSx8N5dRGsesX0J9VlYgKKetE8N+b/UtmqdC8CqmOmH MFerZ/jQl8xu+pd+47lWkrlDXBiu8agGGmqO1/gGbCO9HuYrfC97hwrtF8QGll1b4Nbn /MzudO0SHisOr/Us1X+VvgeYUoiX5Rla8u4I/p0ayM29tKxMdaFuvKT1xeIkPtTcWKDP gu8E1KVfID7a67F2bZxMRoQjlolyG/WXRWugfHKPqIkLKPmHWnv/7s1Mw+MEeH2T3arD 9JHg== X-Gm-Message-State: AOAM533d2hIdF4adBmNnC8C9wTk8k0ws5IQqJY9hIl1XQn+3vgfa944B 1uMwvcauR7bMhDULTN7z+aQJ0w== X-Google-Smtp-Source: ABdhPJyHRhlZN19k7D3+xBCkdk/lfkczfhY6G2sv1zXXmCei8h4SccPpxiGK2cLvuDZbuGDPWQKCdQ== X-Received: by 2002:a05:600c:221a:: with SMTP id z26mr4709920wml.122.1621524527742; Thu, 20 May 2021 08:28:47 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 7/9] target/arm: Make FPSCR.LTPSIZE writable for MVE Date: Thu, 20 May 2021 16:28:38 +0100 Message-Id: <20210520152840.24453-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210520152840.24453-1-peter.maydell@linaro.org> References: <20210520152840.24453-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The M-profile FPSCR has an LTPSIZE field, but if MVE is not implemented it is read-only and always reads as 4; this is how QEMU currently handles it. Make the field writable when MVE is implemented. We can safely add the field to the MVE migration struct because currently no CPUs enable MVE and so the migration struct is never used. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 3 ++- target/arm/machine.c | 1 + target/arm/vfp_helper.c | 9 ++++++--- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b0237f0dc83..0e33db88240 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -563,7 +563,7 @@ typedef struct CPUARMState { uint32_t fpdscr[M_REG_NUM_BANKS]; uint32_t cpacr[M_REG_NUM_BANKS]; uint32_t nsacr; - int ltpsize; + uint32_t ltpsize; uint32_t vpr; } v7m; =20 @@ -1561,6 +1561,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); =20 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) +#define FPCR_LTPSIZE_LENGTH 3 =20 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) diff --git a/target/arm/machine.c b/target/arm/machine.c index 62a71a3b640..81e30de8243 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -332,6 +332,7 @@ static const VMStateDescription vmstate_m_mve =3D { .needed =3D mve_needed, .fields =3D (VMStateField[]) { VMSTATE_UINT32(env.v7m.vpr, ARMCPU), + VMSTATE_UINT32(env.v7m.ltpsize, ARMCPU), VMSTATE_END_OF_LIST() }, }; diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 01b9d8557f7..e0886ab5a56 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -195,8 +195,10 @@ uint32_t vfp_get_fpscr(CPUARMState *env) =20 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { + ARMCPU *cpu =3D env_archcpu(env); + /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(any_fp16, env_archcpu(env))) { + if (!cpu_isar_feature(any_fp16, cpu)) { val &=3D ~FPCR_FZ16; } =20 @@ -210,11 +212,12 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t= val) * because in v7A no-short-vector-support cores still had to * allow Stride/Len to be written with the only effect that * some insns are required to UNDEF if the guest sets them. - * - * TODO: if M-profile MVE implemented, set LTPSIZE. */ env->vfp.vec_len =3D extract32(val, 16, 3); env->vfp.vec_stride =3D extract32(val, 20, 2); + } else if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.ltpsize =3D extract32(val, FPCR_LTPSIZE_SHIFT, + FPCR_LTPSIZE_LENGTH); } =20 if (arm_feature(env, ARM_FEATURE_NEON)) { --=20 2.20.1 From nobody Fri May 3 03:51:13 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1621525262; cv=none; d=zohomail.com; s=zohoarc; b=Iuo1b2g70jx5trKJGLcmgfB2xqPhzTAcKld49iyzg7f+lXNapp0bW7cAHk9UGjW+ps1XBToViUiMoE5ZBRTSULxlQfn9uQcYDDw5yoRFkjxaublv7NAF27V2jZqVTbvTtYjk9OCtRPNb0mEv7fRjRHNsZcOl/udxQXy684BNk9M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621525262; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nycRzRnC22+MMRKklZmpFxoGXgNbpGqBimi8PnwOL/E=; b=cGojWMS7H07hp4tOBXcDgy1VrEtrXc4pwbWp0VpefNREBx1Da48CV+SH9rd/VzmNVBYhmHYSZ+nGzQdyT6VerClyvz+VcztRVMloYWvcA1UA9kKwGjGLTe3mX0rhS8iKoXiAw/x+ms7v7/xXoQZiJ0+kHj3WGbbZiS4QRgvt6Zw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162152526285152.39272225397883; Thu, 20 May 2021 08:41:02 -0700 (PDT) Received: from localhost ([::1]:41190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljknF-0001wU-Ql for importer2@patchew.org; Thu, 20 May 2021 11:41:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljkbW-0008Hb-Vb for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:55 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:50747) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljkbR-0000hT-Sd for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:54 -0400 Received: by mail-wm1-x32c.google.com with SMTP id t206so9468229wmf.0 for ; Thu, 20 May 2021 08:28:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm3916126wrv.39.2021.05.20.08.28.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 08:28:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nycRzRnC22+MMRKklZmpFxoGXgNbpGqBimi8PnwOL/E=; b=AaPDH5X8ibid2VkKdGpr8XjN4Mbsf0ECm3KzJ1doR2AIHpYo2t8vDOOm58xtVGln+V tpPV05U6xQOTafqiSzzAy1F1rfZsqN7g1/QOCxMHjtKU6RF9tp4by80HlWzHwASYMvDG yksU0+6gI5d+zkTxKXXsaHaQcJrqcB8e1NgxRGNdMAWTiIWRC0LSgRzvA2IhvdOSr8jI 8S1oPwTMDh3zpPUOi888AtjU2Uz99Sn/f2BPySFHZAqTXrOt+JSbiVBNKwWqEPOqGqUM PVRlY34/7QNQiOAC60jqe6djMHQQLiGLD5XUV+lNUPEhlcf30Kg6PRBNEs/udtrgpvgH eWqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nycRzRnC22+MMRKklZmpFxoGXgNbpGqBimi8PnwOL/E=; b=BZZtgcPkltsa7Qdr5XbNVTmne9Kqyy+VDuxsFr1lwaVJebcqNKp7WNOkBmd+V1BPib iuF6L6iMgoB+4KNpr0Fzb06ACYv6TSll6OZHeM38KQr14k5r2NeY+/9kWLcMspLVsLB9 sXFaMMfXz8iVdewS6I6S67srkFNWZhNzVHDgnNnQE1Kf7Mtr+/AI5EftIP/ICPqrDxlK xddFbe9bVDr+BPooSarNbmtDzRZNdO6l8k4GganjYTPXdzHl2T9VYaXvCwM66nrb8rjN XW/DSqU8kYZCHwRrQ1w4O2/GgMIuhE8e3Y8zRaXfJOVgeS4s3tqb/QIRtE/sFudxPI5a wJZg== X-Gm-Message-State: AOAM533qv1TjYN7yhUV6d1Iw0yYmNiYiHozGDdlA/IQ2fES1YoLtRCrR vTe1rMRLTLrzFiPXEsP86cOaLZPW4fI8dv6t X-Google-Smtp-Source: ABdhPJxpja45Ak1JyfOFSbCLhsYLfpdgwbjpClzZrxQNoRZr6Dj7NNeSAbyl9+hY0VAXr3yFt6Gehg== X-Received: by 2002:a1c:4602:: with SMTP id t2mr4488851wma.173.1621524528475; Thu, 20 May 2021 08:28:48 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 8/9] target/arm: Enable FPSCR.QC bit for MVE Date: Thu, 20 May 2021 16:28:39 +0100 Message-Id: <20210520152840.24453-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210520152840.24453-1-peter.maydell@linaro.org> References: <20210520152840.24453-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" MVE has an FPSCR.QC bit similar to the A-profile Neon one; when MVE is implemented make the bit writeable. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/vfp_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index e0886ab5a56..11e1e087e81 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -220,7 +220,8 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t v= al) FPCR_LTPSIZE_LENGTH); } =20 - if (arm_feature(env, ARM_FEATURE_NEON)) { + if (arm_feature(env, ARM_FEATURE_NEON) || + cpu_isar_feature(aa32_mve, cpu)) { /* * The bit we set within fpscr_q is arbitrary; the register as a * whole being zero/non-zero is what counts. --=20 2.20.1 From nobody Fri May 3 03:51:13 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1621525196; cv=none; d=zohomail.com; s=zohoarc; b=dAcuU9OQBLZ6Ng3wcs1OVerJqHI9D3vga3mfTuG150L2KvFrB6ax53NZw/rEmMriDvKWULSkSC4/0N9yiutulu3sSozhOTWpS5CUSHEnfn6X7xxiGwlJQ8b4UXNrL+0iK88xeIYwkfLVStUJXwzylSWHqnISaHZjxHeBCycYCsM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621525196; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PEqMXhVTCuRe0JtaB2Xv9j94Ph2CmIe5jNctvMp+E7g=; b=V8EOx0WPnFWZnHVDASaykf4aCTq2Hbnm/i5tUXafVHkpCZ7flBHbte950IM9JEg7QtjAwDrVuCLi3Zoq3wKCTAjfZG4ki8l8SOUjVZL+EvIWwl8FHCzAnrCrzaw3rfTmcvMaQWyuqdYQf1o4Ew65Fc49ZvzjBX3gyx9l+dQCS98= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1621525196564108.46031165109275; Thu, 20 May 2021 08:39:56 -0700 (PDT) Received: from localhost ([::1]:37698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljkmB-0007zd-Gh for importer2@patchew.org; Thu, 20 May 2021 11:39:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49780) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljkbV-00089y-AF for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:53 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:50751) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljkbS-0000iA-Us for qemu-devel@nongnu.org; Thu, 20 May 2021 11:28:53 -0400 Received: by mail-wm1-x330.google.com with SMTP id t206so9468265wmf.0 for ; Thu, 20 May 2021 08:28:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm3916126wrv.39.2021.05.20.08.28.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 08:28:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PEqMXhVTCuRe0JtaB2Xv9j94Ph2CmIe5jNctvMp+E7g=; b=AChR9As+LwNxnJJGr+XOWQPoitDm0bQlsGZYsOwUzApt24opiHBW1dMs741cO/9UxG +DQr8cNUprZh1apLUJfKgz67TS8/BBFvI2B7yvSju813MqD06d9FCCRVfIDpHoZyV/+8 XPXSK+fccKRKwTyXRmsuai5HxwNMzhaYfyXyEVckkN+PZv8YWLFUAec312xCkmRN6C4u e2vXJMPeaW5ZGe6/ljHzHft/0Q5UV9xdBGNzim4Wbwn3M+BUcP0pgqcTitxMEAzH6XkR dFcStwIknjQkpwd4zz4I/LirQ4+si8XX+pTi8b8C3GBzoGltOMYRE2Evx0d2c0y3jKNK oZOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PEqMXhVTCuRe0JtaB2Xv9j94Ph2CmIe5jNctvMp+E7g=; b=ZkIJaBXaPUypkyVq2kKBOavieSqOgvPR3wEv4kstb2XCRNqbgRQtEK8/sIG1nwOTJ6 0g/4y98/3iibbnK88uXWONDKbQyVj23dsHfTkE9FMp6kUi3U9pqwiFvmr8T6QVPA5rbj exDoUOnBGwjxvvJbBhDaQx6qOf6ToXwBTOyE4pjzmgorO9nxHrW4RZA5WyybqrQvW+4s vHCgW67cjY7E4LLzjJ3KR7FD4i1ajHHQaj0CFD2UX7UeUZx6UTrRXTeyIG/XNmB+AMao x6pktnQyMRcMPPttvzzGHMEklrR3UdIId413t2pRB9CSdFLGgwmbGlg0nJuB3lOWMm/O IUyg== X-Gm-Message-State: AOAM531keCq0guhZKyEvUYpeKuJoh264fkkP9zWf8kZK4g2/d3I7viH7 s4QLOxW1+O1KTlzjWmp8LvObwg== X-Google-Smtp-Source: ABdhPJylCAaiRgXLNA/239zTwY4brz/qttEpSMGGyNwCmG/SFslwsie6kLl1yfqFxpvwfcmtZw9yfQ== X-Received: by 2002:a1c:4482:: with SMTP id r124mr4722902wma.42.1621524529333; Thu, 20 May 2021 08:28:49 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 9/9] target/arm: Allow board models to specify initial NS VTOR Date: Thu, 20 May 2021 16:28:40 +0100 Message-Id: <20210520152840.24453-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210520152840.24453-1-peter.maydell@linaro.org> References: <20210520152840.24453-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Currently we allow board models to specify the initial value of the Secure VTOR register, using an init-svtor property on the TYPE_ARMV7M object which is plumbed through to the CPU. Allow board models to also specify the initial value of the Non-secure VTOR via a similar init-nsvtor property. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- I admit to not having a publicly-visible use for this yet, but it does bring the NSVTOR into line with both our handling of the SVTOR and also with the hardware, which allows both to be set via reset-time config signal inputs, as seen eg on the Cortex-M55: https://developer.arm.com/documentation/101051/0002/Signal-descriptions/Res= et-configuration-signals?lang=3Den --- include/hw/arm/armv7m.h | 2 ++ target/arm/cpu.h | 2 ++ hw/arm/armv7m.c | 7 +++++++ target/arm/cpu.c | 10 ++++++++++ 4 files changed, 21 insertions(+) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 189b23a8ceb..bc6733c5184 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -46,6 +46,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) * devices will be automatically layered on top of this view.) * + Property "idau": IDAU interface (forwarded to CPU object) * + Property "init-svtor": secure VTOR reset value (forwarded to CPU obje= ct) + * + Property "init-nsvtor": non-secure VTOR reset value (forwarded to CPU= object) * + Property "vfp": enable VFP (forwarded to CPU object) * + Property "dsp": enable DSP (forwarded to CPU object) * + Property "enable-bitband": expose bitbanded IO @@ -69,6 +70,7 @@ struct ARMv7MState { MemoryRegion *board_memory; Object *idau; uint32_t init_svtor; + uint32_t init_nsvtor; bool enable_bitband; bool start_powered_off; bool vfp; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0e33db88240..af67e2bf2e3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -869,6 +869,8 @@ struct ARMCPU { =20 /* For v8M, initial value of the Secure VTOR */ uint32_t init_svtor; + /* For v8M, initial value of the Non-secure VTOR */ + uint32_t init_nsvtor; =20 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU typ= e. diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index af0d935bf78..9ce5c30cd5c 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -176,6 +176,12 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) return; } } + if (object_property_find(OBJECT(s->cpu), "init-nsvtor")) { + if (!object_property_set_uint(OBJECT(s->cpu), "init-nsvtor", + s->init_nsvtor, errp)) { + return; + } + } if (object_property_find(OBJECT(s->cpu), "start-powered-off")) { if (!object_property_set_bool(OBJECT(s->cpu), "start-powered-off", s->start_powered_off, errp)) { @@ -254,6 +260,7 @@ static Property armv7m_properties[] =3D { MemoryRegion *), DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Objec= t *), DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0), + DEFINE_PROP_UINT32("init-nsvtor", ARMv7MState, init_nsvtor, 0), DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false), DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off, false), diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4eb0d2f85c4..167c4feee4b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -327,6 +327,7 @@ static void arm_cpu_reset(DeviceState *dev) env->regs[14] =3D 0xffffffff; =20 env->v7m.vecbase[M_REG_S] =3D cpu->init_svtor & 0xffffff80; + env->v7m.vecbase[M_REG_NS] =3D cpu->init_nsvtor & 0xffffff80; =20 /* Load the initial SP and PC from offset 0 and 4 in the vector ta= ble */ vecbase =3D env->v7m.vecbase[env->v7m.secure]; @@ -1272,6 +1273,15 @@ void arm_cpu_post_init(Object *obj) &cpu->init_svtor, OBJ_PROP_FLAG_READWRITE); } + if (arm_feature(&cpu->env, ARM_FEATURE_M)) { + /* + * Initial value of the NS VTOR (for cores without the Security + * extension, this is the only VTOR) + */ + object_property_add_uint32_ptr(obj, "init-nsvtor", + &cpu->init_nsvtor, + OBJ_PROP_FLAG_READWRITE); + } =20 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); =20 --=20 2.20.1