From nobody Sun Apr 28 06:54:46 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622052833; cv=none; d=zohomail.com; s=zohoarc; b=ImRbmvvA1SKd4mZS/8E+fhdzshEcH69v6ZZ/A/tb3NTw9wOBe9KhnU8r6YQVckJor/+giGrnpQ7CJRdq19fpQ9M8glLtLslWaJdfOO2feKTJK6LV4o0O+hyt5Vw1U+aHRZNora0KcKeChmNAWlCfT7KJa/oJa6bigMBLIpo4TgQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622052833; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=/2slS83H/aRsUNXYyk0GZQ476x3p1VMv3SQLoPSvmvQ=; b=Uf6avG8ndqgPUnHN0lOnGeXbGOkYMlES5jU+bRMKo9cH0Eei3E88GMg6ADIOUIcKOphdCSmItx+uSZ0CllY9nxt3isRAxzydbb/gPloUwLHDnH7BHgOukFNB/ZTkt8Q4jW6zzXwI/Z99RZnPYy8nIPfl/Z4YmNaLV2UHUe+wgmA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622052833950699.1779113430357; Wed, 26 May 2021 11:13:53 -0700 (PDT) Received: from localhost ([::1]:52832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lly2S-0000vy-Qm for importer2@patchew.org; Wed, 26 May 2021 14:13:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54992) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1llxnO-0002fp-7X; Wed, 26 May 2021 13:58:18 -0400 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]:35363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1llxnM-0006yc-Ei; Wed, 26 May 2021 13:58:18 -0400 Received: by mail-ej1-x635.google.com with SMTP id k14so3861680eji.2; Wed, 26 May 2021 10:58:15 -0700 (PDT) Received: from neptune.lab ([81.200.23.112]) by smtp.googlemail.com with ESMTPSA id hp1sm10407449ejc.96.2021.05.26.10.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 10:58:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/2slS83H/aRsUNXYyk0GZQ476x3p1VMv3SQLoPSvmvQ=; b=e9cetxDT3L7X6m9fkLb2t2Zv2Ei5c+7COVLX6iTwVleu7oIhDlRGM7tuZT9mg03kbj vWCvXfY5i+gmeY0b5U+55EPWsZfsSLTiIKaEvbEphSY7wSHp5R2HjVGMbDNC9qeM7bBZ NAjc3UMK8sj7v1HwhziG80v/k8wWFTgrkDibg3LePgLOyS6Ctc9gfekxcL08OwBvEzTy MlKRcYddb4NEKyIAPHGIZJtxusoL63oewJFmjaTyAuuj1moPZPj8kLw/OGrVqv0zAsvP ACK3u9l9LOpEmNcH5Js2AdFMpO/IWe/ccBDovKm92syW+I79JJQNhQJKMBIkI8KFDol/ B2uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/2slS83H/aRsUNXYyk0GZQ476x3p1VMv3SQLoPSvmvQ=; b=gUsCWTlsEnkUGJb/djF2KMvnvR9K5fb5dmIAhsDodHOg7WyR7m+TTstmGjlvpNSnI2 y6igRi/r5F0+bYqr4AjJh/EyE5a97yAnbjcHBQ/UHADgXiFAsliDUQ/2YZpXJIdxKW27 Yp3WubSuVEYocmjKmKcnf/9p04k41p3YzH3xFlG34chOlwcXHZk5xR85jr/KA8Id5pvZ iWElM0KY11pVyzf9TZls6P2gWkuNeBH2cdg2qicU1O033tuWqV+zJpCYqUvRdnTCfc9T 5GY2WxTyq00TV6PJ4a/B0ThFqfcOiWWcvQVMwePikLrl1cKP/EfazW/QWDyLz81/6YVM 4abg== X-Gm-Message-State: AOAM5304arM9bJGd2Kkqotc4stL4obKLGsq8b/ZfpfqhFZPtN8KiwuYv FotSGmWazJpUzOOaVpVhNZw= X-Google-Smtp-Source: ABdhPJywYWT97er0w0PgPK0PhMUSc9Q9DeWJ7k8rDERn6d40afZEQs5+T/WHt5OZp3kMB+rd3Sz1Fw== X-Received: by 2002:a17:906:80ce:: with SMTP id a14mr9696934ejx.311.1622051893961; Wed, 26 May 2021 10:58:13 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v9 1/6] [RISCV_PM] Add J-extension into RISC-V Date: Wed, 26 May 2021 20:57:43 +0300 Message-Id: <20210526175749.25709-2-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210526175749.25709-1-space.monkey.delivers@gmail.com> References: <20210526175749.25709-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, Bin Meng , richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair Francis , kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7e879fb9ca..1673872223 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,6 +67,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVJ RV('J') =20 /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -286,6 +287,7 @@ struct RISCVCPU { bool ext_s; bool ext_u; bool ext_h; + bool ext_j; bool ext_v; bool ext_counters; bool ext_ifencei; --=20 2.20.1 From nobody Sun Apr 28 06:54:46 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622053569; cv=none; d=zohomail.com; s=zohoarc; b=RRr2ySZ9/rIVfMAmbNO2f6DRwej3iwwiugsyfab7YVpPy0SOi0/7Ca9d/zlpGIlNqiQC41y4QGzsfN0D6rXq9LRO7quZPRuEn2BL2uuXsrZhOkXfsZdRCxXjtgI1YJHP0jbhUP6Sb7DLGHJmFFK+9rQOUOXwraqD2kYX4jbcSZA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622053569; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=/1EBiKW2umZFELd/QvlDNITpP1fUzdZ8FY3fiwv+fWc=; b=YvJNr5XRA1zZjNlfzweKFX0MR9nqXCzz7/w+br1q79umqlJmM/r0AKBgsn/Dd3pDTBfqYxlQXfOkqFHFCvfPxbucJedlDmV92QqE/TLr5KxWvIeTcYZHjzbR90jGfkNqeqPHiG88n7MAWKlmugb4OsGvK5sKapqJcPmIeghugMk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622053569091778.8780034590741; Wed, 26 May 2021 11:26:09 -0700 (PDT) Received: from localhost ([::1]:45864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1llyEJ-0007N3-Ts for importer2@patchew.org; Wed, 26 May 2021 14:26:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55008) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1llxnQ-0002hk-RB; Wed, 26 May 2021 13:58:21 -0400 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]:42770) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1llxnM-0006zH-WA; Wed, 26 May 2021 13:58:20 -0400 Received: by mail-ej1-x62a.google.com with SMTP id lg14so3814544ejb.9; Wed, 26 May 2021 10:58:16 -0700 (PDT) Received: from neptune.lab ([81.200.23.112]) by smtp.googlemail.com with ESMTPSA id hp1sm10407449ejc.96.2021.05.26.10.58.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 10:58:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/1EBiKW2umZFELd/QvlDNITpP1fUzdZ8FY3fiwv+fWc=; b=vA3Q1ZnB+iu/hPTi8NPf7BFLq70zDIOn4zpLsEtdC/t+6CjwBJq422zpSAfEjh1hNt s7h1b16gia6to4Lyzsfjr10oMxCf0K84LqXsJSh+W1mVTHHYSbwqxD+3BkoZvHrJL2Is LxXsnxz37OjnB41E11TtgTewNye6PWmGmDnocbapKhnhu7bXEVv9vzacwMURip/2t+nK b33aGfXYa78gbW8ML8dCCCmE7Bt8LvGENLM9EbZbRNVwWLIuv0vBxOqF51MFsWIqpJq8 vzLat20AaDqvYbPs7w+Q1Ixg70gYrqqw0KwSJgiWiMvARHi6vXRNeVZ2zO5m+2uyE32o qk7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/1EBiKW2umZFELd/QvlDNITpP1fUzdZ8FY3fiwv+fWc=; b=K2QwJYp/wTnxjptemeUDm/nfKXQAxtxugWUq91Nrv340DU7D2z1IGRENwIEokq4VtX pnIF7yFTo6sLjsUyOKjh4X9KpSjIkzcqkw31pFQx3Pmkvpdo2wP5z5WKjuQYoEEukaxv Ia66xxe2pViUAd1D1RiCCsp4Rwuecr1FhlYoyxcfdXufKZ7Z+uuDl18rgNmDHpOjdSgy eZPmMavAcPlDZz9yQ85sxuSezlMI4iO217A+bUuYF5IFKbTOjIz/Xq5lOgUcovp3gj77 keA/jA5tO+iUZleiv0+I3oxgTc/jqySg3pt9Y8jydcakTDqRZyXd6+nrwxZzFkJXNYni db5Q== X-Gm-Message-State: AOAM531c7ugOwqA0KuVRDU2Amwjw30t3/1aNH/NcCRKezfLnMbu7z0AM bvQtHEN8IFVfdEmCM0ku7yRlfxey90JoqpawC0o= X-Google-Smtp-Source: ABdhPJwOd81Dup/GFxwnhKJ1X+CXvQj+lCNwkVq1TIiQx6VC4RjFSJMoRgcCfvmP4Q5+bOzGQV9n2w== X-Received: by 2002:a17:906:b104:: with SMTP id u4mr34495173ejy.211.1622051895207; Wed, 26 May 2021 10:58:15 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v9 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode Date: Wed, 26 May 2021 20:57:44 +0300 Message-Id: <20210526175749.25709-3-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210526175749.25709-1-space.monkey.delivers@gmail.com> References: <20210526175749.25709-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, Bin Meng , richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair Francis , kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 6 + target/riscv/cpu.h | 12 ++ target/riscv/cpu_bits.h | 97 +++++++++++++ target/riscv/csr.c | 306 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 421 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3191fd0082..9841711e71 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -486,6 +486,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) if (cpu->cfg.ext_h) { target_misa |=3D RVH; } + if (cpu->cfg.ext_j) { +#ifndef CONFIG_USER_ONLY + /* mmte is supposed to have pm.current hardwired to 1 */ + env->mmte |=3D (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); +#endif + } if (cpu->cfg.ext_v) { target_misa |=3D RVV; if (!is_power_of_2(cpu->cfg.vlen)) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1673872223..a68e523d87 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -233,6 +233,18 @@ struct CPURISCVState { =20 /* True if in debugger mode. */ bool debugger; + + /* + * CSRs for PointerMasking extension + * TODO: move these csr to appropriate groups + */ + target_ulong mmte; + target_ulong mpmmask; + target_ulong mpmbase; + target_ulong spmmask; + target_ulong spmbase; + target_ulong upmmask; + target_ulong upmbase; #endif =20 float_status fp_status; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 52640e6856..97e2aa8a97 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -334,6 +334,39 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f =20 + +/* + * User PointerMasking registers + * NB: actual CSR numbers might be changed in future + */ +#define CSR_UMTE 0x4c0 +#define CSR_UPMMASK 0x4c1 +#define CSR_UPMBASE 0x4c2 + +/* + * Machine PointerMasking registers + * NB: actual CSR numbers might be changed in future + */ +#define CSR_MMTE 0x3c0 +#define CSR_MPMMASK 0x3c1 +#define CSR_MPMBASE 0x3c2 + +/* + * Supervisor PointerMaster registers + * NB: actual CSR numbers might be changed in future + */ +#define CSR_SMTE 0x1c0 +#define CSR_SPMMASK 0x1c1 +#define CSR_SPMBASE 0x1c2 + +/* + * Hypervisor PointerMaster registers + * NB: actual CSR numbers might be changed in future + */ +#define CSR_VSMTE 0x2c0 +#define CSR_VSPMMASK 0x2c1 +#define CSR_VSPMBASE 0x2c2 + /* mstatus CSR bits */ #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 @@ -530,4 +563,68 @@ typedef enum RISCVException { #define MIE_UTIE (1 << IRQ_U_TIMER) #define MIE_SSIE (1 << IRQ_S_SOFT) #define MIE_USIE (1 << IRQ_U_SOFT) + +/* General PointerMasking CSR bits*/ +#define PM_ENABLE 0x00000001ULL +#define PM_CURRENT 0x00000002ULL +#define PM_INSN 0x00000004ULL +#define PM_XS_MASK 0x00000003ULL + +/* PointerMasking XS bits values */ +#define PM_EXT_DISABLE 0x00000000ULL +#define PM_EXT_INITIAL 0x00000001ULL +#define PM_EXT_CLEAN 0x00000002ULL +#define PM_EXT_DIRTY 0x00000003ULL + +/* Offsets for every pair of control bits per each priv level */ +#define XS_OFFSET 0ULL +#define U_OFFSET 2ULL +#define S_OFFSET 5ULL +#define M_OFFSET 8ULL + +#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET) +#define U_PM_ENABLE (PM_ENABLE << U_OFFSET) +#define U_PM_CURRENT (PM_CURRENT << U_OFFSET) +#define U_PM_INSN (PM_INSN << U_OFFSET) +#define S_PM_ENABLE (PM_ENABLE << S_OFFSET) +#define S_PM_CURRENT (PM_CURRENT << S_OFFSET) +#define S_PM_INSN (PM_INSN << S_OFFSET) +#define M_PM_ENABLE (PM_ENABLE << M_OFFSET) +#define M_PM_CURRENT (PM_CURRENT << M_OFFSET) +#define M_PM_INSN (PM_INSN << M_OFFSET) + +/* mmte CSR bits */ +#define MMTE_PM_XS_BITS PM_XS_BITS +#define MMTE_U_PM_ENABLE U_PM_ENABLE +#define MMTE_U_PM_CURRENT U_PM_CURRENT +#define MMTE_U_PM_INSN U_PM_INSN +#define MMTE_S_PM_ENABLE S_PM_ENABLE +#define MMTE_S_PM_CURRENT S_PM_CURRENT +#define MMTE_S_PM_INSN S_PM_INSN +#define MMTE_M_PM_ENABLE M_PM_ENABLE +#define MMTE_M_PM_CURRENT M_PM_CURRENT +#define MMTE_M_PM_INSN M_PM_INSN +#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INS= N | \ + MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INS= N | \ + MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INS= N | \ + MMTE_PM_XS_BITS) + +/* (v)smte CSR bits */ +#define SMTE_PM_XS_BITS PM_XS_BITS +#define SMTE_U_PM_ENABLE U_PM_ENABLE +#define SMTE_U_PM_CURRENT U_PM_CURRENT +#define SMTE_U_PM_INSN U_PM_INSN +#define SMTE_S_PM_ENABLE S_PM_ENABLE +#define SMTE_S_PM_CURRENT S_PM_CURRENT +#define SMTE_S_PM_INSN S_PM_INSN +#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INS= N | \ + SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INS= N | \ + SMTE_PM_XS_BITS) + +/* umte CSR bits */ +#define UMTE_U_PM_ENABLE U_PM_ENABLE +#define UMTE_U_PM_CURRENT U_PM_CURRENT +#define UMTE_U_PM_INSN U_PM_INSN +#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_IN= SN) + #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fe5628fea6..e1c5bb9c35 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -192,6 +192,16 @@ static RISCVException hmode32(CPURISCVState *env, int = csrno) =20 } =20 +/* Checks if PointerMasking registers could be accessed */ +static RISCVException pointer_masking(CPURISCVState *env, int csrno) +{ + /* Check if j-ext is present */ + if (riscv_has_ext(env, RVJ)) { + return RISCV_EXCP_NONE; + } + return RISCV_EXCP_ILLEGAL_INST; +} + static RISCVException pmp(CPURISCVState *env, int csrno) { if (riscv_feature(env, RISCV_FEATURE_PMP)) { @@ -1420,6 +1430,289 @@ static RISCVException write_pmpaddr(CPURISCVState *= env, int csrno, return RISCV_EXCP_NONE; } =20 +/* + * Functions to access Pointer Masking feature registers + * We have to check if current priv lvl could modify + * csr in given mode + */ +static int check_pm_current_disabled(CPURISCVState *env, int csrno) +{ + int csr_priv =3D get_field(csrno, 0x300); + /* + * If priv lvls differ that means we're accessing csr from higher priv= lvl, + * so allow the access + */ + if (env->priv !=3D csr_priv) { + return 0; + } + int cur_bit_pos; + switch (env->priv) { + case PRV_M: + cur_bit_pos =3D M_PM_CURRENT; + break; + case PRV_S: + cur_bit_pos =3D S_PM_CURRENT; + break; + case PRV_U: + cur_bit_pos =3D U_PM_CURRENT; + break; + default: + g_assert_not_reached(); + } + int pm_current =3D get_field(env->mmte, cur_bit_pos); + /* It's same priv lvl, so we allow to modify csr only if pm.current=3D= =3D1 */ + return !pm_current; +} + +static RISCVException read_mmte(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mmte & MMTE_MASK; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mmte(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + target_ulong wpri_val =3D val & MMTE_MASK; + if (val !=3D wpri_val) { + qemu_log_mask(LOG_GUEST_ERROR, + "MMTE: WPRI violation written 0x%lx vs expected 0x%l= x\n", + val, wpri_val); + } + /* for machine mode pm.current is hardwired to 1 */ + wpri_val |=3D MMTE_M_PM_CURRENT; + /* hardwiring pm.instruction bit to 0, since it's not supported yet */ + wpri_val &=3D ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); + env->mmte =3D wpri_val | PM_EXT_DIRTY; + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus =3D env->mstatus; + if (riscv_cpu_is_32bit(env)) { + mstatus =3D set_field(mstatus, MSTATUS32_SD, 1); + } else { + mstatus =3D set_field(mstatus, MSTATUS64_SD, 1); + } + env->mstatus |=3D MSTATUS_XS; + env->mstatus =3D mstatus; + return RISCV_EXCP_NONE; +} + +static RISCVException read_smte(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mmte & SMTE_MASK; + return RISCV_EXCP_NONE; +} + +static RISCVException write_smte(CPURISCVState *env, int csrno, + target_ulong val) +{ + target_ulong wpri_val =3D val & SMTE_MASK; + if (val !=3D wpri_val) { + qemu_log_mask(LOG_GUEST_ERROR, + "SMTE: WPRI violation written 0x%lx vs expected 0x%l= x\n", + val, wpri_val); + } + /* if pm.current=3D=3D0 we can't modify current PM CSRs */ + if (check_pm_current_disabled(env, csrno)) { + return RISCV_EXCP_NONE; + } + target_ulong new_val =3D wpri_val | (env->mmte & ~SMTE_MASK); + write_mmte(env, csrno, new_val); + return RISCV_EXCP_NONE; +} + +static RISCVException read_umte(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mmte & UMTE_MASK; + return RISCV_EXCP_NONE; +} + +static RISCVException write_umte(CPURISCVState *env, int csrno, + target_ulong val) +{ + target_ulong wpri_val =3D val & UMTE_MASK; + if (val !=3D wpri_val) { + qemu_log_mask(LOG_GUEST_ERROR, + "UMTE: WPRI violation written 0x%lx vs expected 0x%l= x\n", + val, wpri_val); + } + if (check_pm_current_disabled(env, csrno)) { + return RISCV_EXCP_NONE; + } + target_ulong new_val =3D wpri_val | (env->mmte & ~UMTE_MASK); + write_mmte(env, csrno, new_val); + return RISCV_EXCP_NONE; +} + +static RISCVException read_mpmmask(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mpmmask; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mpmmask(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + env->mpmmask =3D val; + env->mmte |=3D PM_EXT_DIRTY; + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus =3D env->mstatus; + if (riscv_cpu_is_32bit(env)) { + mstatus =3D set_field(mstatus, MSTATUS32_SD, 1); + } else { + mstatus =3D set_field(mstatus, MSTATUS64_SD, 1); + } + env->mstatus |=3D MSTATUS_XS; + env->mstatus =3D mstatus; + return RISCV_EXCP_NONE; +} + +static RISCVException read_spmmask(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->spmmask; + return RISCV_EXCP_NONE; +} + +static RISCVException write_spmmask(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + /* if pm.current=3D=3D0 we can't modify current PM CSRs */ + if (check_pm_current_disabled(env, csrno)) { + return RISCV_EXCP_NONE; + } + env->spmmask =3D val; + env->mmte |=3D PM_EXT_DIRTY; + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus =3D env->mstatus; + if (riscv_cpu_is_32bit(env)) { + mstatus =3D set_field(mstatus, MSTATUS32_SD, 1); + } else { + mstatus =3D set_field(mstatus, MSTATUS64_SD, 1); + } + env->mstatus |=3D MSTATUS_XS; + env->mstatus =3D mstatus; + return RISCV_EXCP_NONE; +} + +static RISCVException read_upmmask(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->upmmask; + return RISCV_EXCP_NONE; +} + +static RISCVException write_upmmask(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + /* if pm.current=3D=3D0 we can't modify current PM CSRs */ + if (check_pm_current_disabled(env, csrno)) { + return RISCV_EXCP_NONE; + } + env->upmmask =3D val; + env->mmte |=3D PM_EXT_DIRTY; + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus =3D env->mstatus; + if (riscv_cpu_is_32bit(env)) { + mstatus =3D set_field(mstatus, MSTATUS32_SD, 1); + } else { + mstatus =3D set_field(mstatus, MSTATUS64_SD, 1); + } + env->mstatus |=3D MSTATUS_XS; + env->mstatus =3D mstatus; + return RISCV_EXCP_NONE; +} + +static RISCVException read_mpmbase(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mpmbase; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mpmbase(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + env->mpmbase =3D val; + env->mmte |=3D PM_EXT_DIRTY; + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus =3D env->mstatus; + if (riscv_cpu_is_32bit(env)) { + mstatus =3D set_field(mstatus, MSTATUS32_SD, 1); + } else { + mstatus =3D set_field(mstatus, MSTATUS64_SD, 1); + } + env->mstatus |=3D MSTATUS_XS; + env->mstatus =3D mstatus; + return RISCV_EXCP_NONE; +} + +static RISCVException read_spmbase(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->spmbase; + return RISCV_EXCP_NONE; +} + +static RISCVException write_spmbase(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + /* if pm.current=3D=3D0 we can't modify current PM CSRs */ + if (check_pm_current_disabled(env, csrno)) { + return RISCV_EXCP_NONE; + } + env->spmbase =3D val; + env->mmte |=3D PM_EXT_DIRTY; + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus =3D env->mstatus; + if (riscv_cpu_is_32bit(env)) { + mstatus =3D set_field(mstatus, MSTATUS32_SD, 1); + } else { + mstatus =3D set_field(mstatus, MSTATUS64_SD, 1); + } + env->mstatus |=3D MSTATUS_XS; + env->mstatus =3D mstatus; + return RISCV_EXCP_NONE; +} + +static RISCVException read_upmbase(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->upmbase; + return RISCV_EXCP_NONE; +} + +static RISCVException write_upmbase(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + /* if pm.current=3D=3D0 we can't modify current PM CSRs */ + if (check_pm_current_disabled(env, csrno)) { + return RISCV_EXCP_NONE; + } + env->upmbase =3D val; + env->mmte |=3D PM_EXT_DIRTY; + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus =3D env->mstatus; + if (riscv_cpu_is_32bit(env)) { + mstatus =3D set_field(mstatus, MSTATUS32_SD, 1); + } else { + mstatus =3D set_field(mstatus, MSTATUS64_SD, 1); + } + env->mstatus |=3D MSTATUS_XS; + env->mstatus =3D mstatus; + return RISCV_EXCP_NONE; +} + #endif =20 /* @@ -1652,6 +1945,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_PMPADDR14] =3D { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR15] =3D { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, =20 + /* User Pointer Masking */ + [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write= _umte }, + [CSR_UPMMASK] =3D { "upmmask", pointer_masking, read_upmmask, write= _upmmask }, + [CSR_UPMBASE] =3D { "upmbase", pointer_masking, read_upmbase, write= _upmbase }, + /* Machine Pointer Masking */ + [CSR_MMTE] =3D { "mmte", pointer_masking, read_mmte, write= _mmte }, + [CSR_MPMMASK] =3D { "mpmmask", pointer_masking, read_mpmmask, write= _mpmmask }, + [CSR_MPMBASE] =3D { "mpmbase", pointer_masking, read_mpmbase, write= _mpmbase }, + /* Supervisor Pointer Masking */ + [CSR_SMTE] =3D { "smte", pointer_masking, read_smte, write= _smte }, + [CSR_SPMMASK] =3D { "spmmask", pointer_masking, read_spmmask, write= _spmmask }, + [CSR_SPMBASE] =3D { "spmbase", pointer_masking, read_spmbase, write= _spmbase }, + /* Performance Counters */ [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_zero }, [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_zero }, --=20 2.20.1 From nobody Sun Apr 28 06:54:46 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622054523; cv=none; d=zohomail.com; s=zohoarc; b=mKolrjfSN2WU9IPAA5RRIosAx/uzcSLq8YgpSuxF8h13YeUs18fzdO7vzQfU6GnigtqgGEo7kiW+Ucl6AMPD7i9ntaKwcOos4/QnqLZbF57yPTPjrp4r7kOG4fc+oaK/MldN8VzQRMue7yZJvLjK7zBSD1p5YtIGKGudmowSUMI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622054523; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=6P47nwDyYtXSKtHDGnpN6mD0yBf3ZQehoCf7mlzEQWo=; b=mHzJF/AHnV2rfB4wUviPDfB3Qe0pbiqFR+hhOrECPIr5gEDLBaaYU2ABjviDf08+U/8thY2lBkYAixSlNeQbZJXQ3ZKOo4lw21mLLYtNxVFxTwLZKxzwt1dXbnFuRudEQzw1wYNooAyBCh8Sqib+vuQz4wNbgkhW1zXXgf2emrg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622054523794429.19136552214877; Wed, 26 May 2021 11:42:03 -0700 (PDT) Received: from localhost ([::1]:52394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1llyTi-0005mO-P8 for importer2@patchew.org; Wed, 26 May 2021 14:42:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1llxnS-0002ia-Ct; Wed, 26 May 2021 13:58:22 -0400 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]:38836) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1llxnO-0006zt-12; Wed, 26 May 2021 13:58:22 -0400 Received: by mail-ed1-x52c.google.com with SMTP id o5so2590021edc.5; Wed, 26 May 2021 10:58:17 -0700 (PDT) Received: from neptune.lab ([81.200.23.112]) by smtp.googlemail.com with ESMTPSA id hp1sm10407449ejc.96.2021.05.26.10.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 10:58:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6P47nwDyYtXSKtHDGnpN6mD0yBf3ZQehoCf7mlzEQWo=; b=kuLqa/g8R1bB/Z2QvBwUTrzR3b1H/fX4o+zz/W2idN7b30HH03NaIMUsqJcnBEl+6A mzJyykLO8WhLyDbW0NPByJ/mf1EsngEaVgEi37ViOpj/YSBMGA9J6z1A4K+zIhY7P8p1 +fv1Vs1Q1Sv4IvklVeIs0c8MryTZzC1QLSXd8Ufgo9p233BVLTILxIBIlAYRluFp1T1s AHDmfh1SBeVZZwQ7lrCMoLz9tqbzInBkaWOil2XANwvWqxvdTuJE+xzUBLqW2Al83Zjn x8/Nm9k7q7sWuEWANr0M6LJQH4QWFG1TwtGBRpoPWwUPdBwZBOgyf0HxJm6iFvxZijjW 3yNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6P47nwDyYtXSKtHDGnpN6mD0yBf3ZQehoCf7mlzEQWo=; b=nHnLBwbeJrJw6DzYsUGG82V4UFM9C8CGAynBmSoW1nkWIzldudY2HbHtt2D9LTLXns YPzTdVblouJXO6W5D5OF3rnz9q9cDsXLiPm/ie+j4e2vtNwrPtiv4z90PxqSo3vB5aKf Y4DqqUQanX+LBEvPF2ubebRa/eKLu4lXSDaTvgqn1gO6R+JAe1JAJdtvtDWqbpkzoALN YuO6kTFsMFQ7kskWXD2Gp6JtuKmhd8sVqPQiJzi+PwSVPr9yFdn6JAqmDdUQT74/5IAy 1hxMR2WwGHSrBVc+QlGoE9Ysk+wQLcLsj4TRDklseUvSMcj2XRZKKmo3GazpciG+3G8j nveQ== X-Gm-Message-State: AOAM532h04K9ogwAn1CGPb1/U2mdVBaYUcKtazbJjmHJ+rD6piorQ+z0 jsIuHgL2axVbTB0nPje9aYA= X-Google-Smtp-Source: ABdhPJx0KvfvKH6xvkKIEu3F++n/8StWX2kak4PlpZxJgNOT3GWj6IY4xxW1AISZrPbkT2ON0vhz8w== X-Received: by 2002:a05:6402:14c2:: with SMTP id f2mr39945039edx.69.1622051896453; Wed, 26 May 2021 10:58:16 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v9 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs Date: Wed, 26 May 2021 20:57:45 +0300 Message-Id: <20210526175749.25709-4-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210526175749.25709-1-space.monkey.delivers@gmail.com> References: <20210526175749.25709-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=baturo.alexey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, Bin Meng , richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair Francis , kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9841711e71..25e28e9b95 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -292,6 +292,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f= , int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); } + if (riscv_has_ext(env, RVJ)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte); + switch (env->priv) { + case PRV_U: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ", + env->upmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ", + env->upmmask); + break; + case PRV_S: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ", + env->spmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ", + env->spmmask); + break; + case PRV_M: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ", + env->mpmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ", + env->mpmmask); + break; + default: + g_assert_not_reached(); + } + } #endif =20 for (i =3D 0; i < 32; i++) { --=20 2.20.1 From nobody Sun Apr 28 06:54:46 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622053769; cv=none; d=zohomail.com; s=zohoarc; b=k9KIvop2q5YfLvXKsIWRUl1LCZJmYoaIuPUO7NJizJGoD+8Jih1REEbhN6p8XV958STsSV944t4tP532kSlBafoyM/B33bG8TuLV9rYROADahOqk2cYr+GMPcatb6VEV7xxP7LPGObsEBZOGQiWOAXDUXjk/2sH9Ny41bGiCrGQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622053769; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=UrdK90AxJe0VQhnSQVLd85RJr//QkA1RW/MAOEcI6Os=; b=OnpEwHp7WZ0e+0Kbcb373RiEln2g2Vw5OoPK23ZwXg2bppnnho7PUtrvAZtEfZq7yUT9RyA9/6xUcSUVZFoUL9ly6IWBSMDHCPTMwdb0X5Zhw7usc9T/xq6O15S8iW03qu5I5la55+5BOJvi0gUWFx56coLmr3Doe0UtXhqEdnM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622053769162495.564643352482; Wed, 26 May 2021 11:29:29 -0700 (PDT) Received: from localhost ([::1]:54288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1llyHX-0004fx-49 for importer2@patchew.org; Wed, 26 May 2021 14:29:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55046) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1llxnT-0002mr-Jk; Wed, 26 May 2021 13:58:23 -0400 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:35355) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1llxnQ-00071b-Sx; Wed, 26 May 2021 13:58:23 -0400 Received: by mail-ej1-x62b.google.com with SMTP id k14so3862084eji.2; Wed, 26 May 2021 10:58:19 -0700 (PDT) Received: from neptune.lab ([81.200.23.112]) by smtp.googlemail.com with ESMTPSA id hp1sm10407449ejc.96.2021.05.26.10.58.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 10:58:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UrdK90AxJe0VQhnSQVLd85RJr//QkA1RW/MAOEcI6Os=; b=GIX21iQNLVE3MnFULnui3qTibfCV5XXgejBtTtWUHbcWrVb4tmAbA3chfrCj/bh0C8 hoyIqBkfJwKcYZMrtJD4Biz60SXWKzwnavWgdMLSfzmgkIvBuB/oeoYkEdLdNemJSfxd k5GvE2z4U2VGI8GUeGliIcT8qiHih3qr9cUVQc5JIuyc7QJxJbxwPRiXevwSDyQMA10l 11oOSgNqd4UNZD+Hue8rjtewiONzBSlQH44KXBgRlTh2JBYllmN5DTU20cpwCf3GkcEL L/Ck2/L1bCsBRuCEFEtf3wIUabyynJNcci4+/tFRkvIDx5d/hRt7ryaBjEjbgMYmrT/g CzpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UrdK90AxJe0VQhnSQVLd85RJr//QkA1RW/MAOEcI6Os=; b=Y5drmARysO9VPSdkdkx9Oh4W4ncUwWB3BVaRzv3/AcfAUwCIB67MfF/GhlGVJ5RwfN MThH37KIPmaSpAZlmslwOQbYS22U4Dv3Ry0xp+7wRDi2kvWORaKZGwhlwQLJ951btifJ vx2J5KCvLMbGviTPXsbHcMiS6VrPbqJvfGPwpSbI5VsR+KLiyQBC4W3QVeMFegrqQSNr MPviN2SCw8NBNhO1NvAhtAinYj6OIyv9J+zRHbaQLTKfoLEMVzeBT+WnYSOG3rMxaieu FQEEVuTT+6dXajHJUon36yqyG1+Iazxnb7wpgpN0aG6qqCl0T2F/S1+cC8XFNxVrT3yv bebQ== X-Gm-Message-State: AOAM532GEtRyo9448PmV0F1kdQ8qV5BSRjfiCdMAPOgvjzoaZmKiSA+G KawfVdJaZnE9Egbs7NeaPFs= X-Google-Smtp-Source: ABdhPJwbZBIFB7vKvDiFZNuyiWZrWkSHblUWS7XVllOn+PtZm5gfKKKmptI4jVwCNamVVarz7/NBlQ== X-Received: by 2002:a17:907:2071:: with SMTP id qp17mr34707361ejb.15.1622051898824; Wed, 26 May 2021 10:58:18 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v9 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Date: Wed, 26 May 2021 20:57:46 +0300 Message-Id: <20210526175749.25709-5-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210526175749.25709-1-space.monkey.delivers@gmail.com> References: <20210526175749.25709-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, GAPPY_SUBJECT=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, Bin Meng , richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair Francis , kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/translate.c | 10 ++++++++++ 5 files changed, 19 insertions(+) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index ab2ec4f0a5..e8879a1a6b 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -26,6 +26,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *= a, MemOp mop) if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } + gen_pm_adjust_address(ctx, src1, src1); tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); if (a->aq) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -46,6 +47,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *= a, MemOp mop) TCGLabel *l2 =3D gen_new_label(); =20 gen_get_gpr(src1, a->rs1); + gen_pm_adjust_address(ctx, src1, src1); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); =20 gen_get_gpr(src2, a->rs2); @@ -91,6 +93,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, gen_get_gpr(src1, a->rs1); gen_get_gpr(src2, a->rs2); =20 + gen_pm_adjust_address(ctx, src1, src1); (*func)(src2, src1, src2, ctx->mem_idx, mop); =20 gen_set_gpr(a->rd, src2); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 7e45538ae0..27a89d7f96 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -25,6 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) TCGv t0 =3D tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); =20 tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); =20 @@ -40,6 +41,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) TCGv t0 =3D tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); =20 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); =20 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index db1c0c9974..d81548a359 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -30,6 +30,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) TCGv t0 =3D tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); =20 tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); @@ -47,6 +48,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) gen_get_gpr(t0, a->rs1); =20 tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); =20 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index bd93f634cf..df5749352d 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -147,6 +147,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemO= p memop) TCGv t1 =3D tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); gen_set_gpr(a->rd, t1); @@ -186,6 +187,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, Mem= Op memop) TCGv dat =3D tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); gen_get_gpr(dat, a->rs2); =20 tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e945352bca..2e94d58651 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -94,6 +94,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); } =20 +/* + * Temp stub: generates address adjustment for PointerMasking + */ +static void gen_pm_adjust_address(DisasContext *s, + TCGv_i64 dst, + TCGv_i64 src) +{ + tcg_gen_mov_i64(dst, src); +} + /* * A narrow n-bit operation, where n < FLEN, checks that input operands * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. --=20 2.20.1 From nobody Sun Apr 28 06:54:46 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622053228; cv=none; d=zohomail.com; s=zohoarc; b=lMP5ZMJ1gu6lmczU2FuceuQ8Ch83+b2E9LeSFq9urHmf4ylxEpi4niYMqNWipQPRoi0GjnLhAf1pp9EW/i3oS1/TQnXeYWYD1R9ghWh1j1KaCz1F6pqIdU26ELPbXsobaIeuucd20252/IiLKxnak8X5Mfc3udUJ3k/izi26oHg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622053228; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=33F4ua5IT/jNcL6V6m6aBX0F3Jg04e5hV8J5pPkHUw0=; b=fvA3fJazaQ+MRNokwCZfzlXwa7F/XPyTy7kU1FSc0ooUJXu0jfAJRTKjghV9J8zV4oVG/QsCBcnvdd9u4XanSdWYrxHCrfta/lVVoqK+tl/VZM0MKOOQ5HRhv4mZbbPhdZ2sX7SVTkVpzsyRLylhbCWtIxaz2dq5l4u6Uv8s7y8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622053228511873.4483753924839; Wed, 26 May 2021 11:20:28 -0700 (PDT) Received: from localhost ([::1]:33952 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lly8o-0007TH-9Y for importer2@patchew.org; Wed, 26 May 2021 14:20:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55056) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1llxnU-0002oc-6Q; Wed, 26 May 2021 13:58:24 -0400 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:43587) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1llxnR-00071h-Tu; Wed, 26 May 2021 13:58:23 -0400 Received: by mail-ej1-x629.google.com with SMTP id f18so3798565ejq.10; Wed, 26 May 2021 10:58:21 -0700 (PDT) Received: from neptune.lab ([81.200.23.112]) by smtp.googlemail.com with ESMTPSA id hp1sm10407449ejc.96.2021.05.26.10.58.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 10:58:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=33F4ua5IT/jNcL6V6m6aBX0F3Jg04e5hV8J5pPkHUw0=; b=NQnZAwKivbtM3qnZWReAGAFhtTRiisA/wKdWAmP+9hhSZcX3ik88DeT4Zl8S33Tn2n Slb9irf1xQuOye8nZLZ9UbTBGNH5ou6GlRN4vwwwvC8Nhk+bqYx8yIXZ1shD3yyQ1W6w Gkx/HYV/ZN5+pSJICVBMSDPTx1XEC0KD5LslrMN/pn5gkUo8NS9lkFOHvUe/6ad7Jq/q NuUz2oMUvxTqD2Vrem3YAI/7GLn3rd3I/mmDjOK0qcHOGuoZPZZiZBheYIN37No+MGLH CyAIVfKYLDSPOw9zcnOGOxD9kvwSrOpSB7q0BFch8vbVNIeFUYulQD0HKMlg8afZkuiz OhBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=33F4ua5IT/jNcL6V6m6aBX0F3Jg04e5hV8J5pPkHUw0=; b=byeGvMYe5XeK5i1ga5OwVMvQnSK7wC262gimS5HIbBeeipH91mZjfBOFN35YGXfnh4 w1hJUhbu40wEbFFbL6kar+3IZwfAbbTqfZGhgXPODQR7LtubDIdiXbjDNnT7ThSau7dK p2+msaSi77lKMYXg+ybKaKtl6ikOQsQAksXrddObsPLrW8UKD1XhdTIFKarMyPxUuv0n C/yEPB1tWpX5fsKLKPnVvgqIJM129tsjqE3XRzMGR0LVzw7+5gHrGb7B7hC2ya9dqThn 5qOOkj430d0nPJUYudX9sxzvVr4x5VHUQp3/zpzUto5aLrkBXQwnYzxucgDd5A2xO+O0 iL8A== X-Gm-Message-State: AOAM5333YHfP7hNNG+VElttekG/BbPzjrA5GAe8ZE4Xty9jxUuG8XcFA nHFjdDxy2uL0N6fGQKzP0No= X-Google-Smtp-Source: ABdhPJyw1mcGIRsze3jq7i5cPouwy8SFmls1822SrkY5aVKjPoiD6LPo5xYAiTTvEoSu0eZPN5ugEw== X-Received: by 2002:a17:906:4a5a:: with SMTP id a26mr33467903ejv.548.1622051900153; Wed, 26 May 2021 10:58:20 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v9 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Date: Wed, 26 May 2021 20:57:47 +0300 Message-Id: <20210526175749.25709-6-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210526175749.25709-1-space.monkey.delivers@gmail.com> References: <20210526175749.25709-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, Bin Meng , richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair Francis , kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 20 ++++++++++++++++++++ target/riscv/translate.c | 36 ++++++++++++++++++++++++++++++++++-- 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a68e523d87..d29857846c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -403,6 +403,8 @@ FIELD(TB_FLAGS, SEW, 5, 3) FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) +/* If PointerMasking should be applied */ +FIELD(TB_FLAGS, PM_ENABLED, 10, 1) =20 bool riscv_cpu_is_32bit(CPURISCVState *env); =20 @@ -460,6 +462,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } } + if (riscv_has_ext(env, RVJ)) { + int priv =3D cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK; + bool pm_enabled =3D false; + switch (priv) { + case PRV_U: + pm_enabled =3D env->mmte & U_PM_ENABLE; + break; + case PRV_S: + pm_enabled =3D env->mmte & S_PM_ENABLE; + break; + case PRV_M: + pm_enabled =3D env->mmte & M_PM_ENABLE; + break; + default: + g_assert_not_reached(); + } + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled); + } #endif =20 *pflags =3D flags; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2e94d58651..a6bc4e764e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; +/* globals for PM CSRs */ +static TCGv pm_mask[4]; +static TCGv pm_base[4]; =20 #include "exec/gen-icount.h" =20 @@ -64,6 +67,10 @@ typedef struct DisasContext { uint16_t vlen; uint16_t mlen; bool vl_eq_vlmax; + /* PointerMasking extension */ + bool pm_enabled; + TCGv pm_mask; + TCGv pm_base; CPUState *cs; } DisasContext; =20 @@ -95,13 +102,19 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) } =20 /* - * Temp stub: generates address adjustment for PointerMasking + * Generates address adjustment for PointerMasking */ static void gen_pm_adjust_address(DisasContext *s, TCGv_i64 dst, TCGv_i64 src) { - tcg_gen_mov_i64(dst, src); + if (!s->pm_enabled) { + /* Load unmodified address */ + tcg_gen_mov_i64(dst, src); + } else { + tcg_gen_andc_i64(dst, src, s->pm_mask); + tcg_gen_or_i64(dst, dst, s->pm_base); + } } =20 /* @@ -669,6 +682,10 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen =3D 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->pm_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); + int priv =3D cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK; + ctx->pm_mask =3D pm_mask[priv]; + ctx->pm_base =3D pm_base[priv]; ctx->cs =3D cs; } =20 @@ -789,4 +806,19 @@ void riscv_translate_init(void) "load_res"); load_val =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_= val), "load_val"); +#ifndef CONFIG_USER_ONLY + /* Assign PM CSRs to tcg globals */ + pm_mask[PRV_U] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmma= sk"); + pm_base[PRV_U] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmba= se"); + pm_mask[PRV_S] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmma= sk"); + pm_base[PRV_S] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmba= se"); + pm_mask[PRV_M] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmma= sk"); + pm_base[PRV_M] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmba= se"); +#endif } --=20 2.20.1 From nobody Sun Apr 28 06:54:46 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622053477; cv=none; d=zohomail.com; s=zohoarc; b=B37ez9ezVR9GP9X0YcO//7oMrvFNE62gPogJKC0LLgdcjsQBWVuPAfqit/NVY4oNw5eUKvQQd5o7uMF1jkifbgSRcKgSDgvz9tFbyJjUyM5lrZF9fMa95bs0171W+N20KUNh/3A1E7D8wc6ILH0bDwx/xIJ/j5rxianrgOgkteA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622053477; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=MU3JTu3rmDbZc+WwTSzdujwDE0KKZH6TsSTAfE4l5Ts=; b=WN1kywmQR0MRbhZesa0m0Ri4TN6T7Ke8rLqtCd3WnWK7h1E1TVl8WpAkWbL1a5ijUePUPE1LqbRtC0+lvje0F38IFJcRJsKSwR4BbTLB3wYHTl9zemtvwiB+zkK50X8U41tz59rWdeO0BmTUFpW8hXQXuKUprds901/m7vluYE0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162205347738045.027800605141124; Wed, 26 May 2021 11:24:37 -0700 (PDT) Received: from localhost ([::1]:42724 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1llyCq-0005C5-7q for importer2@patchew.org; Wed, 26 May 2021 14:24:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55060) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1llxnU-0002qj-Ow; Wed, 26 May 2021 13:58:24 -0400 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]:47059) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1llxnT-00071w-1y; Wed, 26 May 2021 13:58:24 -0400 Received: by mail-ej1-x636.google.com with SMTP id b9so3801093ejc.13; Wed, 26 May 2021 10:58:22 -0700 (PDT) Received: from neptune.lab ([81.200.23.112]) by smtp.googlemail.com with ESMTPSA id hp1sm10407449ejc.96.2021.05.26.10.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 10:58:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MU3JTu3rmDbZc+WwTSzdujwDE0KKZH6TsSTAfE4l5Ts=; b=eqEoCViOy06LqnwtyLVD1S0Vo+k3cARfcpcaQ4tpEnNH/YYxUeLuA6pkyxuc0aDL02 +pUY9Js58RrwVgPiS64Ww2IDxwb32M3OJmrZtkHMcR747O4SlSLWkesZlRXusZInytPj NMuJg3H8dLaAOkH1V9bT2L3+kegQx44nmqPXz6VcSuV07C9jukXz+edjnmiQ9TxFV8FW AbwtTIWhO/BxM7ZWLQGOr5THC7vQGvnXbfB3PghA/FonAec4BKgDPIWwxCPdOCijOZYi by1HkfFRIfwq56SfOT4ZxrSsrtqIYvXmXJn3+LOk0SIIiiAmSpo9kU83unfbf3ZI+Dda aMfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MU3JTu3rmDbZc+WwTSzdujwDE0KKZH6TsSTAfE4l5Ts=; b=ABIExqPvX/RjI21yjMcbqrarpMI3+duHiYEZxW3ZNpvU7zOrC4yHR6Fxc7bPGzyEKR fPAic55RuQpgC5SGS00bKzJAcl42yBctmQ64+8gvQqwi0jnSziVJHAcNxWe8KUrGXLff E0H+OmiNw+58pCqH9cJBEPW+yONpXZQvR6qrSgRIepnoXJfgVhQ6WVRd7aCz1AfR/Iit jZJ97BIZpGV/TwiSKBoNTRPj/CbxaGulZqEFAzk4oMdh4qpiRJ3y/dd6Y3zVZSEn5o5B GnCwnTHwu4GH7lNKRc1AXVs880WXGy/AI3WXqI1Xfd7Nknywbx0FE3L0jhMGfqbggRNQ wFOA== X-Gm-Message-State: AOAM53351+fv0pdN86iYDxbrsmJJLB+6vvF0/5348KNIQnDCY06ZABP0 2l5ZUikN3t4h90J2x+dSvX8= X-Google-Smtp-Source: ABdhPJwk6OQRE0rsO7LB9XCgo0g0lw1LvO3O949JB1hVuPuJdLlW+58ZYe10KsaIh63sB3ErfyQAtQ== X-Received: by 2002:a17:906:5fca:: with SMTP id k10mr35682346ejv.357.1622051901293; Wed, 26 May 2021 10:58:21 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v9 6/6] [RISCV_PM] Allow experimental J-ext to be turned on Date: Wed, 26 May 2021 20:57:48 +0300 Message-Id: <20210526175749.25709-7-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210526175749.25709-1-space.monkey.delivers@gmail.com> References: <20210526175749.25709-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, Bin Meng , richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair Francis , kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 25e28e9b95..21a96ec366 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -516,6 +516,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) /* mmte is supposed to have pm.current hardwired to 1 */ env->mmte |=3D (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); #endif + target_misa |=3D RVJ; } if (cpu->cfg.ext_v) { target_misa |=3D RVV; @@ -588,6 +589,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), --=20 2.20.1