From nobody Sat Apr 27 17:20:31 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622109250; cv=none; d=zohomail.com; s=zohoarc; b=NU3IBh+wDX+HwJmWaLp6IjD/58tBoDa+ftezRaVyjVpuWL1irjrfRqLg4xXX8tBqBVk73QseY4KmtUwt3QH7PfhPVyVZCNdUq0lE0eyOBFISlGNDgxaQQzxwNhFTRZTTQpKhMBLzdEPjfSod4ns26mmEcejdYT8yecxKoRSWvkY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622109250; h=Content-Transfer-Encoding:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=G5B5hvCGISwVvcSmxDpwJiBIsP15U0MlpZf6BrKPNX8=; b=hM81pGZOzj4Cal9WGuFsHi2mwF2F0GqvazVbOimAVKAuKOEexV1g8uw19GGUYJ/iH/0EAdmNNUDc9kBXDctFcsVZg4TxVr2D6R9nwL0bwO7LL7EGy42pTfMQrMfPPTZCyEFVMk1EyiURzkqefBhxuN/azhrgsMqkmfq/RcgJq6g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622109250932290.32685881732937; Thu, 27 May 2021 02:54:10 -0700 (PDT) Received: from localhost ([::1]:57384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lmCiP-0007O9-Tr for importer2@patchew.org; Thu, 27 May 2021 05:54:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52400) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lmCgL-0006Ii-Eq for qemu-devel@nongnu.org; Thu, 27 May 2021 05:52:01 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:38431) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lmCgG-0002zy-E3 for qemu-devel@nongnu.org; Thu, 27 May 2021 05:52:01 -0400 Received: by mail-wr1-x42b.google.com with SMTP id j14so4076950wrq.5 for ; Thu, 27 May 2021 02:51:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y14sm2357589wrr.82.2021.05.27.02.51.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 02:51:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=G5B5hvCGISwVvcSmxDpwJiBIsP15U0MlpZf6BrKPNX8=; b=YCx3w/RAumGPZ6rdVTx27h7SNU8eZKEGfKNYJBwOaIiscpmNBLkbBvrjCq3U4IpWLF 1oSY0LXwPZt9WtTzoUTKfPE9GzVNXPi1LDbzcVXoCPQNRAQE8ZfVCVIncBvWGIIMK87M EHimicMHaRvA3sX9sXZCB6lUqFEBoHlE8/sf2sgb7vxx04vCVU5qR69IL9ZgTfiYyVY8 Xj9+z3IyiVlxfEtysGrJVdjhWObjMfcp6rHrKIxsvFmASbG1JjB/MoVCkj/wNV7dbF3r ME6giU47bdqdBOaIqm2nkHON8tESme0ZEqd4ARvZsIcSgBSjmNBc9jlClhHDVgc30+/U SoZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=G5B5hvCGISwVvcSmxDpwJiBIsP15U0MlpZf6BrKPNX8=; b=K/uH++SLqljquC/V18JjOT9MjHH73c4XXxIwy9XFZbb63mE1Xof0BGruuas6yGkSqw S8ljZTfZGbUsxzQMlg7kBSgryqJ34hpPGTGOaa2aUePFaS6AeI6L+gM+DPUc5WXxdvtq ijav+ECt90thApsd9zIVEEMycSGycQdSQ/qGO6zEE0/ckzzYZkzFUwvgaBz0r1XrwFR8 JIRdgklXjnGt/1ecWCdFVrJw4VKR+LLRDvqj4JoglylmsH75TFMH+IdzpvWPQNZ811qj gPSicJqCP8JXJoPba890N1WHO6UIMcyz77bbCQ7hxSvdP5yQWtuQ+NGo5Lp1yxiq7KK5 9I3Q== X-Gm-Message-State: AOAM531rQSRAljPpzoSE9QFVK8IyzrXD5aOsbfAj6fzIefCys4sDY9+c 8nKcqdXWaCkz79wwkoYHwfGEKw== X-Google-Smtp-Source: ABdhPJxcoNlF6ng5ksw78iPSMmccL152IsM9NT+AoWqLVs6n6b2myfN3OxGjIqJwgzK32l0rJppOhQ== X-Received: by 2002:adf:e411:: with SMTP id g17mr2388550wrm.402.1622109114209; Thu, 27 May 2021 02:51:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH] arm: Consistently use "Cortex-Axx", not "Cortex Axx" Date: Thu, 27 May 2021 10:51:52 +0100 Message-Id: <20210527095152.10968-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The official punctuation for Arm CPU names uses a hyphen, like "Cortex-A9". We mostly follow this, but in a few places usage without the hyphen has crept in. Fix those so we consistently use the same way of writing the CPU name. This commit was created with: git grep -z -l 'Cortex ' | xargs -0 sed -i 's/Cortex /Cortex-/' Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- docs/system/arm/aspeed.rst | 4 ++-- docs/system/arm/nuvoton.rst | 6 +++--- docs/system/arm/sabrelite.rst | 2 +- include/hw/arm/allwinner-h3.h | 2 +- hw/arm/aspeed.c | 6 +++--- hw/arm/mcimx6ul-evk.c | 2 +- hw/arm/mcimx7d-sabre.c | 2 +- hw/arm/npcm7xx_boards.c | 4 ++-- hw/arm/sabrelite.c | 2 +- hw/misc/npcm7xx_clk.c | 2 +- 10 files changed, 16 insertions(+), 16 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index a1911f94031..57ee2bd94fc 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -5,7 +5,7 @@ The QEMU Aspeed machines model BMCs of various OpenPOWER sy= stems and Aspeed evaluation boards. They are based on different releases of the Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600 -with dual cores ARM Cortex A7 CPUs (1.2GHz). +with dual cores ARM Cortex-A7 CPUs (1.2GHz). =20 The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C, etc. @@ -24,7 +24,7 @@ AST2500 SoC based machines : =20 AST2600 SoC based machines : =20 -- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex A7) +- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7) - ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC =20 Supported devices diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index d3cf2d9cd7e..ca011bd4797 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -3,19 +3,19 @@ Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``) =20 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are designed to be used as Baseboard Management Controllers (BMCs) in various -servers. They all feature one or two ARM Cortex A9 CPU cores, as well as an +servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an assortment of peripherals targeted for either Enterprise or Data Center / Hyperscale applications. The former is a superset of the latter, so NPCM75= 0 has all the peripherals of NPCM730 and more. =20 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/ =20 -The NPCM750 SoC has two Cortex A9 cores and is targeted for the Enterprise +The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise segment. The following machines are based on this chip : =20 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board =20 -The NPCM730 SoC has two Cortex A9 cores and is targeted for Data Center and +The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and Hyperscale applications. The following machines are based on this chip : =20 - ``quanta-gsj`` Quanta GSJ server BMC diff --git a/docs/system/arm/sabrelite.rst b/docs/system/arm/sabrelite.rst index 71713310e3a..4ccb0560afe 100644 --- a/docs/system/arm/sabrelite.rst +++ b/docs/system/arm/sabrelite.rst @@ -10,7 +10,7 @@ Supported devices =20 The SABRE Lite machine supports the following devices: =20 - * Up to 4 Cortex A9 cores + * Up to 4 Cortex-A9 cores * Generic Interrupt Controller * 1 Clock Controller Module * 1 System Reset Controller diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index cc308a5d2c9..63025fb27c8 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -18,7 +18,7 @@ */ =20 /* - * The Allwinner H3 is a System on Chip containing four ARM Cortex A7 + * The Allwinner H3 is a System on Chip containing four ARM Cortex-A7 * processor cores. Features and specifications include DDR2/DDR3 memory, * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and * various I/O modules. diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 3fe6c55744f..0eafc791540 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -947,7 +947,7 @@ static void aspeed_machine_ast2600_evb_class_init(Objec= tClass *oc, void *data) MachineClass *mc =3D MACHINE_CLASS(oc); AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); =20 - mc->desc =3D "Aspeed AST2600 EVB (Cortex A7)"; + mc->desc =3D "Aspeed AST2600 EVB (Cortex-A7)"; amc->soc_name =3D "ast2600-a1"; amc->hw_strap1 =3D AST2600_EVB_HW_STRAP1; amc->hw_strap2 =3D AST2600_EVB_HW_STRAP2; @@ -966,7 +966,7 @@ static void aspeed_machine_tacoma_class_init(ObjectClas= s *oc, void *data) MachineClass *mc =3D MACHINE_CLASS(oc); AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); =20 - mc->desc =3D "OpenPOWER Tacoma BMC (Cortex A7)"; + mc->desc =3D "OpenPOWER Tacoma BMC (Cortex-A7)"; amc->soc_name =3D "ast2600-a1"; amc->hw_strap1 =3D TACOMA_BMC_HW_STRAP1; amc->hw_strap2 =3D TACOMA_BMC_HW_STRAP2; @@ -1003,7 +1003,7 @@ static void aspeed_machine_rainier_class_init(ObjectC= lass *oc, void *data) MachineClass *mc =3D MACHINE_CLASS(oc); AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); =20 - mc->desc =3D "IBM Rainier BMC (Cortex A7)"; + mc->desc =3D "IBM Rainier BMC (Cortex-A7)"; amc->soc_name =3D "ast2600-a1"; amc->hw_strap1 =3D RAINIER_BMC_HW_STRAP1; amc->hw_strap2 =3D RAINIER_BMC_HW_STRAP2; diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index ce16b6b3174..77fae874b16 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -67,7 +67,7 @@ static void mcimx6ul_evk_init(MachineState *machine) =20 static void mcimx6ul_evk_machine_init(MachineClass *mc) { - mc->desc =3D "Freescale i.MX6UL Evaluation Kit (Cortex A7)"; + mc->desc =3D "Freescale i.MX6UL Evaluation Kit (Cortex-A7)"; mc->init =3D mcimx6ul_evk_init; mc->max_cpus =3D FSL_IMX6UL_NUM_CPUS; mc->default_ram_id =3D "mcimx6ul-evk.ram"; diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index e896222c34c..935d4b0f1cd 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -67,7 +67,7 @@ static void mcimx7d_sabre_init(MachineState *machine) =20 static void mcimx7d_sabre_machine_init(MachineClass *mc) { - mc->desc =3D "Freescale i.MX7 DUAL SABRE (Cortex A7)"; + mc->desc =3D "Freescale i.MX7 DUAL SABRE (Cortex-A7)"; mc->init =3D mcimx7d_sabre_init; mc->max_cpus =3D FSL_IMX7_NUM_CPUS; mc->default_ram_id =3D "mcimx7d-sabre.ram"; diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index d4553e37865..698be46d303 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -299,7 +299,7 @@ static void npcm750_evb_machine_class_init(ObjectClass = *oc, void *data) =20 npcm7xx_set_soc_type(nmc, TYPE_NPCM750); =20 - mc->desc =3D "Nuvoton NPCM750 Evaluation Board (Cortex A9)"; + mc->desc =3D "Nuvoton NPCM750 Evaluation Board (Cortex-A9)"; mc->init =3D npcm750_evb_init; mc->default_ram_size =3D 512 * MiB; }; @@ -311,7 +311,7 @@ static void gsj_machine_class_init(ObjectClass *oc, voi= d *data) =20 npcm7xx_set_soc_type(nmc, TYPE_NPCM730); =20 - mc->desc =3D "Quanta GSJ (Cortex A9)"; + mc->desc =3D "Quanta GSJ (Cortex-A9)"; mc->init =3D quanta_gsj_init; mc->default_ram_size =3D 512 * MiB; }; diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 42348e5cb15..29fc777b613 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -105,7 +105,7 @@ static void sabrelite_init(MachineState *machine) =20 static void sabrelite_machine_init(MachineClass *mc) { - mc->desc =3D "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)"; + mc->desc =3D "Freescale i.MX6 Quad SABRE Lite Board (Cortex-A9)"; mc->init =3D sabrelite_init; mc->max_cpus =3D FSL_IMX6_NUM_CPUS; mc->ignore_memory_transaction_failures =3D true; diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c index a1ee67dc9a1..0b61070c52f 100644 --- a/hw/misc/npcm7xx_clk.c +++ b/hw/misc/npcm7xx_clk.c @@ -35,7 +35,7 @@ #define NPCM7XX_CLOCK_REF_HZ (25000000) =20 /* Register Field Definitions */ -#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */ +#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex-A9 Cores */ =20 #define PLLCON_LOKI BIT(31) #define PLLCON_LOKS BIT(30) --=20 2.20.1