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charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20210601144234epcas5p153e855ad673876cf67e57d4b539dc274 References: <20210601143749.1669-1-anaidu.gollu@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=203.254.224.25; envelope-from=anaidu.gollu@samsung.com; helo=mailout2.samsung.com X-Spam_score_int: -74 X-Spam_score: -7.5 X-Spam_bar: ------- X-Spam_report: (-7.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.371, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, kwolf@redhat.com, qemu-block@nongnu.org, Gollu Appalanaidu , mreitz@redhat.com, its@irrelevant.dk, stefanha@redhat.com, kbusch@kernel.org Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 NVMe Boot Partitions provides an area that may be read by the host without initializing queues or even enabling the controller. This allows various platform initialization code to be stored on the NVMe device instead of some separete medium. This patch adds the read support for such an area, as well as support for updating the boot partition contents from the host through the FW Download and Commit commands. Signed-off-by: Gollu Appalanaidu --- hw/nvme/ctrl.c | 207 +++++++++++++++++++++++++++++++++++++++++++ hw/nvme/nvme.h | 3 + hw/nvme/trace-events | 7 ++ include/block/nvme.h | 75 +++++++++++++++- 4 files changed, 291 insertions(+), 1 deletion(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 0bcaf7192f..ab72091802 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -100,6 +100,12 @@ * the minimum memory page size (CAP.MPSMIN). The default value is 0 (i.= e. * defaulting to the value of `mdts`). * + * - `bootpart` + * NVMe Boot Partitions provides an area that may be read by the host wi= thout + * initializing queues or even enabling the controller. This 'bootpart' = block + * device stores platform initialization code. Its size shall be in 256 = KiB + * units. + * * nvme namespace device parameters * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * - `shared` @@ -215,6 +221,8 @@ static const uint32_t nvme_cse_acs[256] =3D { [NVME_ADM_CMD_ASYNC_EV_REQ] =3D NVME_CMD_EFF_CSUPP, [NVME_ADM_CMD_NS_ATTACHMENT] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= NIC, [NVME_ADM_CMD_FORMAT_NVM] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, + [NVME_ADM_CMD_DOWNLOAD_FW] =3D NVME_CMD_EFF_CSUPP, + [NVME_ADM_CMD_COMMIT_FW] =3D NVME_CMD_EFF_CSUPP, }; =20 static const uint32_t nvme_cse_iocs_none[256]; @@ -5145,6 +5153,112 @@ static uint16_t nvme_format(NvmeCtrl *n, NvmeReques= t *req) return req->status; } =20 +struct nvme_bp_read_ctx { + NvmeCtrl *n; + QEMUSGList qsg; +}; + +static void nvme_bp_read_cb(void *opaque, int ret) +{ + struct nvme_bp_read_ctx *ctx =3D opaque; + NvmeCtrl *n =3D ctx->n; + + trace_pci_nvme_bp_read_cb(); + + if (ret) { + NVME_BPINFO_CLEAR_BRS(n->bar.bpinfo); + NVME_BPINFO_SET_BRS(n->bar.bpinfo, NVME_BPINFO_BRS_ERROR); + goto free; + } + + NVME_BPINFO_CLEAR_BRS(n->bar.bpinfo); + NVME_BPINFO_SET_BRS(n->bar.bpinfo, NVME_BPINFO_BRS_SUCCESS); + +free: + if (ctx->qsg.sg) { + qemu_sglist_destroy(&ctx->qsg); + } + + g_free(ctx); +} + +static void nvme_fw_commit_cb(void *opaque, int ret) +{ + NvmeRequest *req =3D opaque; + + trace_pci_nvme_fw_commit_cb(nvme_cid(req)); + + if (ret) { + nvme_aio_err(req, ret); + } + + nvme_enqueue_req_completion(nvme_cq(req), req); +} + +static uint16_t nvme_fw_commit(NvmeCtrl *n, NvmeRequest *req) +{ + uint32_t dw10 =3D le32_to_cpu(req->cmd.cdw10); + uint8_t fwug =3D n->id_ctrl.fwug; + uint8_t fs =3D dw10 & 0x7; + uint8_t ca =3D (dw10 >> 3) & 0x7; + uint8_t bpid =3D dw10 >> 31; + int64_t offset =3D 0; + + trace_pci_nvme_fw_commit(nvme_cid(req), dw10, fwug, fs, ca, + bpid); + + if (fs || ca =3D=3D NVME_FW_CA_REPLACE) { + return NVME_INVALID_FW_SLOT | NVME_DNR; + } + /* + * current firmware commit command only support boot partions + * related commit actions + */ + if (ca < NVME_FW_CA_REPLACE_BP) { + return NVME_FW_ACTIVATE_PROHIBITED | NVME_DNR; + } + + if (ca =3D=3D NVME_FW_CA_ACTIVATE_BP) { + NVME_BPINFO_CLEAR_ABPID(n->bar.bpinfo); + NVME_BPINFO_SET_ABPID(n->bar.bpinfo, bpid); + return NVME_SUCCESS; + } + + if (bpid) { + offset =3D n->bp_size; + } + + nvme_sg_init(n, &req->sg, false); + qemu_iovec_add(&req->sg.iov, n->bp_data, n->bp_size); + + req->aiocb =3D blk_aio_pwritev(n->blk_bp, offset, &req->sg.iov, 0, + nvme_fw_commit_cb, req); + + return NVME_NO_COMPLETE; +} + +static uint16_t nvme_fw_download(NvmeCtrl *n, NvmeRequest *req) +{ + uint32_t numd =3D le32_to_cpu(req->cmd.cdw10); + uint32_t offset =3D le32_to_cpu(req->cmd.cdw11); + size_t len =3D 0; + uint16_t status =3D NVME_SUCCESS; + + trace_pci_nvme_fw_download(nvme_cid(req), numd, offset, n->id_ctrl.fwu= g); + + len =3D (numd + 1) << 2; + offset <<=3D 2; + + if (len + offset > n->bp_size) { + trace_pci_nvme_fw_download_invalid_bp_size(offset, len, n->bp_size= ); + return NVME_INVALID_FIELD | NVME_DNR; + } + + status =3D nvme_h2c(n, n->bp_data + offset, len, req); + + return status; +} + static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req) { trace_pci_nvme_admin_cmd(nvme_cid(req), nvme_sqid(req), req->cmd.opcod= e, @@ -5181,6 +5295,10 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequ= est *req) return nvme_get_feature(n, req); case NVME_ADM_CMD_ASYNC_EV_REQ: return nvme_aer(n, req); + case NVME_ADM_CMD_COMMIT_FW: + return nvme_fw_commit(n, req); + case NVME_ADM_CMD_DOWNLOAD_FW: + return nvme_fw_download(n, req); case NVME_ADM_CMD_NS_ATTACHMENT: return nvme_ns_attachment(n, req); case NVME_ADM_CMD_FORMAT_NVM: @@ -5265,6 +5383,7 @@ static void nvme_ctrl_reset(NvmeCtrl *n) n->qs_created =3D false; =20 n->bar.cc =3D 0; + NVME_BPINFO_CLEAR_BRS(n->bar.bpinfo); } =20 static void nvme_ctrl_shutdown(NvmeCtrl *n) @@ -5546,6 +5665,47 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offse= t, uint64_t data, NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly, "invalid write to read only CMBSZ, ignored"); return; + case 0x44: /* BPRSEL */ + n->bar.bprsel =3D data & 0xffffffff; + size_t bp_len =3D NVME_BPRSEL_BPRSZ(n->bar.bprsel) * 4 * KiB; + int64_t bp_offset =3D NVME_BPRSEL_BPROF(n->bar.bprsel) * 4 * KiB; + int64_t off =3D 0; + struct nvme_bp_read_ctx *ctx; + + trace_pci_nvme_mmio_bprsel(data, n->bar.bprsel, + NVME_BPRSEL_BPID(n->bar.bpinfo), + bp_offset, bp_len); + + if (bp_len + bp_offset > n->bp_size) { + NVME_BPINFO_CLEAR_BRS(n->bar.bpinfo); + NVME_BPINFO_SET_BRS(n->bar.bpinfo, NVME_BPINFO_BRS_ERROR); + return; + } + + off =3D NVME_BPRSEL_BPID(n->bar.bpinfo) * n->bp_size + bp_offset; + + NVME_BPINFO_CLEAR_BRS(n->bar.bpinfo); + NVME_BPINFO_SET_BRS(n->bar.bpinfo, NVME_BPINFO_BRS_READING); + + ctx =3D g_new(struct nvme_bp_read_ctx, 1); + + ctx->n =3D n; + + pci_dma_sglist_init(&ctx->qsg, &n->parent_obj, 1); + + qemu_sglist_add(&ctx->qsg, n->bar.bpmbl, bp_len); + + dma_blk_read(n->blk_bp, &ctx->qsg, off , BDRV_SECTOR_SIZE, + nvme_bp_read_cb, ctx); + return; + case 0x48: /* BPMBL */ + n->bar.bpmbl =3D size =3D=3D 8 ? data : + (n->bar.bpmbl & ~0xffffffff) | (data & 0xfffff000); + trace_pci_nvme_mmio_bpmbl(data, n->bar.bpmbl); + return; + case 0x4c: /* BPMBL hi */ + n->bar.bpmbl =3D (n->bar.bpmbl & 0xffffffff) | (data << 32); + return; case 0x50: /* CMBMSC */ if (!NVME_CAP_CMBS(n->bar.cap)) { return; @@ -6074,6 +6234,9 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pc= i_dev) id->mdts =3D n->params.mdts; id->ver =3D cpu_to_le32(NVME_SPEC_VER); id->oacs =3D cpu_to_le16(NVME_OACS_NS_MGMT | NVME_OACS_FORMAT); + if (n->blk_bp) { + id->oacs |=3D NVME_OACS_FW; + } id->cntrltype =3D 0x1; =20 /* @@ -6135,9 +6298,44 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *p= ci_dev) NVME_CAP_SET_MPSMAX(n->bar.cap, 4); NVME_CAP_SET_CMBS(n->bar.cap, n->params.cmb_size_mb ? 1 : 0); NVME_CAP_SET_PMRS(n->bar.cap, n->pmr.dev ? 1 : 0); + NVME_CAP_SET_BPS(n->bar.cap, 0x1); =20 n->bar.vs =3D NVME_SPEC_VER; n->bar.intmc =3D n->bar.intms =3D 0; + + /* Boot Partition Information (BPINFO) */ + n->bar.bpinfo =3D 0; +} + +static int nvme_init_boot_partitions(NvmeCtrl *n, Error **errp) +{ + BlockBackend *blk =3D n->blk_bp; + uint64_t len, perm, shared_perm; + size_t bp_size; + int ret; + + len =3D blk_getlength(blk); + if (len % (256 * KiB)) { + error_setg(errp, "boot partitions image size shall be"\ + " multiple of 256 KiB current size %lu", len); + return -1; + } + + perm =3D BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE; + shared_perm =3D BLK_PERM_ALL; + + ret =3D blk_set_perm(blk, perm, shared_perm, errp); + if (ret) { + return ret; + } + + bp_size =3D len / (256 * KiB); + NVME_BPINFO_SET_BPSZ(n->bar.bpinfo, bp_size); + n->bp_size =3D bp_size * 128 * KiB; + + n->bp_data =3D g_malloc(n->bp_size); + + return 0; } =20 static int nvme_init_subsys(NvmeCtrl *n, Error **errp) @@ -6207,6 +6405,13 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) =20 nvme_attach_ns(n, ns); } + + if (n->blk_bp) { + if (nvme_init_boot_partitions(n, errp)) { + error_propagate(errp, local_err); + return; + } + } } =20 static void nvme_exit(PCIDevice *pci_dev) @@ -6229,6 +6434,7 @@ static void nvme_exit(PCIDevice *pci_dev) g_free(n->cq); g_free(n->sq); g_free(n->aer_reqs); + g_free(n->bp_data); =20 if (n->params.cmb_size_mb) { g_free(n->cmb.buf); @@ -6247,6 +6453,7 @@ static Property nvme_props[] =3D { HostMemoryBackend *), DEFINE_PROP_LINK("subsys", NvmeCtrl, subsys, TYPE_NVME_SUBSYS, NvmeSubsystem *), + DEFINE_PROP_DRIVE("bootpart", NvmeCtrl, blk_bp), DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial), DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0), DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 0), diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index c55293f6d3..1f51e8907e 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -435,6 +435,9 @@ typedef struct NvmeCtrl { DECLARE_BITMAP(changed_nsids, NVME_CHANGED_NSID_SIZE); =20 NvmeSubsystem *subsys; + BlockBackend *blk_bp; + uint8_t *bp_data; + uint64_t bp_size; =20 NvmeNamespace namespace; NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1]; diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events index ea33d0ccc3..11234b2dba 100644 --- a/hw/nvme/trace-events +++ b/hw/nvme/trace-events @@ -80,6 +80,11 @@ pci_nvme_enqueue_event(uint8_t typ, uint8_t info, uint8_= t log_page) "type 0x%"PR pci_nvme_enqueue_event_noqueue(int queued) "queued %d" pci_nvme_enqueue_event_masked(uint8_t typ) "type 0x%"PRIx8"" pci_nvme_no_outstanding_aers(void) "ignoring event; no outstanding AERs" +pci_nvme_fw_commit(uint16_t cid, uint32_t dw10, uint8_t fwug, uint8_t fs, = uint8_t ca, uint8_t bpid) "cid %"PRIu16" dw10 %"PRIu32" fwug %"PRIu8" fs %"= PRIu8" ca %"PRIu8" bpid %"PRIu8"" +pci_nvme_fw_download(uint16_t cid, uint32_t numd, uint32_t ofst, uint8_t f= wug) "cid %"PRIu16" numd %"PRIu32" ofst %"PRIu32" fwug %"PRIu8"" +pci_nvme_fw_commit_cb(uint16_t cid) "cid %"PRIu16"" +pci_nvme_bp_read_cb(void) "" +pci_nvme_fw_download_invalid_bp_size(uint32_t ofst, size_t len, uint64_t b= p_size) "ofst %"PRIu32" len %zu bp_size %"PRIu64"" pci_nvme_enqueue_req_completion(uint16_t cid, uint16_t cqid, uint16_t stat= us) "cid %"PRIu16" cqid %"PRIu16" status 0x%"PRIx16"" pci_nvme_mmio_read(uint64_t addr, unsigned size) "addr 0x%"PRIx64" size %d" pci_nvme_mmio_write(uint64_t addr, uint64_t data, unsigned size) "addr 0x%= "PRIx64" data 0x%"PRIx64" size %d" @@ -96,6 +101,8 @@ pci_nvme_mmio_acqaddr_hi(uint64_t data, uint64_t new_add= r) "wrote MMIO, admin co pci_nvme_mmio_start_success(void) "setting controller enable bit succeeded" pci_nvme_mmio_stopped(void) "cleared controller enable bit" pci_nvme_mmio_shutdown_set(void) "shutdown bit set" +pci_nvme_mmio_bpmbl(uint64_t data, uint64_t bpmbl) "wrote MMIO, boot parti= tions buffer location data=3D0x%"PRIx64", bpmbl=3D0x%"PRIx64"" +pci_nvme_mmio_bprsel(uint64_t data, uint8_t bp_id, uint64_t bp_off, uint64= _t bp_size, uint64_t bprsel) "wrote MMIO, boot partitions read select data= =3D0x%"PRIx64", bp_id=3D0x%"PRIx8" bp_off=3D0x%"PRIx64", bp_off=3D0x%"PRIx6= 4", bprsel=3D0x%"PRIx64"" pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared" pci_nvme_open_zone(uint64_t slba, uint32_t zone_idx, int all) "open zone, = slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" pci_nvme_close_zone(uint64_t slba, uint32_t zone_idx, int all) "close zone= , slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" diff --git a/include/block/nvme.h b/include/block/nvme.h index 2b9d849023..4785687ab8 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -38,6 +38,7 @@ enum NvmeCapShift { CAP_DSTRD_SHIFT =3D 32, CAP_NSSRS_SHIFT =3D 36, CAP_CSS_SHIFT =3D 37, + CAP_BPS_SHIFT =3D 45, CAP_MPSMIN_SHIFT =3D 48, CAP_MPSMAX_SHIFT =3D 52, CAP_PMRS_SHIFT =3D 56, @@ -52,6 +53,7 @@ enum NvmeCapMask { CAP_DSTRD_MASK =3D 0xf, CAP_NSSRS_MASK =3D 0x1, CAP_CSS_MASK =3D 0xff, + CAP_BPS_MASK =3D 0x1, CAP_MPSMIN_MASK =3D 0xf, CAP_MPSMAX_MASK =3D 0xf, CAP_PMRS_MASK =3D 0x1, @@ -65,6 +67,7 @@ enum NvmeCapMask { #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) +#define NVME_CAP_BPS(cap) (((cap) >> CAP_BPS_SHIFT) & CAP_BPS_MASK) #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) #define NVME_CAP_PMRS(cap) (((cap) >> CAP_PMRS_SHIFT) & CAP_PMRS_MASK) @@ -84,6 +87,8 @@ enum NvmeCapMask { << CAP_NSSRS_SH= IFT) #define NVME_CAP_SET_CSS(cap, val) (cap |=3D (uint64_t)(val & CAP_CSS_M= ASK) \ << CAP_CSS_SHIF= T) +#define NVME_CAP_SET_BPS(cap, val) (cap |=3D (uint64_t)(val & CAP_BPS_M= ASK) \ + << CAP_BPS_SHIF= T) #define NVME_CAP_SET_MPSMIN(cap, val) (cap |=3D (uint64_t)(val & CAP_MPSMI= N_MASK)\ << CAP_MPSMIN_S= HIFT) #define NVME_CAP_SET_MPSMAX(cap, val) (cap |=3D (uint64_t)(val & CAP_MPSMA= X_MASK)\ @@ -495,6 +500,63 @@ enum NvmePmrmscMask { #define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ (pmrmsc |=3D (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) =20 +enum NvmeBpReadStatus { + NVME_BPINFO_BRS_NOREAD =3D 0x0, + NVME_BPINFO_BRS_READING =3D 0x1, + NVME_BPINFO_BRS_SUCCESS =3D 0x2, + NVME_BPINFO_BRS_ERROR =3D 0x3, +}; + +enum NvmeBpInfoShift { + BPINFO_BPSZ_SHIFT =3D 0, + BPINFO_BRS_SHIFT =3D 24, + BPINFO_ABPID_SHIFT =3D 31, +}; + +enum NvmeBpInfoMask { + BPINFO_BPSZ_MASK =3D 0x7fff, + BPINFO_BRS_MASK =3D 0x3, + BPINFO_ABPID_MASK =3D 0x1, +}; + +#define NVME_BPINFO_SET_BPSZ(bpinfo, val) \ + (bpinfo |=3D (uint64_t)(val & BPINFO_BPSZ_MASK) << BPINFO_BPSZ_SHIFT) +#define NVME_BPINFO_SET_BRS(bpinfo, val) \ + (bpinfo |=3D (uint64_t)(val & BPINFO_BRS_MASK) << BPINFO_BRS_SHIFT) +#define NVME_BPINFO_SET_ABPID(bpinfo, val) \ + (bpinfo |=3D (uint64_t)(val & BPINFO_ABPID_MASK) << BPINFO_ABPID_SHIFT) + +#define NVME_BPINFO_BPSZ(bpinfo) \ + ((bpinfo >> BPINFO_BPSZ_SHIFT) & BPINFO_BPSZ_MASK) +#define NVME_BPINFO_BRS(bpinfo) \ + ((bpinfo >> BPINFO_BRS_SHIFT) & BPINFO_BRS_MASK) +#define NVME_BPINFO_ABPID(bpinfo) \ + ((bpinfo >> BPINFO_ABPID_SHIFT) & BPINFO_ABPID_MASK) + +#define NVME_BPINFO_CLEAR_ABPID(bpinfo) \ + (bpinfo &=3D (uint64_t)(~(BPINFO_ABPID_MASK << BPINFO_ABPID_SHIFT))) +#define NVME_BPINFO_CLEAR_BRS(bpinfo) \ + (bpinfo &=3D (uint64_t)(~(BPINFO_BRS_MASK << BPINFO_BRS_SHIFT))) + +enum NvmeBpReadSelectShift { + BPRSEL_BPRSZ_SHIFT =3D 0, + BPRSEL_BPROF_SHIFT =3D 10, + BPRSEL_BPID_SHIFT =3D 31, +}; + +enum NvmeBpReadSelectMask { + BPRSEL_BPRSZ_MASK =3D 0x3ff, + BPRSEL_BPROF_MASK =3D 0xffff, + BPRSEL_BPID_MASK =3D 0x1, +}; + +#define NVME_BPRSEL_BPRSZ(bprsel) \ + ((bprsel >> BPRSEL_BPRSZ_SHIFT) & BPRSEL_BPRSZ_MASK) +#define NVME_BPRSEL_BPROF(bprsel) \ + ((bprsel >> BPRSEL_BPROF_SHIFT) & BPRSEL_BPROF_MASK) +#define NVME_BPRSEL_BPID(bprsel) \ + ((bprsel >> BPRSEL_BPID_SHIFT) & BPRSEL_BPID_MASK) + enum NvmeSglDescriptorType { NVME_SGL_DESCR_TYPE_DATA_BLOCK =3D 0x0, NVME_SGL_DESCR_TYPE_BIT_BUCKET =3D 0x1, @@ -564,7 +626,7 @@ enum NvmeAdminCommands { NVME_ADM_CMD_SET_FEATURES =3D 0x09, NVME_ADM_CMD_GET_FEATURES =3D 0x0a, NVME_ADM_CMD_ASYNC_EV_REQ =3D 0x0c, - NVME_ADM_CMD_ACTIVATE_FW =3D 0x10, + NVME_ADM_CMD_COMMIT_FW =3D 0x10, NVME_ADM_CMD_DOWNLOAD_FW =3D 0x11, NVME_ADM_CMD_NS_ATTACHMENT =3D 0x15, NVME_ADM_CMD_FORMAT_NVM =3D 0x80, @@ -846,6 +908,8 @@ enum NvmeStatusCodes { NVME_FEAT_NOT_CHANGEABLE =3D 0x010e, NVME_FEAT_NOT_NS_SPEC =3D 0x010f, NVME_FW_REQ_SUSYSTEM_RESET =3D 0x0110, + NVME_FW_ACTIVATE_PROHIBITED =3D 0x0113, + NVME_BP_WRITE_PROHIBITED =3D 0x011e, NVME_NS_ALREADY_ATTACHED =3D 0x0118, NVME_NS_PRIVATE =3D 0x0119, NVME_NS_NOT_ATTACHED =3D 0x011a, @@ -1107,6 +1171,15 @@ enum NvmeIdCtrlFrmw { NVME_FRMW_SLOT1_RO =3D 1 << 0, }; =20 +enum NvmeFwCommitActions { + NVME_FW_CA_REPLACE =3D 0x00, + NVME_FW_CA_REPLACE_AND_ACTIVATE =3D 0x01, + NVME_FW_CA_ACTIVATE =3D 0x02, + NVME_FW_CA_REPLACE_AND_ACTIVATE_NOW =3D 0x03, + NVME_FW_CA_REPLACE_BP =3D 0x06, + NVME_FW_CA_ACTIVATE_BP =3D 0x07, +}; + enum NvmeIdCtrlLpa { NVME_LPA_NS_SMART =3D 1 << 0, NVME_LPA_CSE =3D 1 << 1, --=20 2.17.1 From nobody Sat May 4 00:30:49 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=samsung.com ARC-Seal: i=1; a=rsa-sha256; t=1622561230; cv=none; d=zohomail.com; s=zohoarc; b=fYp0SHbI2lI4Sxb1sfpb1l8mgghLAUD0+qG9f3KCAxpxuTpA1PdD5oc01zQui+0gVKWGdhK776xyGO6nzjvyVkAiUN1QrGOeyK8yCJIcSxhBjDvOVlBc+AZ80Au5ToX4FFKF5jbZcyyQtmDgNBMgfoungcubO2lL2zShqTMpFzo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Signed-off-by: Gollu Appalanaidu --- tests/qtest/nvme-test.c | 118 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 117 insertions(+), 1 deletion(-) diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c index d32c953a38..39d2e26f76 100644 --- a/tests/qtest/nvme-test.c +++ b/tests/qtest/nvme-test.c @@ -13,6 +13,19 @@ #include "libqos/libqtest.h" #include "libqos/qgraph.h" #include "libqos/pci.h" +#include "libqos/pci-pc.h" +#include "libqos/malloc-pc.h" +#include "libqos/malloc.h" +#include "libqos/libqos.h" +#include "include/block/nvme.h" +#include "include/hw/pci/pci.h" + +#define NVME_BPINFO_BPSZ_UNITS (128 * KiB) +#define NVME_BRS_BPSZ_UNITS (4 * KiB) +#define NVME_BRS_READ_MAX_TIME 1000000 +#define TEST_IMAGE_SIZE (2 * 128 * KiB) + +static char *t_path; =20 typedef struct QNvme QNvme; =20 @@ -44,6 +57,13 @@ static void *nvme_create(void *pci_bus, QGuestAllocator = *alloc, void *addr) return &nvme->obj; } =20 +static void drive_destroy(void *path) +{ + unlink(path); + g_free(path); + qos_invalidate_command_line(); +} + /* This used to cause a NULL pointer dereference. */ static void nvmetest_oob_cmb_test(void *obj, void *data, QGuestAllocator *= alloc) { @@ -66,12 +86,100 @@ static void nvmetest_oob_cmb_test(void *obj, void *dat= a, QGuestAllocator *alloc) g_assert_cmpint(qpci_io_readl(pdev, bar, cmb_bar_size - 1), !=3D, 0x44= 332211); } =20 +static void nvmetest_bp_read_test(void *obj, void *data, QGuestAllocator *= alloc) +{ + uint16_t test_size =3D 32; + size_t bp_test_len =3D test_size * NVME_BRS_BPSZ_UNITS; + uint8_t *read_buf =3D g_malloc(bp_test_len); + uint8_t *cmp_buf =3D g_malloc(bp_test_len); + QNvme *nvme =3D obj; + QPCIDevice *pdev =3D &nvme->dev; + QPCIBar nvme_bar; + uint8_t brs =3D 0; + uint64_t sleep_time =3D 0; + uintptr_t guest_buf; + uint64_t buf_addr; + + memset(cmp_buf, 0x42, bp_test_len); + + guest_buf =3D guest_alloc(alloc, bp_test_len); + buf_addr =3D cpu_to_le64(guest_buf); + + qpci_device_enable(pdev); + nvme_bar =3D qpci_iomap(pdev, 0, NULL); + + /* BPINFO */ + uint32_t bpinfo =3D qpci_io_readl(pdev, nvme_bar, 0x40); + uint16_t single_bp_size =3D bpinfo & BPINFO_BPSZ_MASK; + uint8_t active_bpid =3D bpinfo >> BPINFO_ABPID_SHIFT; + uint8_t read_select =3D (bpinfo >> BPINFO_BRS_SHIFT) & BPINFO_BRS_MASK; + + g_assert_cmpint(single_bp_size, =3D=3D, 0x1); + g_assert_cmpint(active_bpid, =3D=3D, 0); + g_assert_cmpint(read_select, =3D=3D, NVME_BPINFO_BRS_NOREAD); + + /* BPMBL */ + uint64_t bpmbl =3D buf_addr; + uint32_t bpmbl_low =3D bpmbl & 0xffffffff; + uint32_t bpmbl_hi =3D (bpmbl >> 32) & 0xffffffff; + qpci_io_writel(pdev, nvme_bar, 0x48, bpmbl_low); + qpci_io_writel(pdev, nvme_bar, 0x4c, bpmbl_hi); + + /* BPRSEL */ + qpci_io_writel(pdev, nvme_bar, 0x44, 32); + + while (true) { + usleep(1000); + sleep_time +=3D 1000; + brs =3D qpci_io_readb(pdev, nvme_bar, 0x43) & BPINFO_BRS_MASK; + if (brs =3D=3D NVME_BPINFO_BRS_SUCCESS || brs =3D=3D NVME_BPINFO_B= RS_ERROR || + sleep_time =3D=3D NVME_BRS_READ_MAX_TIME) { + break; + } + } + g_assert_cmpint(brs, =3D=3D, NVME_BPINFO_BRS_SUCCESS); + + qtest_memread(pdev->bus->qts, guest_buf, read_buf, bp_test_len); + g_assert_cmpint(memcmp(cmp_buf, read_buf, bp_test_len), =3D=3D, 0); + + g_free(cmp_buf); + g_free(read_buf); + g_test_queue_destroy(drive_destroy, t_path); +} + static void nvme_register_nodes(void) { + int fd; + FILE *fh; + uint16_t bpsz =3D 2; + size_t bp_len =3D NVME_BPINFO_BPSZ_UNITS * bpsz; + size_t ret; + uint8_t *pattern =3D g_malloc(bp_len); + + t_path =3D g_strdup("/tmp/qtest.XXXXXX"); + + /* Create a temporary raw image */ + fd =3D mkstemp(t_path); + g_assert_cmpint(fd, >=3D, 0); + ret =3D ftruncate(fd, TEST_IMAGE_SIZE); + g_assert_cmpint(ret, =3D=3D, 0); + close(fd); + + memset(pattern, 0x42, bp_len); + + fh =3D fopen(t_path, "w+"); + ret =3D fwrite(pattern, NVME_BPINFO_BPSZ_UNITS, bpsz, fh); + g_assert_cmpint(ret, =3D=3D, bpsz); + fclose(fh); + + char *bp_cmd_line =3D g_strdup_printf("-drive id=3Dbp0,file=3D%s,if=3D= none," + "format=3Draw", t_path); + QOSGraphEdgeOptions opts =3D { .extra_device_opts =3D "addr=3D04.0,drive=3Ddrv0,serial=3Dfoo", .before_cmd_line =3D "-drive id=3Ddrv0,if=3Dnone,file=3Dnull-co://= ," - "file.read-zeroes=3Don,format=3Draw", + "file.read-zeroes=3Don,format=3Draw ", + bp_cmd_line, }; =20 add_qpci_address(&opts, &(QPCIAddress) { .devfn =3D QPCI_DEVFN(4, 0) }= ); @@ -83,6 +191,14 @@ static void nvme_register_nodes(void) qos_add_test("oob-cmb-access", "nvme", nvmetest_oob_cmb_test, &(QOSGra= phTestOptions) { .edge.extra_device_opts =3D "cmb_size_mb=3D2" }); + + qos_add_test("bp-read-access", "nvme", nvmetest_bp_read_test, + &(QOSGraphTestOptions) { + .edge.extra_device_opts =3D "bootpart=3Dbp0" + }); + + /* Clean Up */ + g_free(pattern); } =20 libqos_init(nvme_register_nodes); --=20 2.17.1