From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1622576293; cv=none; d=zohomail.com; s=zohoarc; b=m5cfPEzttdtA2/scSQxrocOgjvs8Put+tEmInuaxMS6bmAnNKxqiMoDjULssc1663Vn4i/bJI25eDCL/tLaoZKTsbM04xgHsd5zWRKYe1V2hj32Gc5rvvLSkWLcLqGuOA7lc0pdqVzq03T7YaJPzf4bSP3+vC+SoKxLGl1GnWFw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622576293; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lXUg0HMlO9ev+KJbZvX+0/gN7MlCeDySpBPHpNOcEWA=; b=cuGdJ3EygTtcC2iDt3nnvINSxhb5J6yhp5ks7i788v2kvh8w6CtlfIDyMSSTE6v7p9NLSt/YCbkCUh1uLroPYjGypMfZeEDHbdSDoSccbFwlJKQ3ME3IdoAJ8aNYB46b2sSinVj/w+gGZJpTd9PqYQOvpZySIcH9pxfP3y3HHOs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622576293059441.5130680817281; Tue, 1 Jun 2021 12:38:13 -0700 (PDT) Received: from localhost ([::1]:33048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loADM-00044l-1W for importer2@patchew.org; Tue, 01 Jun 2021 15:38:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33292) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loAB3-0001Lw-5K; Tue, 01 Jun 2021 15:35:49 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAB1-0002Jl-N1; Tue, 01 Jun 2021 15:35:48 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:40 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id CFF4580148C; Tue, 1 Jun 2021 16:35:39 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 01/14] target/ppc: Introduce macros to check isa extensions Date: Tue, 1 Jun 2021 16:35:15 -0300 Message-Id: <20210601193528.2533031-2-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:40.0331 (UTC) FILETIME=[4DE60FB0:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Richard Henderson These will be used by the decodetree trans_* functions to early-exit when the instruction set is not enabled. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/translate.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e16a2721e2..11fd3342a0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7664,6 +7664,32 @@ static inline void set_avr64(int regno, TCGv_i64 src= , bool high) tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); } =20 +/* + * Helpers for trans_* functions to check for specific insns flags. + * Use token pasting to ensure that we use the proper flag with the + * proper variable. + */ +#define REQUIRE_INSNS_FLAGS(CTX, NAME) \ + do { \ + if (((CTX)->insns_flags & PPC_##NAME) =3D=3D 0) { \ + return false; \ + } \ + } while (0) + +#define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ + do { \ + if (((CTX)->insns_flags2 & PPC2_##NAME) =3D=3D 0) { \ + return false; \ + } \ + } while (0) + +/* Then special-case the check for 64-bit so that we elide code for ppc32.= */ +#if TARGET_LONG_BITS =3D=3D 32 +# define REQUIRE_64BIT(CTX) return false +#else +# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) +#endif + #include "translate/fp-impl.c.inc" =20 #include "translate/vmx-impl.c.inc" --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 1 Jun 2021 12:38:16 -0700 (PDT) Received: from localhost ([::1]:33284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loADP-0004ER-4K for importer2@patchew.org; Tue, 01 Jun 2021 15:38:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33304) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loAB5-0001Ph-MC; Tue, 01 Jun 2021 15:35:51 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAB4-0002Jl-6u; Tue, 01 Jun 2021 15:35:51 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:40 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 5596E80148B; Tue, 1 Jun 2021 16:35:40 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 02/14] target/ppc: Move page crossing check to ppc_tr_translate_insn Date: Tue, 1 Jun 2021 16:35:16 -0300 Message-Id: <20210601193528.2533031-3-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:40.0815 (UTC) FILETIME=[4E2FE9F0:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Richard Henderson With prefixed instructions, the number of instructions remaining until the page crossing is no longer constant. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/translate.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 11fd3342a0..d2c9fd9dd7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8821,9 +8821,6 @@ static void ppc_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) =20 if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP))= { ctx->base.max_insns =3D 1; - } else { - int bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; - ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); } } =20 @@ -8874,6 +8871,12 @@ static void ppc_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) gen_invalid(ctx); } =20 + /* End the TB when crossing a page boundary. */ + if (ctx->base.is_jmp =3D=3D DISAS_NEXT && + !(ctx->base.pc_next & ~TARGET_PAGE_MASK)) { + ctx->base.is_jmp =3D DISAS_TOO_MANY; + } + translator_loop_temp_check(&ctx->base); } =20 --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1622576522; cv=none; d=zohomail.com; s=zohoarc; b=aYIPKfdB+9TSVveL7Dd9jvatTfgR17l7kgQEbW+IRmta94sbcsRvE1h7HljP9l/9jWqsUA/mY3M4KM4nGbHPOVp2BFyRhYjWIS6kevT6gXIvpDFt9J3/JMqLpKDiBbqUBNR0aebYL8RKjvpN6jDOs8afH5mL3DbiwN1hTjpX/dU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622576522; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J9Pxl+c+odjsiLYyr4ghGYieqmD4EvuSR/fL4fy7RFk=; b=Sj5f5NZSTHAdUnDU5wZfr6vbW12h5WZJsm8mDgF/Pa9HONScaxbPAXB0mK6rJUC8FxanUJ12+ppaJyEQ8c2bb8MyLPKia72hB+q5pzWXzxPJG2ODyKqxQnv4r+mPrq5VNCAeXaenqOEPx/347Owrq0FQb3IZLewqCuPAEAKCCVE= ARC-Authentication-Results: i=1; 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Tue, 1 Jun 2021 16:35:41 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id C65E080148C; Tue, 1 Jun 2021 16:35:40 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 03/14] target/ppc: Add infrastructure for prefixed insns Date: Tue, 1 Jun 2021 16:35:17 -0300 Message-Id: <20210601193528.2533031-4-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:41.0284 (UTC) FILETIME=[4E777A40:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Luis Pires Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/cpu.h | 1 + target/ppc/insn32.decode | 18 +++++++++++ target/ppc/insn64.decode | 18 +++++++++++ target/ppc/meson.build | 9 ++++++ target/ppc/translate.c | 37 ++++++++++++++++++---- target/ppc/translate/fixedpoint-impl.c.inc | 18 +++++++++++ 6 files changed, 95 insertions(+), 6 deletions(-) create mode 100644 target/ppc/insn32.decode create mode 100644 target/ppc/insn64.decode create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b0934d9be4..ad34c479ec 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -144,6 +144,7 @@ enum { POWERPC_EXCP_ALIGN_PROT =3D 0x04, /* Access cross protection bound= ary */ POWERPC_EXCP_ALIGN_BAT =3D 0x05, /* Access cross a BAT/seg bounda= ry */ POWERPC_EXCP_ALIGN_CACHE =3D 0x06, /* Impossible dcbz access = */ + POWERPC_EXCP_ALIGN_INSN =3D 0x07, /* Pref. insn x-ing 64-byte boun= dary */ /* Exception subtypes for POWERPC_EXCP_PROGRAM = */ /* FP exceptions = */ POWERPC_EXCP_FP =3D 0x10, diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode new file mode 100644 index 0000000000..a3a8ae06bf --- /dev/null +++ b/target/ppc/insn32.decode @@ -0,0 +1,18 @@ +# +# Power ISA decode for 32-bit insns (opcode space 0) +# +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode new file mode 100644 index 0000000000..a38b1f84dc --- /dev/null +++ b/target/ppc/insn64.decode @@ -0,0 +1,18 @@ +# +# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1) +# +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# diff --git a/target/ppc/meson.build b/target/ppc/meson.build index a6a53a8d5c..a4f18ff414 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -20,6 +20,15 @@ ppc_ss.add(when: 'CONFIG_TCG', if_true: files( =20 ppc_ss.add(libdecnumber) =20 +gen =3D [ + decodetree.process('insn32.decode', + extra_args: '--static-decode=3Ddecode_insn32'), + decodetree.process('insn64.decode', + extra_args: ['--static-decode=3Ddecode_insn64', + '--insnwidth=3D64']), +] +ppc_ss.add(gen) + ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('k= vm-stub.c')) ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d2c9fd9dd7..f3f464c654 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7690,6 +7690,10 @@ static inline void set_avr64(int regno, TCGv_i64 src= , bool high) # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) #endif =20 +#include "decode-insn32.c.inc" +#include "decode-insn64.c.inc" +#include "translate/fixedpoint-impl.c.inc" + #include "translate/fp-impl.c.inc" =20 #include "translate/vmx-impl.c.inc" @@ -8850,11 +8854,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBas= e *dcbase, CPUState *cs, return true; } =20 +static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + return opc1(insn) =3D=3D 1; +} + static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D cs->env_ptr; + target_ulong pc; uint32_t insn; bool ok; =20 @@ -8862,18 +8873,32 @@ static void ppc_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cs) LOG_DISAS("nip=3D" TARGET_FMT_lx " super=3D%d ir=3D%d\n", ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); =20 - ctx->cia =3D ctx->base.pc_next; - insn =3D translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx= )); - ctx->base.pc_next +=3D 4; + ctx->cia =3D pc =3D ctx->base.pc_next; + insn =3D translator_ldl_swap(env, pc, need_byteswap(ctx)); + ctx->base.pc_next =3D pc +=3D 4; =20 - ok =3D decode_legacy(cpu, ctx, insn); + if (!is_prefix_insn(ctx, insn)) { + ok =3D (decode_insn32(ctx, insn) || + decode_legacy(cpu, ctx, insn)); + } else if ((pc & 63) =3D=3D 0) { + /* + * Power v3.1, section 1.9 Exceptions: + * attempt to execute a prefixed instruction that crosses a + * 64-byte address boundary (system alignment error). + */ + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN= ); + ok =3D true; + } else { + uint32_t insn2 =3D translator_ldl_swap(env, pc, need_byteswap(ctx)= ); + ctx->base.pc_next =3D pc +=3D 4; + ok =3D decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); + } if (!ok) { gen_invalid(ctx); } =20 /* End the TB when crossing a page boundary. */ - if (ctx->base.is_jmp =3D=3D DISAS_NEXT && - !(ctx->base.pc_next & ~TARGET_PAGE_MASK)) { + if (ctx->base.is_jmp =3D=3D DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { ctx->base.is_jmp =3D DISAS_TOO_MANY; } =20 diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc new file mode 100644 index 0000000000..be75085cee --- /dev/null +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -0,0 +1,18 @@ +/* + * Power ISA decode for Fixed-Point Facility instructions + * + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1622576703; cv=none; d=zohomail.com; s=zohoarc; b=S1UWhU5fKwHOYVBuEWJPOFey6tbWXzb7OCnjriVtgFypVxsLAuZzsCoT7Zge2CVBjUcV3rUrY4RxyJQnxBIp/31ZujPjTr3KV1Vi7skiJt3Y8FtdCeZSoSlkmCzLFH+oi2rrn8mFJyqQIy5o6jisVMnH4gBs0+gvWUMlLLB21ps= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622576703; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Tue, 01 Jun 2021 15:35:57 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:41 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 4D22A80148B; Tue, 1 Jun 2021 16:35:41 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 04/14] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI Date: Tue, 1 Jun 2021 16:35:18 -0300 Message-Id: <20210601193528.2533031-5-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:41.0753 (UTC) FILETIME=[4EBF0A90:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 8 ++++ target/ppc/insn64.decode | 12 ++++++ target/ppc/translate.c | 29 -------------- target/ppc/translate/fixedpoint-impl.c.inc | 44 ++++++++++++++++++++++ 4 files changed, 64 insertions(+), 29 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index a3a8ae06bf..e7c062d8b4 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -16,3 +16,11 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see . # + +&D rt ra si:int64_t +@D ...... rt:5 ra:5 si:s16 &D + +### Fixed-Point Arithmetic Instructions + +ADDI 001110 ..... ..... ................ @D +ADDIS 001111 ..... ..... ................ @D diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index a38b1f84dc..1965088915 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -16,3 +16,15 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see . # + +# Format MLS:D and 8LS:D +&PLS_D rt ra si:int64_t r:bool +%pls_si 32:s18 0:16 +@PLS_D ...... .. ... r:1 .. .................. \ + ...... rt:5 ra:5 ................ \ + &PLS_D si=3D%pls_si + +### Fixed-Point Arithmetic Instructions + +PADDI 000001 10 0--.-- .................. \ + 001110 ..... ..... ................ @PLS_D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f3f464c654..3012c7447a 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1760,19 +1760,6 @@ GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); /* addze addze. addzeo addzeo.*/ GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) -/* addi */ -static void gen_addi(DisasContext *ctx) -{ - target_long simm =3D SIMM(ctx->opcode); - - if (rA(ctx->opcode) =3D=3D 0) { - /* li case */ - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); - } else { - tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rA(ctx->opcode)], simm); - } -} /* addic addic.*/ static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) { @@ -1792,20 +1779,6 @@ static void gen_addic_(DisasContext *ctx) gen_op_addic(ctx, 1); } =20 -/* addis */ -static void gen_addis(DisasContext *ctx) -{ - target_long simm =3D SIMM(ctx->opcode); - - if (rA(ctx->opcode) =3D=3D 0) { - /* lis case */ - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); - } else { - tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rA(ctx->opcode)], simm << 16); - } -} - /* addpcis */ static void gen_addpcis(DisasContext *ctx) { @@ -7817,10 +7790,8 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, = PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), -GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index be75085cee..344a3ed54b 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -16,3 +16,47 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ + +/* + * Incorporate CIA into the constant when R=3D1. + * Validate that when R=3D1, RA=3D0. + */ +static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) +{ + d->rt =3D a->rt; + d->ra =3D a->ra; + d->si =3D a->si; + if (a->r) { + if (unlikely(a->ra !=3D 0)) { + gen_invalid(ctx); + return false; + } + d->si +=3D ctx->cia; + } + return true; +} + +static bool trans_ADDI(DisasContext *ctx, arg_D *a) +{ + if (a->ra) { + tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si); + } else { + tcg_gen_movi_tl(cpu_gpr[a->rt], a->si); + } + return true; +} + +static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a) +{ + arg_D d; + if (!resolve_PLS_D(ctx, &d, a)) { + return true; + } + return trans_ADDI(ctx, &d); +} + +static bool trans_ADDIS(DisasContext *ctx, arg_D *a) +{ + a->si <<=3D 16; + return trans_ADDI(ctx, a); +} --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; 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Tue, 1 Jun 2021 12:42:12 -0700 (PDT) Received: from localhost ([::1]:43388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAHD-0002Z3-0G for importer2@patchew.org; Tue, 01 Jun 2021 15:42:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33358) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loABE-0001nM-Dw; Tue, 01 Jun 2021 15:36:00 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABC-0002Jl-PV; Tue, 01 Jun 2021 15:36:00 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:42 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id C0FFA80148B; Tue, 1 Jun 2021 16:35:41 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 05/14] target/ppc: Implement PNOP Date: Tue, 1 Jun 2021 16:35:19 -0300 Message-Id: <20210601193528.2533031-6-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:42.0252 (UTC) FILETIME=[4F0B2EC0:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Richard Henderson The illegal suffix behavior matches what was observed in a POWER10 DD2.0 machine. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode | 67 ++++++++++++++++++++++ target/ppc/translate/fixedpoint-impl.c.inc | 11 ++++ 2 files changed, 78 insertions(+) diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 1965088915..9aa5097a98 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -28,3 +28,70 @@ =20 PADDI 000001 10 0--.-- .................. \ 001110 ..... ..... ................ @PLS_D + +### Prefixed No-operation Instruction + +@PNOP 000001 11 0000-- 000000000000000000 \ + ................................ + +{ + [ + ## Invalid suffixes: Branch instruction + # bc[l][a] + INVALID ................................ \ + 010000-------------------------- @PNOP + # b[l][a] + INVALID ................................ \ + 010010-------------------------- @PNOP + # bclr[l] + INVALID ................................ \ + 010011---------------0000010000- @PNOP + # bcctr[l] + INVALID ................................ \ + 010011---------------1000010000- @PNOP + # bctar[l] + INVALID ................................ \ + 010011---------------1000110000- @PNOP + + ## Invalid suffixes: rfebb + INVALID ................................ \ + 010011---------------0010010010- @PNOP + + ## Invalid suffixes: context synchronizing other than isync + # sc + INVALID ................................ \ + 010001------------------------1- @PNOP + # scv + INVALID ................................ \ + 010001------------------------01 @PNOP + # rfscv + INVALID ................................ \ + 010011---------------0001010010- @PNOP + # rfid + INVALID ................................ \ + 010011---------------0000010010- @PNOP + # hrfid + INVALID ................................ \ + 010011---------------0100010010- @PNOP + # urfid + INVALID ................................ \ + 010011---------------0100110010- @PNOP + # stop + INVALID ................................ \ + 010011---------------0101110010- @PNOP + # mtmsr w/ L=3D0 + INVALID ................................ \ + 011111---------0-----0010010010- @PNOP + # mtmsrd w/ L=3D0 + INVALID ................................ \ + 011111---------0-----0010110010- @PNOP + + ## Invalid suffixes: Service Processor Attention + INVALID ................................ \ + 000000----------------100000000- @PNOP + ] + + ## Valid suffixes + PNOP ................................ \ + -------------------------------- @PNOP +} diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 344a3ed54b..ce034a14a7 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -60,3 +60,14 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a) a->si <<=3D 16; return trans_ADDI(ctx, a); } + +static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a) +{ + gen_invalid(ctx); + return true; +} + +static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a) +{ + return true; +} --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1622576318; cv=none; d=zohomail.com; s=zohoarc; b=NL58tK6xkNMOfVzR0Z8CQweiCcniUvuYbWwAyZoDu8tdEYuoPZJdcNIwbVyRivLoOnxesL/W/CUwiV5SPbX3/mQxVMSL/MUk8B3X3pTvJTYwVqzMfXiuwIS84h2IQrkYpm3fe8oX66sNlm41ztKDjXK8gZg3zeDV0wi9iBOJp1k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622576318; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Tue, 01 Jun 2021 15:36:03 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:42 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 4584C80148C; Tue, 1 Jun 2021 16:35:42 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 06/14] target/ppc: Move D/DS/X-form integer loads to decodetree Date: Tue, 1 Jun 2021 16:35:20 -0300 Message-Id: <20210601193528.2533031-7-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:42.0753 (UTC) FILETIME=[4F57A110:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Richard Henderson These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 37 ++++++ target/ppc/translate.c | 147 ++++----------------- target/ppc/translate/fixedpoint-impl.c.inc | 89 +++++++++++++ 3 files changed, 150 insertions(+), 123 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e7c062d8b4..70f64c235b 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -20,6 +20,43 @@ &D rt ra si:int64_t @D ...... rt:5 ra:5 si:s16 &D =20 +%ds_si 2:s14 !function=3Dtimes_4 +@DS ...... rt:5 ra:5 .............. .. &D si=3D%ds_si + +&X rt ra rb +@X ...... rt:5 ra:5 rb:5 .......... . &X + +### Fixed-Point Load Instructions + +LBZ 100010 ..... ..... ................ @D +LBZU 100011 ..... ..... ................ @D +LBZX 011111 ..... ..... ..... 0001010111 - @X +LBZUX 011111 ..... ..... ..... 0001110111 - @X + +LHZ 101000 ..... ..... ................ @D +LHZU 101001 ..... ..... ................ @D +LHZX 011111 ..... ..... ..... 0100010111 - @X +LHZUX 011111 ..... ..... ..... 0100110111 - @X + +LHA 101010 ..... ..... ................ @D +LHAU 101011 ..... ..... ................ @D +LHAX 011111 ..... ..... ..... 0101010111 - @X +LHAXU 011111 ..... ..... ..... 0101110111 - @X + +LWZ 100000 ..... ..... ................ @D +LWZU 100001 ..... ..... ................ @D +LWZX 011111 ..... ..... ..... 0000010111 - @X +LWZUX 011111 ..... ..... ..... 0000110111 - @X + +LWA 111010 ..... ..... ..............10 @DS +LWAX 011111 ..... ..... ..... 0101010101 - @X +LWAUX 011111 ..... ..... ..... 0101110101 - @X + +LD 111010 ..... ..... ..............00 @DS +LDU 111010 ..... ..... ..............01 @DS +LDX 011111 ..... ..... ..... 0000010101 - @X +LDUX 011111 ..... ..... ..... 0000110101 - @X + ### Fixed-Point Arithmetic Instructions =20 ADDI 001110 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3012c7447a..d9238d1d10 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3323,54 +3323,6 @@ GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) #endif =20 -#define GEN_LD(name, ldop, opc, type) = \ -static void glue(gen_, name)(DisasContext *ctx) = \ -{ = \ - TCGv EA; = \ - gen_set_access_type(ctx, ACCESS_INT); = \ - EA =3D tcg_temp_new(); = \ - gen_addr_imm_index(ctx, EA, 0); = \ - gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); = \ - tcg_temp_free(EA); = \ -} - -#define GEN_LDU(name, ldop, opc, type) = \ -static void glue(gen_, name##u)(DisasContext *ctx) = \ -{ = \ - TCGv EA; = \ - if (unlikely(rA(ctx->opcode) =3D=3D 0 || = \ - rA(ctx->opcode) =3D=3D rD(ctx->opcode))) { = \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); = \ - return; = \ - } = \ - gen_set_access_type(ctx, ACCESS_INT); = \ - EA =3D tcg_temp_new(); = \ - if (type =3D=3D PPC_64B) = \ - gen_addr_imm_index(ctx, EA, 0x03); = \ - else = \ - gen_addr_imm_index(ctx, EA, 0); = \ - gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); = \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); = \ - tcg_temp_free(EA); = \ -} - -#define GEN_LDUX(name, ldop, opc2, opc3, type) = \ -static void glue(gen_, name##ux)(DisasContext *ctx) = \ -{ = \ - TCGv EA; = \ - if (unlikely(rA(ctx->opcode) =3D=3D 0 || = \ - rA(ctx->opcode) =3D=3D rD(ctx->opcode))) { = \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); = \ - return; = \ - } = \ - gen_set_access_type(ctx, ACCESS_INT); = \ - EA =3D tcg_temp_new(); = \ - gen_addr_reg_index(ctx, EA); = \ - gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); = \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); = \ - tcg_temp_free(EA); = \ -} - #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) = \ static void glue(gen_, name##x)(DisasContext *ctx) = \ { = \ @@ -3389,21 +3341,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) = \ #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) = \ GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) =20 -#define GEN_LDS(name, ldop, op, type) = \ -GEN_LD(name, ldop, op | 0x20, type); = \ -GEN_LDU(name, ldop, op | 0x21, type); = \ -GEN_LDUX(name, ldop, 0x17, op | 0x01, type); = \ -GEN_LDX(name, ldop, 0x17, op | 0x00, type) - -/* lbz lbzu lbzux lbzx */ -GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); -/* lha lhau lhaux lhax */ -GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); -/* lhz lhzu lhzux lhzx */ -GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); -/* lwz lwzu lwzux lwzx */ -GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); - #define GEN_LDEPX(name, ldop, opc2, opc3) = \ static void glue(gen_, name##epx)(DisasContext *ctx) = \ { = \ @@ -3424,47 +3361,12 @@ GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) #endif =20 #if defined(TARGET_PPC64) -/* lwaux */ -GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); -/* lwax */ -GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); -/* ldux */ -GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); -/* ldx */ -GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); - /* CI load/store variants */ GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) =20 -static void gen_ld(DisasContext *ctx) -{ - TCGv EA; - if (Rc(ctx->opcode)) { - if (unlikely(rA(ctx->opcode) =3D=3D 0 || - rA(ctx->opcode) =3D=3D rD(ctx->opcode))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - } - gen_set_access_type(ctx, ACCESS_INT); - EA =3D tcg_temp_new(); - gen_addr_imm_index(ctx, EA, 0x03); - if (ctx->opcode & 0x02) { - /* lwa (lwau is undefined) */ - gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); - } else { - /* ld - ldu */ - gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); - } - if (Rc(ctx->opcode)) { - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); - } - tcg_temp_free(EA); -} - /* lq */ static void gen_lq(DisasContext *ctx) { @@ -7637,6 +7539,14 @@ static inline void set_avr64(int regno, TCGv_i64 src= , bool high) tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); } =20 +/* + * Helpers for decodetree used by !function for decoding arguments. + */ +static int times_4(DisasContext *ctx, int x) +{ + return x * 4; +} + /* * Helpers for trans_* functions to check for specific insns flags. * Use token pasting to ensure that we use the proper flag with the @@ -7663,6 +7573,21 @@ static inline void set_avr64(int regno, TCGv_i64 src= , bool high) # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) #endif =20 +/* + * Helpers for implementing sets of trans_* functions. + * Defer the implementation of NAME to FUNC, with optional extra arguments. + */ +#define TRANS(NAME, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { return FUNC(ctx, a, __VA_ARGS__); } + +#define TRANS64(NAME, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } + +/* TODO: More TRANS* helpers for extra insn_flags checks. */ + + #include "decode-insn32.c.inc" #include "decode-insn64.c.inc" #include "translate/fixedpoint-impl.c.inc" @@ -7847,7 +7772,6 @@ GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1= B, 0x00000000, PPC_NONE, PPC2_ISA300), #endif #if defined(TARGET_PPC64) -GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), #endif @@ -8213,34 +8137,11 @@ GEN_PPC64_R2(rldcr, 0x1E, 0x09), GEN_PPC64_R4(rldimi, 0x1E, 0x06), #endif =20 -#undef GEN_LD -#undef GEN_LDU -#undef GEN_LDUX #undef GEN_LDX_E -#undef GEN_LDS -#define GEN_LD(name, ldop, opc, type) = \ -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_LDU(name, ldop, opc, type) = \ -GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_LDUX(name, ldop, opc2, opc3, type) = \ -GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) = \ GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), -#define GEN_LDS(name, ldop, op, type) = \ -GEN_LD(name, ldop, op | 0x20, type) = \ -GEN_LDU(name, ldop, op | 0x21, type) = \ -GEN_LDUX(name, ldop, 0x17, op | 0x01, type) = \ -GEN_LDX(name, ldop, 0x17, op | 0x00, type) - -GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) -GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) -GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) -GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) + #if defined(TARGET_PPC64) -GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) -GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) -GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) -GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) =20 /* HV/P7 and later only */ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index ce034a14a7..6140dd41ca 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -36,6 +36,95 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, a= rg_PLS_D *a) return true; } =20 +/* + * Fixed-Point Load/Store Instructions + */ + +static bool do_ldst(DisasContext *ctx, int rt, int ra, TCGv displ, bool up= date, + bool store, MemOp mop) +{ + TCGv ea; + + if (update && (ra =3D=3D 0 || (!store && ra =3D=3D rt))) { + gen_invalid(ctx); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + + ea =3D tcg_temp_new(); + if (ra) { + tcg_gen_add_tl(ea, cpu_gpr[ra], displ); + } else { + tcg_gen_mov_tl(ea, displ); + } + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(ea, ea); + } + mop ^=3D ctx->default_tcg_memop_mask; + if (store) { + tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop); + } else { + tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop); + } + if (update) { + tcg_gen_mov_tl(cpu_gpr[ra], ea); + } + tcg_temp_free(ea); + + return true; +} + +static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store, + MemOp mop) +{ + return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, stor= e, mop); +} + +static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update, + bool store, MemOp mop) +{ + return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop); +} + +/* Load Byte and Zero */ +TRANS(LBZ, do_ldst_D, false, false, MO_UB) +TRANS(LBZX, do_ldst_X, false, false, MO_UB) +TRANS(LBZU, do_ldst_D, true, false, MO_UB) +TRANS(LBZUX, do_ldst_X, true, false, MO_UB) + +/* Load Halfword and Zero */ +TRANS(LHZ, do_ldst_D, false, false, MO_UW) +TRANS(LHZX, do_ldst_X, false, false, MO_UW) +TRANS(LHZU, do_ldst_D, true, false, MO_UW) +TRANS(LHZUX, do_ldst_X, true, false, MO_UW) + +/* Load Halfword Algebraic */ +TRANS(LHA, do_ldst_D, false, false, MO_SW) +TRANS(LHAX, do_ldst_X, false, false, MO_SW) +TRANS(LHAU, do_ldst_D, true, false, MO_SW) +TRANS(LHAXU, do_ldst_X, true, false, MO_SW) + +/* Load Word and Zero */ +TRANS(LWZ, do_ldst_D, false, false, MO_UL) +TRANS(LWZX, do_ldst_X, false, false, MO_UL) +TRANS(LWZU, do_ldst_D, true, false, MO_UL) +TRANS(LWZUX, do_ldst_X, true, false, MO_UL) + +/* Load Word Algebraic */ +TRANS64(LWA, do_ldst_D, false, false, MO_SL) +TRANS64(LWAX, do_ldst_X, false, false, MO_SL) +TRANS64(LWAUX, do_ldst_X, true, false, MO_SL) + +/* Load Doubleword */ +TRANS64(LD, do_ldst_D, false, false, MO_Q) +TRANS64(LDX, do_ldst_X, false, false, MO_Q) +TRANS64(LDU, do_ldst_D, true, false, MO_Q) +TRANS64(LDUX, do_ldst_X, true, false, MO_Q) + +/* + * Fixed-Point Arithmetic Instructions + */ + static bool trans_ADDI(DisasContext *ctx, arg_D *a) { if (a->ra) { --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 1 Jun 2021 12:42:14 -0700 (PDT) Received: from localhost ([::1]:43470 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAHF-0002cn-6l for importer2@patchew.org; Tue, 01 Jun 2021 15:42:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33384) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loABK-00023C-97; Tue, 01 Jun 2021 15:36:06 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABI-0002Jl-LH; Tue, 01 Jun 2021 15:36:06 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:43 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id BF2B980148B; Tue, 1 Jun 2021 16:35:42 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 07/14] target/ppc: Implement prefixed integer load instructions Date: Tue, 1 Jun 2021 16:35:21 -0300 Message-Id: <20210601193528.2533031-8-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:43.0252 (UTC) FILETIME=[4FA3C540:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode | 15 +++++++++++++++ target/ppc/translate/fixedpoint-impl.c.inc | 16 ++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 9aa5097a98..547bd1736f 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -24,6 +24,21 @@ ...... rt:5 ra:5 ................ \ &PLS_D si=3D%pls_si =20 +### Fixed-Point Load Instructions + +PLBZ 000001 10 0--.-- .................. \ + 100010 ..... ..... ................ @PLS_D +PLHZ 000001 10 0--.-- .................. \ + 101000 ..... ..... ................ @PLS_D +PLHA 000001 10 0--.-- .................. \ + 101010 ..... ..... ................ @PLS_D +PLWZ 000001 10 0--.-- .................. \ + 100000 ..... ..... ................ @PLS_D +PLWA 000001 00 0--.-- .................. \ + 101001 ..... ..... ................ @PLS_D +PLD 000001 00 0--.-- .................. \ + 111001 ..... ..... ................ @PLS_D + ### Fixed-Point Arithmetic Instructions =20 PADDI 000001 10 0--.-- .................. \ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 6140dd41ca..7687f31d6f 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -80,6 +80,16 @@ static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool = update, bool store, return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, stor= e, mop); } =20 +static bool do_ldst_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update, + bool store, MemOp mop) +{ + arg_D d; + if (!resolve_PLS_D(ctx, &d, a)) { + return true; + } + return do_ldst_D(ctx, &d, update, store, mop); +} + static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update, bool store, MemOp mop) { @@ -91,35 +101,41 @@ TRANS(LBZ, do_ldst_D, false, false, MO_UB) TRANS(LBZX, do_ldst_X, false, false, MO_UB) TRANS(LBZU, do_ldst_D, true, false, MO_UB) TRANS(LBZUX, do_ldst_X, true, false, MO_UB) +TRANS(PLBZ, do_ldst_PLS_D, false, false, MO_UB) =20 /* Load Halfword and Zero */ TRANS(LHZ, do_ldst_D, false, false, MO_UW) TRANS(LHZX, do_ldst_X, false, false, MO_UW) TRANS(LHZU, do_ldst_D, true, false, MO_UW) TRANS(LHZUX, do_ldst_X, true, false, MO_UW) +TRANS(PLHZ, do_ldst_PLS_D, false, false, MO_UW) =20 /* Load Halfword Algebraic */ TRANS(LHA, do_ldst_D, false, false, MO_SW) TRANS(LHAX, do_ldst_X, false, false, MO_SW) TRANS(LHAU, do_ldst_D, true, false, MO_SW) TRANS(LHAXU, do_ldst_X, true, false, MO_SW) +TRANS(PLHA, do_ldst_PLS_D, false, false, MO_SW) =20 /* Load Word and Zero */ TRANS(LWZ, do_ldst_D, false, false, MO_UL) TRANS(LWZX, do_ldst_X, false, false, MO_UL) TRANS(LWZU, do_ldst_D, true, false, MO_UL) TRANS(LWZUX, do_ldst_X, true, false, MO_UL) +TRANS(PLWZ, do_ldst_PLS_D, false, false, MO_UL) =20 /* Load Word Algebraic */ TRANS64(LWA, do_ldst_D, false, false, MO_SL) TRANS64(LWAX, do_ldst_X, false, false, MO_SL) TRANS64(LWAUX, do_ldst_X, true, false, MO_SL) +TRANS64(PLWA, do_ldst_PLS_D, false, false, MO_SL) =20 /* Load Doubleword */ TRANS64(LD, do_ldst_D, false, false, MO_Q) TRANS64(LDX, do_ldst_X, false, false, MO_Q) TRANS64(LDU, do_ldst_D, true, false, MO_Q) TRANS64(LDUX, do_ldst_X, true, false, MO_Q) +TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q) =20 /* * Fixed-Point Arithmetic Instructions --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 1 Jun 2021 12:42:17 -0700 (PDT) Received: from localhost ([::1]:43668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAHI-0002lI-6J for importer2@patchew.org; Tue, 01 Jun 2021 15:42:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loABN-0002B4-4z; Tue, 01 Jun 2021 15:36:09 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABL-0002Jl-BT; Tue, 01 Jun 2021 15:36:08 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:43 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 43E4C80148C; Tue, 1 Jun 2021 16:35:43 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 08/14] target/ppc: Move D/DS/X-form integer stores to decodetree Date: Tue, 1 Jun 2021 16:35:22 -0300 Message-Id: <20210601193528.2533031-9-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:43.0737 (UTC) FILETIME=[4FEDC690:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Richard Henderson These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 22 ++++++ target/ppc/translate.c | 85 +--------------------- target/ppc/translate/fixedpoint-impl.c.inc | 24 ++++++ 3 files changed, 49 insertions(+), 82 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 70f64c235b..00ec0f4328 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -57,6 +57,28 @@ LDU 111010 ..... ..... ..............01 = @DS LDX 011111 ..... ..... ..... 0000010101 - @X LDUX 011111 ..... ..... ..... 0000110101 - @X =20 +### Fixed-Point Store Instructions + +STB 100110 ..... ..... ................ @D +STBU 100111 ..... ..... ................ @D +STBX 011111 ..... ..... ..... 0011010111 - @X +STBUX 011111 ..... ..... ..... 0011110111 - @X + +STH 101100 ..... ..... ................ @D +STHU 101101 ..... ..... ................ @D +STHX 011111 ..... ..... ..... 0110010111 - @X +STHUX 011111 ..... ..... ..... 0110110111 - @X + +STW 100100 ..... ..... ................ @D +STWU 100101 ..... ..... ................ @D +STWX 011111 ..... ..... ..... 0010010111 - @X +STWUX 011111 ..... ..... ..... 0010110111 - @X + +STD 111110 ..... ..... ..............00 @DS +STDU 111110 ..... ..... ..............01 @DS +STDX 011111 ..... ..... ..... 0010010101 - @X +STDUX 011111 ..... ..... ..... 0010110101 - @X + ### Fixed-Point Arithmetic Instructions =20 ADDI 001110 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d9238d1d10..3c3cb1b664 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3299,7 +3299,9 @@ static void glue(gen_qemu_, stop)(DisasContext *ctx, = \ tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ } =20 +#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) +#endif GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) =20 @@ -3432,52 +3434,6 @@ static void gen_lq(DisasContext *ctx) #endif =20 /*** Integer store = ***/ -#define GEN_ST(name, stop, opc, type) = \ -static void glue(gen_, name)(DisasContext *ctx) = \ -{ = \ - TCGv EA; = \ - gen_set_access_type(ctx, ACCESS_INT); = \ - EA =3D tcg_temp_new(); = \ - gen_addr_imm_index(ctx, EA, 0); = \ - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); = \ - tcg_temp_free(EA); = \ -} - -#define GEN_STU(name, stop, opc, type) = \ -static void glue(gen_, stop##u)(DisasContext *ctx) = \ -{ = \ - TCGv EA; = \ - if (unlikely(rA(ctx->opcode) =3D=3D 0)) { = \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); = \ - return; = \ - } = \ - gen_set_access_type(ctx, ACCESS_INT); = \ - EA =3D tcg_temp_new(); = \ - if (type =3D=3D PPC_64B) = \ - gen_addr_imm_index(ctx, EA, 0x03); = \ - else = \ - gen_addr_imm_index(ctx, EA, 0); = \ - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); = \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); = \ - tcg_temp_free(EA); = \ -} - -#define GEN_STUX(name, stop, opc2, opc3, type) = \ -static void glue(gen_, name##ux)(DisasContext *ctx) = \ -{ = \ - TCGv EA; = \ - if (unlikely(rA(ctx->opcode) =3D=3D 0)) { = \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); = \ - return; = \ - } = \ - gen_set_access_type(ctx, ACCESS_INT); = \ - EA =3D tcg_temp_new(); = \ - gen_addr_reg_index(ctx, EA); = \ - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); = \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); = \ - tcg_temp_free(EA); = \ -} - #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) = \ static void glue(gen_, name##x)(DisasContext *ctx) = \ { = \ @@ -3495,19 +3451,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) = \ #define GEN_STX_HVRM(name, stop, opc2, opc3, type) = \ GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) =20 -#define GEN_STS(name, stop, op, type) = \ -GEN_ST(name, stop, op | 0x20, type); = \ -GEN_STU(name, stop, op | 0x21, type); = \ -GEN_STUX(name, stop, 0x17, op | 0x01, type); = \ -GEN_STX(name, stop, 0x17, op | 0x00, type) - -/* stb stbu stbux stbx */ -GEN_STS(stb, st8, 0x06, PPC_INTEGER); -/* sth sthu sthux sthx */ -GEN_STS(sth, st16, 0x0C, PPC_INTEGER); -/* stw stwu stwux stwx */ -GEN_STS(stw, st32, 0x04, PPC_INTEGER); - #define GEN_STEPX(name, stop, opc2, opc3) = \ static void glue(gen_, name##epx)(DisasContext *ctx) = \ { = \ @@ -3529,8 +3472,6 @@ GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) #endif =20 #if defined(TARGET_PPC64) -GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); -GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) @@ -8166,31 +8107,11 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) #endif =20 -#undef GEN_ST -#undef GEN_STU -#undef GEN_STUX #undef GEN_STX_E -#undef GEN_STS -#define GEN_ST(name, stop, opc, type) = \ -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_STU(name, stop, opc, type) = \ -GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_STUX(name, stop, opc2, opc3, type) = \ -GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) = \ GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), -#define GEN_STS(name, stop, op, type) = \ -GEN_ST(name, stop, op | 0x20, type) = \ -GEN_STU(name, stop, op | 0x21, type) = \ -GEN_STUX(name, stop, 0x17, op | 0x01, type) = \ -GEN_STX(name, stop, 0x17, op | 0x00, type) - -GEN_STS(stb, st8, 0x06, PPC_INTEGER) -GEN_STS(sth, st16, 0x0C, PPC_INTEGER) -GEN_STS(stw, st32, 0x04, PPC_INTEGER) + #if defined(TARGET_PPC64) -GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) -GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 7687f31d6f..adeee33289 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -137,6 +137,30 @@ TRANS64(LDU, do_ldst_D, true, false, MO_Q) TRANS64(LDUX, do_ldst_X, true, false, MO_Q) TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q) =20 +/* Store Byte */ +TRANS(STB, do_ldst_D, false, true, MO_UB) +TRANS(STBX, do_ldst_X, false, true, MO_UB) +TRANS(STBU, do_ldst_D, true, true, MO_UB) +TRANS(STBUX, do_ldst_X, true, true, MO_UB) + +/* Store Halfword */ +TRANS(STH, do_ldst_D, false, true, MO_UW) +TRANS(STHX, do_ldst_X, false, true, MO_UW) +TRANS(STHU, do_ldst_D, true, true, MO_UW) +TRANS(STHUX, do_ldst_X, true, true, MO_UW) + +/* Store Word */ +TRANS(STW, do_ldst_D, false, true, MO_UL) +TRANS(STWX, do_ldst_X, false, true, MO_UL) +TRANS(STWU, do_ldst_D, true, true, MO_UL) +TRANS(STWUX, do_ldst_X, true, true, MO_UL) + +/* Store Doubleword */ +TRANS64(STD, do_ldst_D, false, true, MO_Q) +TRANS64(STDX, do_ldst_X, false, true, MO_Q) +TRANS64(STDU, do_ldst_D, true, true, MO_Q) +TRANS64(STDUX, do_ldst_X, true, true, MO_Q) + /* * Fixed-Point Arithmetic Instructions */ --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 1 Jun 2021 12:45:03 -0700 (PDT) Received: from localhost ([::1]:52440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAJx-0000Dv-OT for importer2@patchew.org; Tue, 01 Jun 2021 15:45:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loABP-0002Hu-Sg; Tue, 01 Jun 2021 15:36:11 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABO-0002Jl-As; Tue, 01 Jun 2021 15:36:11 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:44 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id BC6D580148B; Tue, 1 Jun 2021 16:35:43 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 09/14] target/ppc: Implement prefixed integer store instructions Date: Tue, 1 Jun 2021 16:35:23 -0300 Message-Id: <20210601193528.2533031-10-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:44.0221 (UTC) FILETIME=[5037A0D0:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode | 12 ++++++++++++ target/ppc/translate/fixedpoint-impl.c.inc | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 547bd1736f..72c5944a53 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -39,6 +39,18 @@ PLWA 000001 00 0--.-- .................. \ PLD 000001 00 0--.-- .................. \ 111001 ..... ..... ................ @PLS_D =20 +### Fixed-Point Store Instructions + +PSTW 000001 10 0--.-- .................. \ + 100100 ..... ..... ................ @PLS_D +PSTB 000001 10 0--.-- .................. \ + 100110 ..... ..... ................ @PLS_D +PSTH 000001 10 0--.-- .................. \ + 101100 ..... ..... ................ @PLS_D + +PSTD 000001 00 0--.-- .................. \ + 111101 ..... ..... ................ @PLS_D + ### Fixed-Point Arithmetic Instructions =20 PADDI 000001 10 0--.-- .................. \ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index adeee33289..2d2d874146 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -142,24 +142,28 @@ TRANS(STB, do_ldst_D, false, true, MO_UB) TRANS(STBX, do_ldst_X, false, true, MO_UB) TRANS(STBU, do_ldst_D, true, true, MO_UB) TRANS(STBUX, do_ldst_X, true, true, MO_UB) +TRANS(PSTB, do_ldst_PLS_D, false, true, MO_UB) =20 /* Store Halfword */ TRANS(STH, do_ldst_D, false, true, MO_UW) TRANS(STHX, do_ldst_X, false, true, MO_UW) TRANS(STHU, do_ldst_D, true, true, MO_UW) TRANS(STHUX, do_ldst_X, true, true, MO_UW) +TRANS(PSTH, do_ldst_PLS_D, false, true, MO_UW) =20 /* Store Word */ TRANS(STW, do_ldst_D, false, true, MO_UL) TRANS(STWX, do_ldst_X, false, true, MO_UL) TRANS(STWU, do_ldst_D, true, true, MO_UL) TRANS(STWUX, do_ldst_X, true, true, MO_UL) +TRANS(PSTW, do_ldst_PLS_D, false, true, MO_UL) =20 /* Store Doubleword */ TRANS64(STD, do_ldst_D, false, true, MO_Q) TRANS64(STDX, do_ldst_X, false, true, MO_Q) TRANS64(STDU, do_ldst_D, true, true, MO_Q) TRANS64(STDUX, do_ldst_X, true, true, MO_Q) +TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q) =20 /* * Fixed-Point Arithmetic Instructions --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 1 Jun 2021 12:45:23 -0700 (PDT) Received: from localhost ([::1]:53372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAKI-0000sX-NX for importer2@patchew.org; Tue, 01 Jun 2021 15:45:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loABS-0002PY-HP; Tue, 01 Jun 2021 15:36:14 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABR-0002Jl-0E; Tue, 01 Jun 2021 15:36:14 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:44 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 3B24680148B; Tue, 1 Jun 2021 16:35:44 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 10/14] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions Date: Tue, 1 Jun 2021 16:35:24 -0300 Message-Id: <20210601193528.2533031-11-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:44.0706 (UTC) FILETIME=[5081A220:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Matheus Ferst Implements the following PowerISA v3.1 instructions: setbc: Set Boolean Condition setbcr: Set Boolean Condition Reverse setnbc: Set Negative Boolean Condition setnbcr: Set Negative Boolean Condition Reverse Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 10 ++++++++++ target/ppc/translate/fixedpoint-impl.c.inc | 23 ++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 00ec0f4328..bc69c70493 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -26,6 +26,9 @@ &X rt ra rb @X ...... rt:5 ra:5 rb:5 .......... . &X =20 +&X_bi rt bi +@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi + ### Fixed-Point Load Instructions =20 LBZ 100010 ..... ..... ................ @D @@ -83,3 +86,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - = @X =20 ADDI 001110 ..... ..... ................ @D ADDIS 001111 ..... ..... ................ @D + +### Move To/From System Register Instructions + +SETBC 011111 ..... ..... ----- 0110000000 - @X_bi +SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi +SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi +SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 2d2d874146..5f9845fa40 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -204,3 +204,26 @@ static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a) { return true; } + +static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, boo= l rev) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + uint32_t mask =3D 0x08 >> (a->bi & 0x03); + TCGCond cond =3D rev ? TCG_COND_EQ : TCG_COND_NE; + TCGv temp =3D tcg_temp_new(); + + tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]); + tcg_gen_andi_tl(temp, temp, mask); + tcg_gen_setcondi_tl(cond, cpu_gpr[a->rt], temp, 0); + if (neg) { + tcg_gen_neg_tl(cpu_gpr[a->rt], cpu_gpr[a->rt]); + } + tcg_temp_free(temp); + + return true; +} + +TRANS(SETBC, do_set_bool_cond, false, false) +TRANS(SETBCR, do_set_bool_cond, false, true) +TRANS(SETNBC, do_set_bool_cond, true, false) +TRANS(SETNBCR, do_set_bool_cond, true, true) --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1622576931; cv=none; d=zohomail.com; s=zohoarc; b=Y/radccW2o+ZP9IOuH739y6Ugnk/30Vhb1L2pX3kMl/s+j/Jcg4/hcF6XnyUsz+mx9JlGtUbIAKs5vZROghY+ppkuH1tM+KicD94iJWLzA035gsvEdNPESco8TBY+CKJRm0I1GGHKWZtUrTX3oxkkrtdtyydNqFDH3vglVV7s+4= ARC-Message-Signature: i=1; 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Tue, 01 Jun 2021 15:48:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33458) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loABV-0002Wy-6M; Tue, 01 Jun 2021 15:36:17 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABT-0002Jl-Ip; Tue, 01 Jun 2021 15:36:16 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:45 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id B30C080148B; Tue, 1 Jun 2021 16:35:44 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 11/14] target/ppc: Implement cfuged instruction Date: Tue, 1 Jun 2021 16:35:25 -0300 Message-Id: <20210601193528.2533031-12-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:45.0206 (UTC) FILETIME=[50CDED60:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Matheus Ferst Signed-off-by: Matheus Ferst Reviewed-by: Richard Henderson --- target/ppc/helper.h | 1 + target/ppc/insn32.decode | 4 ++ target/ppc/int_helper.c | 62 ++++++++++++++++++++++ target/ppc/translate/fixedpoint-impl.c.inc | 12 +++++ 4 files changed, 79 insertions(+) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index ea9f2a236c..c517b9f025 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -46,6 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32) DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_3(sraw, tl, env, tl, tl) +DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64) #if defined(TARGET_PPC64) DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl) DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index bc69c70493..d4044d9069 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -87,6 +87,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - = @X ADDI 001110 ..... ..... ................ @D ADDIS 001111 ..... ..... ................ @D =20 +## Fixed-Point Logical Instructions + +CFUGED 011111 ..... ..... ..... 0011011100 - @X + ### Move To/From System Register Instructions =20 SETBC 011111 ..... ..... ----- 0110000000 - @X_bi diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 41f8477d4b..efa833ef64 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -320,6 +320,68 @@ target_ulong helper_popcntb(target_ulong val) } #endif =20 +uint64_t helper_cfuged(uint64_t src, uint64_t mask) +{ + /* + * Instead of processing the mask bit-by-bit from the most significant= to + * the least significant bit, as described in PowerISA, we'll handle i= t in + * blocks of 'n' zeros/ones from LSB to MSB. To avoid the decision to = use + * ctz or cto, we negate the mask at the end of the loop. + */ + target_ulong m, left =3D 0, right =3D 0; + unsigned int n, i =3D 64; + bool bit =3D false; /* tracks if we are processing zeros or ones */ + + if (mask =3D=3D 0 || mask =3D=3D -1) { + return src; + } + + /* Processes the mask in blocks, from LSB to MSB */ + while (i) { + /* Find how many bits we should take */ + n =3D ctz64(mask); + if (n > i) { + n =3D i; + } + + /* + * Extracts 'n' trailing bits of src and put them on the leading '= n' + * bits of 'right' or 'left', pushing down the previously extracted + * values. + */ + m =3D (1ll << n) - 1; + if (bit) { + right =3D ror64(right | (src & m), n); + } else { + left =3D ror64(left | (src & m), n); + } + + /* + * Discards the processed bits from 'src' and 'mask'. Note that we= are + * removing 'n' trailing zeros from 'mask', but the logical shift = will + * add 'n' leading zeros back, so the population count of 'mask' i= s kept + * the same. + */ + src >>=3D n; + mask >>=3D n; + i -=3D n; + bit =3D !bit; + mask =3D ~mask; + } + + /* + * At the end, right was ror'ed ctpop(mask) times. To put it back in p= lace, + * we'll shift it more 64-ctpop(mask) times. + */ + if (bit) { + n =3D ctpop64(mask); + } else { + n =3D 64 - ctpop64(mask); + } + + return left | (right >> n); +} + /*************************************************************************= ****/ /* PowerPC 601 specific instructions (POWER bridge) */ target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong = arg2) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 5f9845fa40..50933a3b9d 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -227,3 +227,15 @@ TRANS(SETBC, do_set_bool_cond, false, false) TRANS(SETBCR, do_set_bool_cond, false, true) TRANS(SETNBC, do_set_bool_cond, true, false) TRANS(SETNBCR, do_set_bool_cond, true, true) + +static bool trans_CFUGED(DisasContext *ctx, arg_X *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA310); +#if defined(TARGET_PPC64) + gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]); +#else + qemu_build_not_reached(); +#endif + return true; +} --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1622576920; cv=none; d=zohomail.com; s=zohoarc; b=Y/B8cnOPQteX4zeAFR4NIdShTereXoK3+TNwHt6DUgnTNfN1NvQScGZPjIEWQcG7+67UlYBseIzH8NGVeavEnOW/1YNn+70rhyutkrCwbv2up/6nYdJxLWslI+LfCetUshRcW8eh6JsZL5t5bcHTKEjw0l5kZA9U3Jl6jVO78T8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622576920; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Z4lViQiSeUK9c0TRAOJDvNFwUtgr/NPzL01oenXFGxk=; b=FY2/tWoZhGL4to8OaR+iz0z3YMdhLjB0SD7Lvur98q1qw1QSs4EMeLx7JJyP8xpVxDO1r2Pfb3fERCZm6ULgsp3l7dbrdZHdiLBhZ7vguibrOGa7Zhsl/BKwFBaYdxQQl8kj0E/7sgwJg+WkqNV3dK1J0XP/8ds/BIsXhuFqYTs= ARC-Authentication-Results: i=1; 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Tue, 1 Jun 2021 16:35:45 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 392E280148B; Tue, 1 Jun 2021 16:35:45 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 12/14] target/ppc: Implement vcfuged instruction Date: Tue, 1 Jun 2021 16:35:26 -0300 Message-Id: <20210601193528.2533031-13-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:45.0706 (UTC) FILETIME=[511A38A0:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Matheus Ferst Signed-off-by: Matheus Ferst Reviewed-by: Richard Henderson --- target/ppc/insn32.decode | 7 ++++ target/ppc/translate.c | 1 + target/ppc/translate/vector-impl.c.inc | 56 ++++++++++++++++++++++++++ 3 files changed, 64 insertions(+) create mode 100644 target/ppc/translate/vector-impl.c.inc diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index d4044d9069..77edf407ab 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -23,6 +23,9 @@ %ds_si 2:s14 !function=3Dtimes_4 @DS ...... rt:5 ra:5 .............. .. &D si=3D%ds_si =20 +&VX vrt vra vrb +@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX + &X rt ra rb @X ...... rt:5 ra:5 rb:5 .......... . &X =20 @@ -97,3 +100,7 @@ SETBC 011111 ..... ..... ----- 0110000000 - = @X_bi SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi + +## Vector Bit Manipulation Instruction + +VCFUGED 000100 ..... ..... ..... 10101001101 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3c3cb1b664..ed5515f8e2 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7538,6 +7538,7 @@ static int times_4(DisasContext *ctx, int x) #include "translate/vmx-impl.c.inc" =20 #include "translate/vsx-impl.c.inc" +#include "translate/vector-impl.c.inc" =20 #include "translate/dfp-impl.c.inc" =20 diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/= vector-impl.c.inc new file mode 100644 index 0000000000..117ce9b137 --- /dev/null +++ b/target/ppc/translate/vector-impl.c.inc @@ -0,0 +1,56 @@ +/* + * Power ISA decode for Vector Facility instructions + * + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#define REQUIRE_ALTIVEC(CTX) \ + do { \ + if (unlikely(!(CTX)->altivec_enabled)) { \ + gen_exception((CTX), POWERPC_EXCP_VPU); \ + return true; \ + } \ + } while (0) + +static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a) +{ + TCGv_i64 tgt, src, mask; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_ALTIVEC(ctx); + + tgt =3D tcg_temp_new_i64(); + src =3D tcg_temp_new_i64(); + mask =3D tcg_temp_new_i64(); + + /* centrifuge lower double word */ + get_cpu_vsrl(src, a->vra + 32); + get_cpu_vsrl(mask, a->vrb + 32); + gen_helper_cfuged(tgt, src, mask); + set_cpu_vsrl(a->vrt + 32, tgt); + + /* centrifuge higher double word */ + get_cpu_vsrh(src, a->vra + 32); + get_cpu_vsrh(mask, a->vrb + 32); + gen_helper_cfuged(tgt, src, mask); + set_cpu_vsrh(a->vrt + 32, tgt); + + tcg_temp_free_i64(tgt); + tcg_temp_free_i64(src); + tcg_temp_free_i64(mask); + + return true; +} --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1622577103; cv=none; d=zohomail.com; s=zohoarc; b=oLmEDz/lk/Ixr+PsOHb+UBxuSvLZGXTAhakKawN8hhsuBA3xsfxCa4Hth0zMC4DSBeOUZJ9MBx0rTUetJsjsjNjJYPMR463NXV80hvkDQeMMApg/H708urdBfLJzi7rk/QM183bpWzZShL0YmrIxlWw6G9uKA6OCijV96nGQNEM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622577103; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=k3LzPfF+XbDbQf7GOyGs/O9iJXA1TSHOmL2iV9ZG9ok=; b=fc/aO2vToNccU3SyYBrrliV0TMaTvSkccxz5QmcaEvVoHHzWA7so0pJS5/iSLK51tKCO6BdkY8ce+mqw74LxVISt/NZMQsSqAIRz/n1XTfgzH02uGw5AlHwamvyI8hCMXc98oMzurvP1Z3BQJt6VASPC16X6XXT3/jsHvtwZCtc= ARC-Authentication-Results: i=1; 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Tue, 1 Jun 2021 16:35:46 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id B1FA380148C; Tue, 1 Jun 2021 16:35:45 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 13/14] target/ppc: Move addpcis to decodetree Date: Tue, 1 Jun 2021 16:35:27 -0300 Message-Id: <20210601193528.2533031-14-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:46.0190 (UTC) FILETIME=[516412E0:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 6 ++++++ target/ppc/translate.c | 9 --------- target/ppc/translate/fixedpoint-impl.c.inc | 7 +++++++ 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 77edf407ab..93e5d44d9e 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -23,6 +23,10 @@ %ds_si 2:s14 !function=3Dtimes_4 @DS ...... rt:5 ra:5 .............. .. &D si=3D%ds_si =20 +&DX rt d +%dx_d 6:s10 16:5 0:1 +@DX ...... rt:5 ..... .......... ..... . &DX d=3D%dx_d + &VX vrt vra vrb @VX ...... vrt:5 vra:5 vrb:5 .......... . &VX =20 @@ -90,6 +94,8 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X ADDI 001110 ..... ..... ................ @D ADDIS 001111 ..... ..... ................ @D =20 +ADDPCIS 010011 ..... ..... .......... 00010 . @DX + ## Fixed-Point Logical Instructions =20 CFUGED 011111 ..... ..... ..... 0011011100 - @X diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ed5515f8e2..35d8831d44 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1779,14 +1779,6 @@ static void gen_addic_(DisasContext *ctx) gen_op_addic(ctx, 1); } =20 -/* addpcis */ -static void gen_addpcis(DisasContext *ctx) -{ - target_long d =3D DX(ctx->opcode); - - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16= )); -} - static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg= 1, TCGv arg2, int sign, int compute_ov) { @@ -7659,7 +7651,6 @@ GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PP= C_NONE, PPC2_ISA300), GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 50933a3b9d..2713366791 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -194,6 +194,13 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a) return trans_ADDI(ctx, a); } =20 +static bool trans_ADDPCIS(DisasContext *ctx, arg_DX *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + tcg_gen_movi_tl(cpu_gpr[a->rt], ctx->base.pc_next + (a->d << 16)); + return true; +} + static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a) { gen_invalid(ctx); --=20 2.25.1 From nobody Thu May 2 02:30:56 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1622577239; cv=none; d=zohomail.com; s=zohoarc; b=O2fnxkv+nUeqg/uQJefTTjUH/vsAgpzA0t7LwfAdt5Ks6utMLv70ReWyq01MgKWPgD87/rkrAxd6g3cS5FxIFmH6KW/Kgy/eLo1F7khHMRjk7Fp+H3c7xnx8Lctq59MLXC/XUY3pFNirNGs62o9rjqjqPhNFfk7Q8GLhX0bYnS0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622577239; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Tue, 01 Jun 2021 15:37:34 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:46 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 391D780148B; Tue, 1 Jun 2021 16:35:46 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 14/14] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree Date: Tue, 1 Jun 2021 16:35:28 -0300 Message-Id: <20210601193528.2533031-15-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 01 Jun 2021 19:35:46.0690 (UTC) FILETIME=[51B05E20:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Matheus Ferst Additionally, REQUIRE_64BIT when L=3D1 to match what is specified in The Programming Environments Manual: "For 32-bit implementations, the L field must be cleared, otherwise the instruction form is invalid." Some CPUs are known to deviate from this specification by ignoring the L bit [1]. The stricter behavior, however, can help users that test software with qemu, making it more likely to detect bugs that would otherwise be silent. If deemed necessary, a future patch can adapt this behavior based on the specific CPU model. [1] The 601 manual is the only one I've found that explicitly states that the L bit is ignored, but we also observe this behavior in a 7447A v1.2. Signed-off-by: Matheus Ferst Reviewed-by: Richard Henderson --- target/ppc/insn32.decode | 14 ++++++ target/ppc/translate.c | 52 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 33 +++++++++++++- 3 files changed, 46 insertions(+), 53 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 93e5d44d9e..9fd8d6b817 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -20,6 +20,10 @@ &D rt ra si:int64_t @D ...... rt:5 ra:5 si:s16 &D =20 +&D_bf bf l:bool ra imm +@D_bfs ...... bf:3 - l:1 ra:5 imm:s16 &D_bf +@D_bfu ...... bf:3 - l:1 ra:5 imm:16 &D_bf + %ds_si 2:s14 !function=3Dtimes_4 @DS ...... rt:5 ra:5 .............. .. &D si=3D%ds_si =20 @@ -36,6 +40,9 @@ &X_bi rt bi @X_bi ...... rt:5 bi:5 ----- .......... - &X_bi =20 +&X_bfl bf l:bool ra rb +@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl + ### Fixed-Point Load Instructions =20 LBZ 100010 ..... ..... ................ @D @@ -89,6 +96,13 @@ STDU 111110 ..... ..... ..............01 = @DS STDX 011111 ..... ..... ..... 0010010101 - @X STDUX 011111 ..... ..... ..... 0010110101 - @X =20 +### Fixed-Point Compare Instructions + +CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl +CMPL 011111 ... - . ..... ..... 0000100000 - @X_bfl +CMPI 001011 ... - . ..... ................ @D_bfs +CMPLI 001010 ... - . ..... ................ @D_bfu + ### Fixed-Point Arithmetic Instructions =20 ADDI 001110 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 35d8831d44..95e4d9b815 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1489,54 +1489,6 @@ static inline void gen_set_Rc0(DisasContext *ctx, TC= Gv reg) } } =20 -/* cmp */ -static void gen_cmp(DisasContext *ctx) -{ - if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { - gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], - 1, crfD(ctx->opcode)); - } else { - gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], - 1, crfD(ctx->opcode)); - } -} - -/* cmpi */ -static void gen_cmpi(DisasContext *ctx) -{ - if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { - gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), - 1, crfD(ctx->opcode)); - } else { - gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), - 1, crfD(ctx->opcode)); - } -} - -/* cmpl */ -static void gen_cmpl(DisasContext *ctx) -{ - if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { - gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], - 0, crfD(ctx->opcode)); - } else { - gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], - 0, crfD(ctx->opcode)); - } -} - -/* cmpli */ -static void gen_cmpli(DisasContext *ctx) -{ - if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { - gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), - 0, crfD(ctx->opcode)); - } else { - gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), - 0, crfD(ctx->opcode)); - } -} - /* cmprb - range comparison: isupper, isaplha, islower*/ static void gen_cmprb(DisasContext *ctx) { @@ -7639,10 +7591,6 @@ GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC= _NONE, PPC2_ISA310), GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), #endif GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), -GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), -GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), -GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), -GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), #if defined(TARGET_PPC64) GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), #endif diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 2713366791..1e0957f5eb 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1,4 +1,4 @@ -/* + /* * Power ISA decode for Fixed-Point Facility instructions * * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) @@ -165,6 +165,37 @@ TRANS64(STDU, do_ldst_D, true, true, MO_Q) TRANS64(STDUX, do_ldst_X, true, true, MO_Q) TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q) =20 +/* + * Fixed-Point Compare Instructions + */ + +static bool do_cmp_X(DisasContext *ctx, arg_X_bfl *a, bool s) +{ + if (a->l) { + REQUIRE_64BIT(ctx); + gen_op_cmp(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf); + } else { + gen_op_cmp32(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf); + } + return true; +} + +static bool do_cmp_D(DisasContext *ctx, arg_D_bf *a, bool s) +{ + if (a->l) { + REQUIRE_64BIT(ctx); + gen_op_cmp(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf); + } else { + gen_op_cmp32(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf); + } + return true; +} + +TRANS(CMP, do_cmp_X, true); +TRANS(CMPL, do_cmp_X, false); +TRANS(CMPI, do_cmp_D, true); +TRANS(CMPLI, do_cmp_D, false); + /* * Fixed-Point Arithmetic Instructions */ --=20 2.25.1