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Wed, 02 Jun 2021 00:22:16 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1520LdUS34341278 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 2 Jun 2021 00:21:39 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 166E8AE051; Wed, 2 Jun 2021 00:22:13 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A0D33AE045; Wed, 2 Jun 2021 00:22:12 +0000 (GMT) Received: from vm.lan (unknown [9.145.39.144]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 2 Jun 2021 00:22:12 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : content-transfer-encoding : mime-version; s=pp1; bh=3oxkLdzLMiwGVR49MTM8vKjJttzgXQJKVHejqJ/kURA=; b=NbXBYqAU5GZHlAjUCYAN+/sh1JF1a8S3G3c56MBl1WVO9Gf5mcjJosy6kSWYkfV2pdoa uOIwIFuRspCxGJAdO8aLh6PUZomd7BsNaHIqUvMWkDxXm1MO8rSD/3BOJXh8dMjWp0Oj pxGstxbpGUZwsLtL4Fz1nk1JySI/YxJoJIRZY9m+p9L7pKkeF+IvknJqxWxgskHYs1yz 1VmtZwGH5h8mTJjcdNVKCXK/vNxyxl4us6OPu+OiADYPm7V9yN+X+fAweidN4lwof/rS w9g6EcZZ2icfWg65ZWfT0mGPOLo71RvhqvEQpCSAoukkKBgmG69RYqWKufTEhy6GCD7p sA== From: Ilya Leoshkevich To: Richard Henderson , David Hildenbrand , Laurent Vivier , Cornelia Huck Subject: [PATCH v3 1/2] target/s390x: Fix SIGILL psw.addr reporting Date: Wed, 2 Jun 2021 02:22:09 +0200 Message-Id: <20210602002210.3144559-2-iii@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602002210.3144559-1-iii@linux.ibm.com> References: <20210602002210.3144559-1-iii@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: z_qgnN5oxYjg5PKI_B7JoLxt5MeAfPzO X-Proofpoint-GUID: I2_1QE_RDYqmWgQhMmrEeBmXg_CyetxZ Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-01_12:2021-06-01, 2021-06-01 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 mlxscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106010161 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=iii@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christian Borntraeger , qemu-s390x@nongnu.org, qemu-devel@nongnu.org, Ilya Leoshkevich , Andreas Krebbel Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When a s390x CPU attempts to execute an illegal instruction, an operation exception is recognized. This is a suppressing exception, which means that the PSW is advanced by the length of the illegal instruction. On the real hardware or in qemu-system-s390x the kernel then raises SIGILL with si_addr pointing to the suppressed instruction and psw.addr containing the updated PSW. Unfortunately qemu-s390x sets both to the address of the suppressed instruction at the moment. Fix by sharing the PSW advancement logic with qemu-system-s390x and setting si_addr to the address of the instruction that raised the exception. Sharing the PSW advancement logic means, however, that now the helpers and the CPU loop must follow the hardware and the kernel a little bit more strictly. In particular: * Unmapped memory accesses should result in a translation rather than in an addressing exception. * Protection exception must rewind psw.addr. * Translation exception must cause a SIGSEGV. While at it, also fix the handling of addressing and privileged operation exceptions. Buglink: https://gitlab.com/qemu-project/qemu/-/issues/319 Signed-off-by: Ilya Leoshkevich --- linux-user/s390x/cpu_loop.c | 23 ++++++++++-- target/s390x/excp_helper.c | 71 ++++++++++++++++++++----------------- target/s390x/internal.h | 1 + target/s390x/mem_helper.c | 2 +- 4 files changed, 60 insertions(+), 37 deletions(-) diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index f2d1215fb1..72ba9170ed 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -21,6 +21,7 @@ #include "qemu-common.h" #include "qemu.h" #include "cpu_loop-common.h" +#include "internal.h" =20 /* s390x masks the fault address it reports in si_addr for SIGSEGV and SIG= BUS */ #define S390X_FAIL_ADDR_MASK -4096LL @@ -29,6 +30,7 @@ void cpu_loop(CPUS390XState *env) { CPUState *cs =3D env_cpu(env); int trapnr, n, sig; + target_ulong excp_psw_addr; target_siginfo_t info; target_ulong addr; abi_long ret; @@ -38,6 +40,7 @@ void cpu_loop(CPUS390XState *env) trapnr =3D cpu_exec(cs); cpu_exec_end(cs); process_queued_cpu_work(cs); + excp_psw_addr =3D env->psw.addr; =20 switch (trapnr) { case EXCP_INTERRUPT: @@ -66,15 +69,29 @@ void cpu_loop(CPUS390XState *env) n =3D TARGET_TRAP_BRKPT; goto do_signal_pc; case EXCP_PGM: + s390_cpu_program_interrupt_advance_psw(env); n =3D env->int_pgm_code; switch (n) { case PGM_OPERATION: - case PGM_PRIVILEGED: sig =3D TARGET_SIGILL; n =3D TARGET_ILL_ILLOPC; goto do_signal_pc; - case PGM_PROTECTION: + case PGM_PRIVILEGED: + sig =3D TARGET_SIGILL; + n =3D TARGET_ILL_PRVOPC; + goto do_signal_pc; case PGM_ADDRESSING: + sig =3D TARGET_SIGILL; + n =3D TARGET_ILL_ILLADR; + goto do_signal_pc; + case PGM_PROTECTION: + /* + * Protection exception handler is special: it is the only= one + * that rewinds psw.addr. + */ + env->psw.addr =3D excp_psw_addr; + /* FALL THROUGH */ + case PGM_PAGE_TRANS: sig =3D TARGET_SIGSEGV; /* XXX: check env->error_code */ n =3D TARGET_SEGV_MAPERR; @@ -131,7 +148,7 @@ void cpu_loop(CPUS390XState *env) break; =20 do_signal_pc: - addr =3D env->psw.addr; + addr =3D excp_psw_addr; do_signal: info.si_signo =3D sig; info.si_errno =3D 0; diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index 20625c2c8f..4133e93978 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -82,6 +82,42 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t= dxc) tcg_s390_data_exception(env, dxc, GETPC()); } =20 +void s390_cpu_program_interrupt_advance_psw(CPUS390XState *env) +{ + switch (env->int_pgm_code) { + case PGM_PER: + if (env->per_perc_atmid & PER_CODE_EVENT_NULLIFICATION) { + break; + } + /* FALL THROUGH */ + case PGM_OPERATION: + case PGM_PRIVILEGED: + case PGM_EXECUTE: + case PGM_PROTECTION: + case PGM_ADDRESSING: + case PGM_SPECIFICATION: + case PGM_DATA: + case PGM_FIXPT_OVERFLOW: + case PGM_FIXPT_DIVIDE: + case PGM_DEC_OVERFLOW: + case PGM_DEC_DIVIDE: + case PGM_HFP_EXP_OVERFLOW: + case PGM_HFP_EXP_UNDERFLOW: + case PGM_HFP_SIGNIFICANCE: + case PGM_HFP_DIVIDE: + case PGM_TRANS_SPEC: + case PGM_SPECIAL_OP: + case PGM_OPERAND: + case PGM_HFP_SQRT: + case PGM_PC_TRANS_SPEC: + case PGM_ALET_SPEC: + case PGM_MONITOR: + /* advance the PSW if our exception is not nullifying */ + env->psw.addr +=3D env->int_pgm_ilen; + break; + } +} + #if defined(CONFIG_USER_ONLY) =20 void s390_cpu_do_interrupt(CPUState *cs) @@ -95,7 +131,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, { S390CPU *cpu =3D S390_CPU(cs); =20 - trigger_pgm_exception(&cpu->env, PGM_ADDRESSING); + trigger_pgm_exception(&cpu->env, PGM_PAGE_TRANS); /* On real machines this value is dropped into LowMem. Since this is userland, simply put this someplace that cpu_loop can find it. = */ cpu->env.__excp_addr =3D address; @@ -202,38 +238,7 @@ static void do_program_interrupt(CPUS390XState *env) =20 assert(ilen =3D=3D 2 || ilen =3D=3D 4 || ilen =3D=3D 6); =20 - switch (env->int_pgm_code) { - case PGM_PER: - if (env->per_perc_atmid & PER_CODE_EVENT_NULLIFICATION) { - break; - } - /* FALL THROUGH */ - case PGM_OPERATION: - case PGM_PRIVILEGED: - case PGM_EXECUTE: - case PGM_PROTECTION: - case PGM_ADDRESSING: - case PGM_SPECIFICATION: - case PGM_DATA: - case PGM_FIXPT_OVERFLOW: - case PGM_FIXPT_DIVIDE: - case PGM_DEC_OVERFLOW: - case PGM_DEC_DIVIDE: - case PGM_HFP_EXP_OVERFLOW: - case PGM_HFP_EXP_UNDERFLOW: - case PGM_HFP_SIGNIFICANCE: - case PGM_HFP_DIVIDE: - case PGM_TRANS_SPEC: - case PGM_SPECIAL_OP: - case PGM_OPERAND: - case PGM_HFP_SQRT: - case PGM_PC_TRANS_SPEC: - case PGM_ALET_SPEC: - case PGM_MONITOR: - /* advance the PSW if our exception is not nullifying */ - env->psw.addr +=3D ilen; - break; - } + s390_cpu_program_interrupt_advance_psw(env); =20 qemu_log_mask(CPU_LOG_INT, "%s: code=3D0x%x ilen=3D%d psw: %" PRIx64 " %" PRIx64 "\= n", diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 11515bb617..9f1665ccbf 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -272,6 +272,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); +void s390_cpu_program_interrupt_advance_psw(CPUS390XState *cpu); =20 =20 /* fpu_helper.c */ diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index f6a7d29273..dff19cba60 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -147,7 +147,7 @@ static int s390_probe_access(CPUArchState *env, target_= ulong addr, int size, flags =3D page_get_flags(addr); if (!(flags & (access_type =3D=3D MMU_DATA_LOAD ? PAGE_READ : PAGE_WR= ITE_ORG))) { env->__excp_addr =3D addr; - flags =3D (flags & PAGE_VALID) ? PGM_PROTECTION : PGM_ADDRESSING; + flags =3D (flags & PAGE_VALID) ? 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b=YP/c5zx98jPypfR78hOsKCX52nvhIXYYrKJCTWQnBcLVGPtaNWAzC7g29gKeGoXlVMJr 5mA4+oiMW59J9MmlYSkAsSqJc2heywxX8b2zQXGmZYn5h/NKIKOcYnWixf20hU+lF0+f n/ic6nETKnemiwpagG0tQvFODB2zzj/M3gQfvPVz/YOr4K4goGLbMksmswLzcO2xKfhu 4m0PMeG4U1h90dmUGe6vU4AZR5sJ4XuiedumqctqDCp+AdLfYrGq3gNyvSq0++nD6ggH jYqUt2+So8LamkKEu1Dp6kY9jl3ff3EUdZcBACP21iWRbU3S8nySFC0LE1BEKX+VzPkp Xg== From: Ilya Leoshkevich To: Richard Henderson , David Hildenbrand , Laurent Vivier , Cornelia Huck Subject: [PATCH v3 2/2] tests/tcg/s390x: Test SIGILL and SIGSEGV handling Date: Wed, 2 Jun 2021 02:22:10 +0200 Message-Id: <20210602002210.3144559-3-iii@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602002210.3144559-1-iii@linux.ibm.com> References: <20210602002210.3144559-1-iii@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 6tJb3niG2YcxLm-9k3lKoU27Xffry2nE X-Proofpoint-ORIG-GUID: 36Bc5SV1eIU0CMTMjeGXtSasTDkXD1iH X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-01_12:2021-06-01, 2021-06-01 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 malwarescore=0 bulkscore=0 adultscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106010161 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=iii@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christian Borntraeger , qemu-s390x@nongnu.org, qemu-devel@nongnu.org, Ilya Leoshkevich , Andreas Krebbel Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Verify that s390x-specific uc_mcontext.psw.addr is reported correctly. Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.target | 1 + tests/tcg/s390x/signal.c | 163 ++++++++++++++++++++++++++++++++ 2 files changed, 164 insertions(+) create mode 100644 tests/tcg/s390x/signal.c diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index 241ef28f61..cdb7d85316 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -8,3 +8,4 @@ TESTS+=3Dexrl-trtr TESTS+=3Dpack TESTS+=3Dmvo TESTS+=3Dmvc +TESTS+=3Dsignal diff --git a/tests/tcg/s390x/signal.c b/tests/tcg/s390x/signal.c new file mode 100644 index 0000000000..c25d7dd019 --- /dev/null +++ b/tests/tcg/s390x/signal.c @@ -0,0 +1,163 @@ +#include +#include +#include +#include +#include +#include + +/* + * Various instructions that generate SIGILL and SIGSEGV. They could have = been + * defined in a separate .s file, but this would complicate the build, so = the + * inline asm is used instead. + */ + +void illegal_op(void); +void after_illegal_op(void); +asm(".globl\tillegal_op\n" + "illegal_op:\t.byte\t0x00,0x00\n" + "\t.globl\tafter_illegal_op\n" + "after_illegal_op:\tbr\t%r14"); + +void stg(void *dst, unsigned long src); +asm(".globl\tstg\n" + "stg:\tstg\t%r3,0(%r2)\n" + "\tbr\t%r14"); + +void mvc_8(void *dst, void *src); +asm(".globl\tmvc_8\n" + "mvc_8:\tmvc\t0(8,%r2),0(%r3)\n" + "\tbr\t%r14"); + +static void safe_puts(const char *s) +{ + write(0, s, strlen(s)); + write(0, "\n", 1); +} + +enum exception { + exception_operation, + exception_translation, + exception_protection, +}; + +static struct { + int sig; + void *addr; + unsigned long psw_addr; + enum exception exception; +} expected; + +static void handle_signal(int sig, siginfo_t *info, void *ucontext) +{ + void *page; + int err; + + if (sig !=3D expected.sig) { + safe_puts("[ FAILED ] wrong signal"); + _exit(1); + } + + if (info->si_addr !=3D expected.addr) { + safe_puts("[ FAILED ] wrong si_addr"); + _exit(1); + } + + if (((ucontext_t *)ucontext)->uc_mcontext.psw.addr !=3D expected.psw_a= ddr) { + safe_puts("[ FAILED ] wrong psw.addr"); + _exit(1); + } + + switch (expected.exception) { + case exception_translation: + page =3D mmap(expected.addr, 4096, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED, -1, 0); + if (page !=3D expected.addr) { + safe_puts("[ FAILED ] mmap() failed"); + _exit(1); + } + break; + case exception_protection: + err =3D mprotect(expected.addr, 4096, PROT_READ | PROT_WRITE); + if (err !=3D 0) { + safe_puts("[ FAILED ] mprotect() failed"); + _exit(1); + } + break; + } +} + +static void check_sigsegv(void *func, enum exception exception, + unsigned long val) +{ + int prot; + unsigned long *page; + unsigned long *addr; + int err; + + prot =3D exception =3D=3D exception_translation ? PROT_NONE : PROT_REA= D; + page =3D mmap(NULL, 4096, prot, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + assert(page !=3D MAP_FAILED); + if (exception =3D=3D exception_translation) { + /* Hopefully nothing will be mapped at this address. */ + err =3D munmap(page, 4096); + assert(err =3D=3D 0); + } + addr =3D page + (val & 0x1ff); + + expected.sig =3D SIGSEGV; + expected.addr =3D page; + expected.psw_addr =3D (unsigned long)func; + expected.exception =3D exception; + if (func =3D=3D stg) { + stg(addr, val); + } else { + assert(func =3D=3D mvc_8); + mvc_8(addr, &val); + } + assert(*addr =3D=3D val); + + err =3D munmap(page, 4096); + assert(err =3D=3D 0); +} + +int main(void) +{ + struct sigaction act; + int err; + + memset(&act, 0, sizeof(act)); + act.sa_sigaction =3D handle_signal; + act.sa_flags =3D SA_SIGINFO; + err =3D sigaction(SIGILL, &act, NULL); + assert(err =3D=3D 0); + err =3D sigaction(SIGSEGV, &act, NULL); + assert(err =3D=3D 0); + + safe_puts("[ RUN ] Operation exception"); + expected.sig =3D SIGILL; + expected.addr =3D illegal_op; + expected.psw_addr =3D (unsigned long)after_illegal_op; + expected.exception =3D exception_operation; + illegal_op(); + safe_puts("[ OK ]"); + + safe_puts("[ RUN ] Translation exception from stg"); + check_sigsegv(stg, exception_translation, 42); + safe_puts("[ OK ]"); + + safe_puts("[ RUN ] Translation exception from mvc"); + check_sigsegv(mvc_8, exception_translation, 4242); + safe_puts("[ OK ]"); + + safe_puts("[ RUN ] Protection exception from stg"); + check_sigsegv(stg, exception_protection, 424242); + safe_puts("[ OK ]"); + + safe_puts("[ RUN ] Protection exception from mvc"); + check_sigsegv(mvc_8, exception_protection, 42424242); + safe_puts("[ OK ]"); + + safe_puts("[ PASSED ]"); + + return 0; +} --=20 2.31.1