From nobody Sun May 5 08:59:41 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622661283; cv=none; d=zohomail.com; s=zohoarc; b=bGczdKF4aLhupwh3eQ320u51BAj7QkBpIN3VK3IKQqdOVlVWbUqe4SjUdaQLrZ6odEu+DwoSx/419R6yWHMjWNWBj9DcrhDc6o0+IY8WY2xFSd8/FqQI6F6iQazpYoJxcWdrvp1CZV6QEGKTPym+AnAspTntGu+75em/lVt1tvg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622661283; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CAa/+EzoUulBLTSh6AZhoZXdy3/J+ZdK8xOisZ5wF38=; b=mw++s4clUbZ29qZngs/IYEwQNC2BQowTVO8z4epHHKQXQ3wWcCKqwyXTbExjg69v6IlLXEmtegGBLYzPA3ENVtUDBzPI49ObpC7ja1B07w6E8zwQNZQgtpkdNH+SV0uz7kAYEAzYc0fT4y94KBTHZJyqRC6UjmYPpb+LJmBfElA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622661283050885.6492087722087; Wed, 2 Jun 2021 12:14:43 -0700 (PDT) Received: from localhost ([::1]:45264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loWKA-0005TL-28 for importer2@patchew.org; Wed, 02 Jun 2021 15:14:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loWHZ-0000cy-ON; Wed, 02 Jun 2021 15:12:01 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:38497) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1loWHT-0001tw-KP; Wed, 02 Jun 2021 15:12:00 -0400 Received: by mail-wr1-x431.google.com with SMTP id j14so3371109wrq.5; Wed, 02 Jun 2021 12:11:54 -0700 (PDT) Received: from asus.. ([83.144.170.28]) by smtp.gmail.com with ESMTPSA id n2sm635304wmb.32.2021.06.02.12.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 12:11:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CAa/+EzoUulBLTSh6AZhoZXdy3/J+ZdK8xOisZ5wF38=; b=eduxVdH0ycvHmAD1tQ8qOjrw2LaGPNA5dLZypIkLfopXTzvciKGDdRJWcChUO6M1pi NqzZMBWmab8wXG7MyHKvmkNXV0MoH0Z860Zqb7Hgj1sREEODY3szSIfQ28a14xFBUTP5 kc8WQMvmyWUlMssa4+5Tu/HUfh7RigUHTChpBDFbm0iIGNAn00+rAbIpYdX77jjPmBYH fe+lckw9S+WN0XRStdlKIn3xPn4uL6gCWBilArn32rHB0GVAm/2n7/h/MsMh+Fbiihps 535GOFrYmRVH1qgr2jCPeCwi0PdEqRufQulv8tFuw//EJpQDskXESocFC15nRuUPYhQf +zew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CAa/+EzoUulBLTSh6AZhoZXdy3/J+ZdK8xOisZ5wF38=; b=iP3cjp2RbF1BS5VGjJlFkqhrZonyh2mN+B9HoCIsH/tbg3E8sAsP+LxkUyqwCQoOso uV4iDrk8WdnoajXxOM4OWm/Ixm4H5vDKgrGt42yd7CkdGSqCBKuEWUforejPmJaarFkG Se956Rsitm9/uoeUx7PEptFncRbhBXbH3NpO4oK7gYREXautuidBzfzyt7LnoN9dI2J/ gbxkyZMLmpuHEQ7/JOdqzo5oUMIjSJkBpJg7wfnfhvj9W9VVJmO+p15hM0gdV4NG/KeL r7VpKmFrdyqyqKqc+4sGzFSFszYHJqQwyrlSbRlBeYSVzl1o5x3hocVpLP1x6312/3r4 6WxA== X-Gm-Message-State: AOAM531jCHTSgulYN6925REg+RjvNMhoXuoye+mYqZA4vXY4McOfntPP PUTvUNz3Zn2R12hz8BPXJXgaI5adSJMZlQOw X-Google-Smtp-Source: ABdhPJyMcBMAfPlTres+M9qVjVp0CUy01HtaHMOLH4qCs2kjwQxEMDHlj2wYvyKtb2OFQMDOkAr4SA== X-Received: by 2002:a5d:4531:: with SMTP id j17mr7770239wra.303.1622661113899; Wed, 02 Jun 2021 12:11:53 -0700 (PDT) From: Jose Martins To: qemu-devel@nongnu.org Subject: [PATCH 1/2] target/riscv: fix VS interrupts forwarding to HS Date: Wed, 2 Jun 2021 20:11:24 +0100 Message-Id: <20210602191125.525742-2-josemartins90@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602191125.525742-1-josemartins90@gmail.com> References: <20210602191125.525742-1-josemartins90@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=josemartins90@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V TCG CPUs" , Sagar Karandikar , Jose Martins , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when not delegated in hideleg (which was not being taken into account). This was mainly because hs level sie was not always considered enabled when it should. The spec states that "Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode." and also "For purposes of interrupt global enables, HS-mode is considered more privileged than VS-mode, and VS-mode is considered more privileged than VU-mode". Also, vs-level interrupts were not being taken into account unless V=3D1, but should be unless delegated. Finally, there is no need for a special case for to handle vs interrupts as the current privilege level, the state of the global ie and of the delegation registers should be enough to route all interrupts to the appropriate privilege level in riscv_cpu_do_interrupt. Signed-off-by: Jose Martins Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 21c54ef561..592d4642be 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -38,36 +38,24 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { - target_ulong irqs; + target_ulong virt_enabled =3D riscv_cpu_virt_enabled(env); =20 target_ulong mstatus_mie =3D get_field(env->mstatus, MSTATUS_MIE); target_ulong mstatus_sie =3D get_field(env->mstatus, MSTATUS_SIE); - target_ulong hs_mstatus_sie =3D get_field(env->mstatus_hs, MSTATUS_SIE= ); =20 - target_ulong pending =3D env->mip & env->mie & - ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); - target_ulong vspending =3D (env->mip & env->mie & - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); + target_ulong pending =3D env->mip & env->mie; =20 target_ulong mie =3D env->priv < PRV_M || (env->priv =3D=3D PRV_M && mstatus_mie); target_ulong sie =3D env->priv < PRV_S || (env->priv =3D=3D PRV_S && mstatus_sie); - target_ulong hs_sie =3D env->priv < PRV_S || - (env->priv =3D=3D PRV_S && hs_mstatus_sie); + target_ulong hsie =3D virt_enabled || sie; + target_ulong vsie =3D virt_enabled && sie; =20 - if (riscv_cpu_virt_enabled(env)) { - target_ulong pending_hs_irq =3D pending & -hs_sie; - - if (pending_hs_irq) { - riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); - return ctz64(pending_hs_irq); - } - - pending =3D vspending; - } - - irqs =3D (pending & ~env->mideleg & -mie) | (pending & env->mideleg &= -sie); + target_ulong irqs =3D + (pending & ~env->mideleg & -mie) | + (pending & env->mideleg & ~env->hideleg & -hsie) | + (pending & env->mideleg & env->hideleg & -vsie); =20 if (irqs) { return ctz64(irqs); /* since non-zero */ --=20 2.30.2 From nobody Sun May 5 08:59:41 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622661256; cv=none; d=zohomail.com; s=zohoarc; b=m2KFXR4V/VziajXKqMuiZdJdlolD0qrmQw6CaCf1+3cRObQai59UcNr9CWK1b52qw5Ii5uyfhLLestXB4utXHHuDFtOzYzKs9YpcCxRKWNaw/QFXYbVsZgWN2lfIpqtPRy+e2hyilH96raN5G7sh6RE+1yLK2V2Mu3UQBvrxOCE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622661256; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XZz91rM5BGIW4nSoz6um0ZzXqGuRd9b6erkMDM2N8cs=; b=NFLaMtodCjUAeWKboGqwX1V5bMK2eekSacZP3BNfzL3B8hR/HBcpgsbav/n2EBMa9K/zVQNwnoSo4R1vJf2O9o9JDsKjYAECuP2wK7I1XYTePU8UcSYgXwJ7NpXyFnZeDVBgbJMnGYnZc+/nSl9lU2LobcsndJAxHT6ynIUmDLQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162266125673289.8809375004937; Wed, 2 Jun 2021 12:14:16 -0700 (PDT) Received: from localhost ([::1]:43100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loWJj-0003zz-MC for importer2@patchew.org; Wed, 02 Jun 2021 15:14:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loWHa-0000ds-Hl; Wed, 02 Jun 2021 15:12:03 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:38829) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1loWHW-0001vf-K0; Wed, 02 Jun 2021 15:12:02 -0400 Received: by mail-wm1-x32d.google.com with SMTP id t4-20020a1c77040000b029019d22d84ebdso4409940wmi.3; Wed, 02 Jun 2021 12:11:57 -0700 (PDT) Received: from asus.. ([83.144.170.28]) by smtp.gmail.com with ESMTPSA id n2sm635304wmb.32.2021.06.02.12.11.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 12:11:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XZz91rM5BGIW4nSoz6um0ZzXqGuRd9b6erkMDM2N8cs=; b=UnfrK+4GBbt+Hzu7he1J9AIQrxEbHwiWwptcoBTwqPE2P1zBK+5mqBoELBSsZvK7Lv aVyMNK7/yGN3qqtHDk/L66RzdY0rtB59aY77Pvg98U9zP0MmO3WqfvVwPykbF+q+6zDz mBV7xwaVbslYCk9OnXKpvZWi0IHUcfBbtjWJYN8sKY4IkueRcB9fIw0F/hQIbgUKrpNK vtL6ao8cUV8FZqpZ2jSKBuEmyBCQ862mKtiV3ZUJnzuWjs8DmThCK72vFbarqaYDla4T D4iCbfKnDfc12QcPI9gueTZXsbinHZrPRRye+7aX9rXpXdRA1evK8peAl89r23qOihdN l1NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XZz91rM5BGIW4nSoz6um0ZzXqGuRd9b6erkMDM2N8cs=; b=XW4VqWq5lU90ZqGszfFEVsACRyqvsN3s5aQfSUus0YRNyN5VrcANA8TmhqHOJj28rK ygQK4U89WQtsfzdUwcGcyhR8Bz+nWOB+JAMCKlghgLd95PKAmpAXOxTWQkWi+rzCckpb yyCMS/oM1u4hqcSBy63v3tfb+COCOW7JTouSo22AMzDesdND9OK1hYC+YnLRij/vTkQB 4hYIzxyWm2/0393ofq7icwWqvmqD0wTxKz7hEx4TIDPSBFwyvcYIxzBH7rGBcoBIpx6i S7mMKNmOoa7JHX+XYPrIh5wOZnhK9JkGCLPNrPpiBpSfksjsY9PlYmbtOUmeABGx0OPN cVug== X-Gm-Message-State: AOAM530F5+oH1Ocb3/5Sobs+woTiyKoa27Hw4vI2bdMx/AI3LlRsLmnV YHpXfms/xduyQqCRtqyT2O1mKKQRPdQrxiRO X-Google-Smtp-Source: ABdhPJwv7/1LjF1fundtjB9gkDh72nQyMVbP8xkBH/lBa5hAk9t7xQBXXRw6RGwCi6BXsTHt8WgmaA== X-Received: by 2002:a1c:6657:: with SMTP id a84mr23393640wmc.15.1622661116568; Wed, 02 Jun 2021 12:11:56 -0700 (PDT) From: Jose Martins To: qemu-devel@nongnu.org Subject: [PATCH 2/2] target/riscv: remove force HS exception Date: Wed, 2 Jun 2021 20:11:25 +0100 Message-Id: <20210602191125.525742-3-josemartins90@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602191125.525742-1-josemartins90@gmail.com> References: <20210602191125.525742-1-josemartins90@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=josemartins90@gmail.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V TCG CPUs" , Sagar Karandikar , Jose Martins , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" There is no need to "force an hs exception" as the current privilege level, the state of the global ie and of the delegation registers should be enough to route the interrupt to the appropriate privilege level in riscv_cpu_do_interrupt. The is true for both asynchronous and synchronous exceptions, specifically, guest page faults which must be hardwired to zero hedeleg. As such the hs_force_except mechanism can be removed. Signed-off-by: Jose Martins Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 -- target/riscv/cpu_bits.h | 6 ------ target/riscv/cpu_helper.c | 26 +------------------------- 3 files changed, 1 insertion(+), 33 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba..a30a64241a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -337,8 +337,6 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interru= pt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); -void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index caf4599207..7322f54157 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -462,12 +462,6 @@ =20 /* Virtulisation Register Fields */ #define VIRT_ONOFF 1 -/* This is used to save state for when we take an exception. If this is set - * that means that we want to force a HS level exception (no matter what t= he - * delegation is set to). This will occur for things such as a second level - * page table fault. - */ -#define FORCE_HS_EXCEP 2 =20 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 592d4642be..babe3d844b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -178,24 +178,6 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bo= ol enable) env->virt =3D set_field(env->virt, VIRT_ONOFF, enable); } =20 -bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) -{ - if (!riscv_has_ext(env, RVH)) { - return false; - } - - return get_field(env->virt, FORCE_HS_EXCEP); -} - -void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) -{ - if (!riscv_has_ext(env, RVH)) { - return; - } - - env->virt =3D set_field(env->virt, FORCE_HS_EXCEP, enable); -} - bool riscv_cpu_two_stage_lookup(int mmu_idx) { return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; @@ -884,7 +866,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - bool force_hs_execp =3D riscv_cpu_force_hs_excep_enabled(env); uint64_t s; =20 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide @@ -913,8 +894,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_INST_GUEST_PAGE_FAULT: case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: - force_hs_execp =3D true; - /* fallthrough */ case RISCV_EXCP_INST_ADDR_MIS: case RISCV_EXCP_INST_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: @@ -973,8 +952,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 0); } =20 - if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && - !force_hs_execp) { + if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt @@ -996,7 +974,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) htval =3D env->guest_phys_fault_addr; =20 riscv_cpu_set_virt_enabled(env, 0); - riscv_cpu_set_force_hs_excep(env, 0); } else { /* Trap into HS mode */ env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, fals= e); @@ -1032,7 +1009,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 /* Trapping to M mode, virt is disabled */ riscv_cpu_set_virt_enabled(env, 0); - riscv_cpu_set_force_hs_excep(env, 0); } =20 s =3D env->mstatus; --=20 2.30.2