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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uDfokmVezSAHwLgnVmTXn57igOgF6mkmm4tytSe1MNo=; b=IT84UwMpdZp41moSF472dvDgsCPwwVwZUBDq5BiaDJfO8EyFOdF/4u3xlvTbRZVwsi MLhm3r5JcbhqKLLnohHoNPxEy6rvCpyQ+wQ4rY5gZVFtPFD6F1WiTyqDdK9GDONXC+K1 AueY8brRX76LAZwszanhYiyKF0jMlxtYSm8qouOZcwJaE8qX0DwVfxXfxCG/PvH6o4Rp 2xwLo619OSFs0N0uZPa0XBC1CS9M/4VdqDMXJO3mf7JZZuRn5ROIq1jJVcRBBt0j/Fx2 IEJ7Y+0cumARzIWES++tgWQodc6LTjOJg1PD/V+ZkrU0fXpIfRln+Y44d5Rhz0vCglNX ycTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uDfokmVezSAHwLgnVmTXn57igOgF6mkmm4tytSe1MNo=; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add the isar feature check functions we will need for v8.1M MVE: * a check for MVE present: this corresponds to the pseudocode's CheckDecodeFaults(ExtType_Mve) * a check for the optional floating-point part of MVE: this corresponds to CheckDecodeFaults(ExtType_MveFp) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210520152840.24453-2-peter.maydell@linaro.org --- target/arm/cpu.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 04f8be35bf0..f1bd7d787cd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3817,6 +3817,28 @@ static inline bool isar_feature_aa32_fp16_arith(cons= t ARMISARegisters *id) } } =20 +static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) +{ + /* + * Return true if MVE is supported (either integer or floating point). + * We must check for M-profile as the MVFR1 field means something + * else for A-profile. + */ + return isar_feature_aa32_mprofile(id) && + FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; +} + +static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) +{ + /* + * Return true if MVE is supported (either integer or floating point). + * We must check for M-profile as the MVFR1 field means something + * else for A-profile. + */ + return isar_feature_aa32_mprofile(id) && + FIELD_EX32(id->mvfr1, MVFR1, MVE) >=3D 2; +} + static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) { /* --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736137; cv=none; d=zohomail.com; s=zohoarc; b=V+VyU2XRK1N1y3ZtKso3KHSEH8RxAWarOZsq0hm4z6SSEe2E+/yZr0TE9jecdmPbezhRyHJIzoo7AuVvAJ1c/2OxB26um86IxQT/R85tNI95AFdbkGGiN2/t9U+hHZAzdKqhPIjctYlB84/DI+X6EMPRKC6fNaC6HWmouTctWvw= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=a7vuyrkb2vzc3hIuNJsHgyPQ2xdcERO/+RVIeaq9+Do=; b=gCG2xMCY5GC9fV3L9LhnCtpOAa1QE5rxuAOfWpqQJBF2MfJ1nAA7Bue4IzXNWsFcg8 IY9Wiy2YEnCMzQHQQbd8FIU9vgPG/ybWu7aEkM8LNeUN2FClsa9WsdWk1k007yWADlq3 whKh3aN5pE7tBqUCLpa2UC/1EdtbPcT0+GH9uHwWzxod2co5dJG31TBRm3sLyyOybqNK XUM8B1KOKDD+775fWeHine+GFofycRWZ1iDvAzzzsu2Fw8dUQVDQdxQLM92nKqTtG/j4 gDr93zW0gS5HtP2/e3WGQ3QV6O+bb06U+SyPmgqnQOAiD50t2XQRm/G9L8/HF+pXH4q/ OOcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a7vuyrkb2vzc3hIuNJsHgyPQ2xdcERO/+RVIeaq9+Do=; b=cTrl6D8ZmiGHK76oH8rNDxSdqgVAmD32Jlo5mx634HqTXAjk76XRzQm3VPdL8JZRwb JOCak2+c2Ctf64QcHNiY5XZNAtl/CRWoAvAyklt22kcs/Htm/FKOJJE8vODcz9XU+2yn +N8QePPH9tXST++j+73xfwiwMlk/Mwgiao+lbnLR8OyI31atGts7zguPJyiaswwKlTHF K2u6BFLvd6rBAuOCWRDmgAG7gezeJixKnNWnkNHezkx5VbipvNfFrhhxo+D7OhhqLpxs LJnGt2LNjnosk1bmnKT6mC2wQFnZr6H8K7ZX1xaA4rL53DxbVO+8WpjLyOoSfkVdChzg TzaA== X-Gm-Message-State: AOAM533bE0C68f+LvTvUspoCGd0QMEx8wO4oM3xyN0ohHALPhzwLKtL4 hSv1hXVXSLWdfjMq7VNQFnT44J+2GRVepfnI X-Google-Smtp-Source: ABdhPJw7fH+6Avxj5z7cGnMXkEFDE6nCDlDD4NUr36KkF63DH6tYZVWCRCwCNd79N6JBqIwhH4Q3tQ== X-Received: by 2002:a5d:46cb:: with SMTP id g11mr644377wrs.418.1622735948484; Thu, 03 Jun 2021 08:59:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/45] target/arm: Update feature checks for insns which are "MVE or FP" Date: Thu, 3 Jun 2021 16:58:21 +0100 Message-Id: <20210603155904.26021-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Some v8M instructions are present if either the floating point extension or MVE is implemented. Update our implementation of them to check for MVE as well as for FP. This is all the insns which use CheckDecodeFaults(ExtType_MveOrFp) or CheckDecodeFaults(ExtType_MveOrDpFp) in their pseudocode, which are essentially the loads and stores, moves and sysreg accesses, except for VMOV_reg_sp and VMOV_reg_dp, which we handle in subsequent patches because they need a refactor to provide a place to put the new MVE check. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210520152840.24453-3-peter.maydell@linaro.org --- target/arm/translate-vfp.c | 48 +++++++++++++++++++++++--------------- 1 file changed, 29 insertions(+), 19 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 3da84f30a01..2202f8985d2 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -543,11 +543,16 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMO= V_to_gp *a) /* VMOV scalar to general purpose register */ TCGv_i32 tmp; =20 - /* SIZE =3D=3D MO_32 is a VFP instruction; otherwise NEON. */ - if (a->size =3D=3D MO_32 - ? !dc_isar_feature(aa32_fpsp_v2, s) - : !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; + /* + * SIZE =3D=3D MO_32 is a VFP instruction; otherwise NEON. MVE has + * all sizes, whether the CPU has fp or not. + */ + if (!dc_isar_feature(aa32_mve, s)) { + if (a->size =3D=3D MO_32 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } } =20 /* UNDEF accesses to D16-D31 if they don't exist */ @@ -571,11 +576,16 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_V= MOV_from_gp *a) /* VMOV general purpose register to scalar */ TCGv_i32 tmp; =20 - /* SIZE =3D=3D MO_32 is a VFP instruction; otherwise NEON. */ - if (a->size =3D=3D MO_32 - ? !dc_isar_feature(aa32_fpsp_v2, s) - : !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; + /* + * SIZE =3D=3D MO_32 is a VFP instruction; otherwise NEON. MVE has + * all sizes, whether the CPU has fp or not. + */ + if (!dc_isar_feature(aa32_mve, s)) { + if (a->size =3D=3D MO_32 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } } =20 /* UNDEF accesses to D16-D31 if they don't exist */ @@ -671,7 +681,7 @@ typedef enum FPSysRegCheckResult { =20 static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno) { - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return FPSysRegCheckFailed; } =20 @@ -1254,7 +1264,7 @@ static bool trans_VMOV_single(DisasContext *s, arg_VM= OV_single *a) { TCGv_i32 tmp; =20 - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1287,7 +1297,7 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMO= V_64_sp *a) { TCGv_i32 tmp; =20 - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1329,7 +1339,7 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMO= V_64_dp *a) * floating point register. Note that this does not require support * for double precision arithmetic. */ - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1368,7 +1378,7 @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_V= LDR_VSTR_sp *a) uint32_t offset; TCGv_i32 addr, tmp; =20 - if (!dc_isar_feature(aa32_fp16_arith, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1403,7 +1413,7 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_V= LDR_VSTR_sp *a) uint32_t offset; TCGv_i32 addr, tmp; =20 - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1439,7 +1449,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_dp *a) TCGv_i64 tmp; =20 /* Note that this does not require support for double arithmetic. */ - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1479,7 +1489,7 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_V= LDM_VSTM_sp *a) TCGv_i32 addr, tmp; int i, n; =20 - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 @@ -1557,7 +1567,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) int i, n; =20 /* Note that this does not require support for double arithmetic. */ - if (!dc_isar_feature(aa32_fpsp_v2, s)) { + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)= ) { return false; } =20 --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736430; cv=none; d=zohomail.com; s=zohoarc; b=mQcsHTXtaWrEEFf3xs4r2jBLyKRumQbo/eH90EA2Rm7wYxwjY81JflE7Yp/iE+0BitIFqotdfI7VmwjJ2RDDIOEHZEsENRFL+fvXM0ATCBfpKipiuAz8jqdXUX0/sZM0QxHTMR9ojq1GLNxdr6M/drbbUqaoq0tQiHlsly/dboU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736430; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZhizTBvitVYMmDuUL4Vbtr5J21f+rhN78RKoxwtR5CE=; b=HlE0NZ3roIPFsTyCRtBXIRY6rP+FniAPDHgiyuebescBIIaS0N1h4n52uAJiX2ByJzWvOfnGKVZxtsc9rX99BCrpVF+7vOANc5Q+FcnIhSLQ2SaLYPNT5YRt7FgnY6XMsZHDCUcyix4FmIaPm6FeWh0Rfqkt+gp+/ilVttbwTpw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622736430790952.2141843197247; Thu, 3 Jun 2021 09:07:10 -0700 (PDT) Received: from localhost ([::1]:43696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lopsD-0006hF-P6 for importer2@patchew.org; Thu, 03 Jun 2021 12:07:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35322) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkX-0007tu-Ve for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:14 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:44918) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkU-0006ln-NR for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:13 -0400 Received: by mail-wr1-x431.google.com with SMTP id f2so6353828wri.11 for ; Thu, 03 Jun 2021 08:59:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZhizTBvitVYMmDuUL4Vbtr5J21f+rhN78RKoxwtR5CE=; b=jYcAod680F8Ca/fDuIdZBMQdwBextQAxef96LgSKVNn4d7wX+rWumlr2SaX0EZJqyR s9/fZZYJRDn1V4aMeR2tDazDcY66kUPRSU/DsnSjNQNvn6CvgURXwJxGny0bXUkv1aNn 4ka1iWsj6mbC+sP/JBVnqnXZxyoKSAUpxq0NfbL5ET3zMrZKkD6H5Br3KTYj8O4+JHau Z+Ex7VW412FYhjD5zSnrVYlDxA/8jssQgD4lX2UwPpqx2DYtTL/1bAeFoe8yJ6afgCme xQ5NeWOeu6W5xXXlF+VlYv1NvNcG9amPlyHkPMm9GrWl6tE8mfGibTUJD6hao5znOC6g OiOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZhizTBvitVYMmDuUL4Vbtr5J21f+rhN78RKoxwtR5CE=; b=CIK9VIlngSbK2u3mA4/OqE4L2X0rFIrvkCKA877CQdhl0XuSEiiCcAdiZsfVe7IJfC S5ubYOR5BaYs8XbCoFaiPM2jW4ax6uWe428+O6CROS2qcf4zRJoJ2c/KQb2Lxl50iglY 5lEkx01zGW30xjQx5XWBpZp4dSbKbvMWX0NosgT4Y3dYU9PH+toAUxcffr/Eru9spzsj 1cffrvINmMQ+lDzFfPaHO4ye/peHHEfae7lqAG8Tn+KaBLKfaiy5+8wyIJ/2ArfDOf7X YrOrYLzqG0P4QbvHmIFEDOZfS3ZSoJu6N7QNF1LFZkIz71EoY7K/RHGZ0WF8HxXMoWVu 2Kag== X-Gm-Message-State: AOAM531uh4l/5UyjBYPjhKyPi0/6l01IYPKhH43s+GFoy+j6/+q4GBPL 3N2MHLdDRFHqFnoGdI6sVNqrATltqU0wfhnS X-Google-Smtp-Source: ABdhPJz8N+0Gw/GOb+k/DbDBabTdNU4cLJ+T1UB05ggT0KquZSqPTgD6wq1BClvZRAqiKWL8dL//pw== X-Received: by 2002:a5d:4689:: with SMTP id u9mr638061wrq.31.1622735949224; Thu, 03 Jun 2021 08:59:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/45] target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp Date: Thu, 3 Jun 2021 16:58:22 +0100 Message-Id: <20210603155904.26021-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The do_vfp_2op_sp() and do_vfp_2op_dp() functions currently check whether floating point is supported via the aa32_fpdp_v2 and aa32_fpsp_v2 isar checks. For v8.1M MVE support, the VMOV_reg trans functions (but not any of the others) need to update this to also allow the insn if MVE is implemented. Move the check out of the do_ function and into its callsites (which are all implemented via the DO_VFP_2OP macro), so we have a place to change the check for the VMOV insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210520152840.24453-4-peter.maydell@linaro.org --- target/arm/translate-vfp.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 2202f8985d2..89246a284aa 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -1925,9 +1925,7 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i32 f0, fd; =20 - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } + /* Note that the caller must check the aa32_fpsp_v2 feature. */ =20 if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { @@ -2002,6 +2000,8 @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) */ TCGv_i32 f0; =20 + /* Note that the caller must check the aa32_fp16_arith feature */ + if (!dc_isar_feature(aa32_fp16_arith, s)) { return false; } @@ -2030,9 +2030,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i64 f0, fd; =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } + /* Note that the caller must check the aa32_fpdp_v2 feature. */ =20 /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { @@ -2810,23 +2808,26 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_= VMOV_imm_dp *a) return true; } =20 -#define DO_VFP_2OP(INSN, PREC, FN) \ +#define DO_VFP_2OP(INSN, PREC, FN, CHECK) \ static bool trans_##INSN##_##PREC(DisasContext *s, \ arg_##INSN##_##PREC *a) \ { \ + if (!dc_isar_feature(CHECK, s)) { \ + return false; \ + } \ return do_vfp_2op_##PREC(s, FN, a->vd, a->vm); \ } =20 -DO_VFP_2OP(VMOV_reg, sp, tcg_gen_mov_i32) -DO_VFP_2OP(VMOV_reg, dp, tcg_gen_mov_i64) +DO_VFP_2OP(VMOV_reg, sp, tcg_gen_mov_i32, aa32_fpsp_v2) +DO_VFP_2OP(VMOV_reg, dp, tcg_gen_mov_i64, aa32_fpdp_v2) =20 -DO_VFP_2OP(VABS, hp, gen_helper_vfp_absh) -DO_VFP_2OP(VABS, sp, gen_helper_vfp_abss) -DO_VFP_2OP(VABS, dp, gen_helper_vfp_absd) +DO_VFP_2OP(VABS, hp, gen_helper_vfp_absh, aa32_fp16_arith) +DO_VFP_2OP(VABS, sp, gen_helper_vfp_abss, aa32_fpsp_v2) +DO_VFP_2OP(VABS, dp, gen_helper_vfp_absd, aa32_fpdp_v2) =20 -DO_VFP_2OP(VNEG, hp, gen_helper_vfp_negh) -DO_VFP_2OP(VNEG, sp, gen_helper_vfp_negs) -DO_VFP_2OP(VNEG, dp, gen_helper_vfp_negd) +DO_VFP_2OP(VNEG, hp, gen_helper_vfp_negh, aa32_fp16_arith) +DO_VFP_2OP(VNEG, sp, gen_helper_vfp_negs, aa32_fpsp_v2) +DO_VFP_2OP(VNEG, dp, gen_helper_vfp_negd, aa32_fpdp_v2) =20 static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm) { @@ -2843,9 +2844,9 @@ static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm) gen_helper_vfp_sqrtd(vd, vm, cpu_env); } =20 -DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp) -DO_VFP_2OP(VSQRT, sp, gen_VSQRT_sp) -DO_VFP_2OP(VSQRT, dp, gen_VSQRT_dp) +DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp, aa32_fp16_arith) +DO_VFP_2OP(VSQRT, sp, gen_VSQRT_sp, aa32_fpsp_v2) +DO_VFP_2OP(VSQRT, dp, gen_VSQRT_dp, aa32_fpdp_v2) =20 static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a) { --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736276; cv=none; d=zohomail.com; s=zohoarc; b=gVn3d8J2nzR9PsJ4oM22Cx24bUDnNrHwdMqp+cp/eKJphmMHOfCFxfaICq5TUih+/obiZ3YkKpldW+PpwTs2605nY0xY4ZmABgZgSurbpRou8EE4fTMsopiQmwDygzcV+uQCn3XSxG0NjSaybjWHBJ7VyXJ6CWR/Xmw5HVN3+6Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wXISN6ZA+fySx1Wmxbs/iMnId7qOVgagiX+zub5wUmg=; b=zk51MTlVlN51i/S29XnhvUR3UaV/nturN8OZmIJUsffHc2eQS6HUc09Jn4/r35YVse q/NiURmi6ZaXFLyFeK9M0JGSl5z3dQKNk+hKzCmRDs/cawTNChbwjRo3cNtxayMQiB9G FmGUuckwYnRHdKRdT+NG6O2VKPQUzgIyjzEESadiRjpCHsBervs5dphT0U4xtfDwNbpR WWAF62nX7Mb4Ig8rVBDgEO9x1ZfQWAaZI79AkXPBQoPfH4KnbcXbMz375IE/lpxxEsdP AyczDa/LxA+vCIpTGTvgqbDIQ3EpOB/Zf2ProUGbOb6advMBmZtFmiTJBlxgh2qOiBPB EKUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wXISN6ZA+fySx1Wmxbs/iMnId7qOVgagiX+zub5wUmg=; b=n34vpYXeSrEHfeQ84wzoWRWiLohraXPOZdP+FL4hNVjjFFS3qtYK26ZsvuF9d1l4je HDEj0WaHSb5BayJP/CcIfyCsUiBbDvlgrU9QqR1y/Kq0tZfGn+Gas3lXq9GhdDRmXkIa qvqdeU9Xf/EbB3l8ptKJKcV/RKS3eSEtYulA1mP6nOmKakVMkiVBXCjGYxwXZkXD3p+6 v1OyjMafcmljRzpWbzswJzifbL3sxQrRLLg5XCeWMEysF8cdGtOxazyyNyOBbtnYPK43 0pcPoKDndEBUCGyOboBsYWpaGUgHJ+U6aFesrGT4JiOkWJQpgdVq0ptkc6KuARQL0kWr 3Oog== X-Gm-Message-State: AOAM5333feK8tX7TFA5tusZM5BXDz5t3heMXejqDVVtLrfdDBJOzlIL9 LFAFFHshY49QtSFQp8v9RkrY0EE0WrwYGAJX X-Google-Smtp-Source: ABdhPJy3d8T+Q+j7lerHiObg1LrTOaMTrypDWa2NtLLPvjFaZVSgSrxgNqv5J1Aly0C7bfzy7Kn2qA== X-Received: by 2002:adf:fbce:: with SMTP id d14mr626217wrs.201.1622735950031; Thu, 03 Jun 2021 08:59:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/45] target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp Date: Thu, 3 Jun 2021 16:58:23 +0100 Message-Id: <20210603155904.26021-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Split out the handling of VMOV_reg_sp and VMOV_reg_dp so that we can permit the insns if either FP or MVE are present. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210520152840.24453-5-peter.maydell@linaro.org --- target/arm/translate-vfp.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 89246a284aa..ac5832a4ed5 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -2818,8 +2818,19 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_V= MOV_imm_dp *a) return do_vfp_2op_##PREC(s, FN, a->vd, a->vm); \ } =20 -DO_VFP_2OP(VMOV_reg, sp, tcg_gen_mov_i32, aa32_fpsp_v2) -DO_VFP_2OP(VMOV_reg, dp, tcg_gen_mov_i64, aa32_fpdp_v2) +#define DO_VFP_VMOV(INSN, PREC, FN) \ + static bool trans_##INSN##_##PREC(DisasContext *s, \ + arg_##INSN##_##PREC *a) \ + { \ + if (!dc_isar_feature(aa32_fp##PREC##_v2, s) && \ + !dc_isar_feature(aa32_mve, s)) { \ + return false; \ + } \ + return do_vfp_2op_##PREC(s, FN, a->vd, a->vm); \ + } + +DO_VFP_VMOV(VMOV_reg, sp, tcg_gen_mov_i32) +DO_VFP_VMOV(VMOV_reg, dp, tcg_gen_mov_i64) =20 DO_VFP_2OP(VABS, hp, gen_helper_vfp_absh, aa32_fp16_arith) DO_VFP_2OP(VABS, sp, gen_helper_vfp_abss, aa32_fpsp_v2) --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736452; cv=none; d=zohomail.com; s=zohoarc; b=bRuw9pZ9xU1vBM8Y4Lorp+o1yXaHFoC+oBpLsfTmKBIEbL6E8KHa9oWaDTBnGsmPmj4RSSHef1kHdi1goxDmJPfYNjL/4owhab+B9LvQuY6H4w6lrzCv27QSUKviFZtGaL5BaDXkCCdxI5w6AYdH/dUcOJ/+jAGQ2gVyo7RcgZ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736452; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=grEElkudzhlG08Zt5qxe4SAKlLrlc5lljt/oYKSsh0g=; b=GJwAP8SuL0ZZqHsuK+aBJ7VTBsLpBZiNi/0hPOxTUwuTXtP4pzmcPoyBa/PMUjqb+OHy27C9r0hDTZe1NPfhFygd1arptHS42oYnXk+DrEo6QnIOnI9i6uWf/AhrSg0LqI64REtw0Onj8rCJc2D2psTlu+8+/XvJLeggHqgRhdM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622736452913131.87649799600854; Thu, 3 Jun 2021 09:07:32 -0700 (PDT) Received: from localhost ([::1]:44644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lopsZ-0007Na-Qk for importer2@patchew.org; Thu, 03 Jun 2021 12:07:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35372) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkZ-00081w-Sl for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:15 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:38609) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkW-0006mr-5u for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:15 -0400 Received: by mail-wr1-x431.google.com with SMTP id j14so6385254wrq.5 for ; Thu, 03 Jun 2021 08:59:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=grEElkudzhlG08Zt5qxe4SAKlLrlc5lljt/oYKSsh0g=; b=XEBsFM0J6bS5OWuXz2lAtzB7Id7ymYkoOaOivbvt59ETq+g++xIkbrQNsv7yoNMbHm v5kYM1tn6ErvIhMUCyUGDZIBy+Hu1ejU/gJ2HxuKCCSZkrk9TMj8tfJ1Brcf5whgRw+9 jvyRS4MLoLj59U+7ABSTqKB/64wmzbXI+D9+qrnffTyv9bf9au3wspMmjcbeuP6E9VKa u9Ggjr4op2OCvo9gPs41ghwzDEGHh7S37gdWObsnz90yW4DkDjjDAK9vbyfRe/01zics fX4miGUswFpwtjTf/o2ZN1zg/dtDnpvw/EAHXhLzrkzFHPmMsMuZ3B83SDzG3u8u0WEk Amkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=grEElkudzhlG08Zt5qxe4SAKlLrlc5lljt/oYKSsh0g=; b=gVg4bF5KSxoHetiB3v3waw2WfAr3mDSRTgl8GKDIYPEtAW7XTtQK8xNMVRKzX2ZkYn ZDegTR2zmmEOVXBx12ZjwZcXDcYgupqtWOHpqP8uDsjhgZI6XMg9d23b+nSDoYS/gxed m6vKB0RjydVfT2rTZdm5q+k2R/YOtTJCEWXxV/XXgG9pgzxmDCT50DaZzWOsGW81hBvt grgbPmjP8F3GVipvahjynmq1LXiNhIEXU8CcRrBELceaI3lw5C3Ey5p48h3TTizVv1U4 JCCOOYuAn5exgPhd2SoPblFBFlWdSnTvQ9J6mAtHlyAXwNf+lIBOSYZU+23wqspKoBGr jQdg== X-Gm-Message-State: AOAM5333Qu1LTayTG1ALtF0V1DktrIXhkqhnJ22yHusalqx7qx2HWYpS JwJJqPjwkSZjT7IoQQvdhC75r6dRMnGeRBiU X-Google-Smtp-Source: ABdhPJx4BGlmQi8Tvy0VZdiAtqY+JsEVuiufUNPPID20mLSYcpTge0VA7F1pO4D5BE21BzZje4SeKQ== X-Received: by 2002:adf:a1d2:: with SMTP id v18mr646572wrv.280.1622735950825; Thu, 03 Jun 2021 08:59:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/45] target/arm: Fix return values in fp_sysreg_checks() Date: Thu, 3 Jun 2021 16:58:24 +0100 Message-Id: <20210603155904.26021-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The fp_sysreg_checks() function is supposed to be returning an FPSysRegCheckResult, which is an enum with three possible values. However, three places in the function "return false" (a hangover from a previous iteration of the design where the function just returned a bool). Make these return FPSysRegCheckFailed instead (for no functional change, since both false and FPSysRegCheckFailed are zero). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210520152840.24453-6-peter.maydell@linaro.org --- target/arm/translate-vfp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index ac5832a4ed5..791c4f5f70b 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -691,16 +691,16 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasCont= ext *s, int regno) break; case ARM_VFP_FPSCR_NZCVQC: if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { - return false; + return FPSysRegCheckFailed; } break; case ARM_VFP_FPCXT_S: case ARM_VFP_FPCXT_NS: if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { - return false; + return FPSysRegCheckFailed; } if (!s->v8m_secure) { - return false; + return FPSysRegCheckFailed; } break; default: --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736257; cv=none; d=zohomail.com; s=zohoarc; b=KFSoXE4W9buQeC8O07yX/eaDtnJjLCs8BMGa6xpeBZxOcvX58ItclH8+twvByITNVWs4ZaB3l6bEfC5Dhe2Dqosap0SI5XLKuAl4VUNb9L7PGt0wEoT6uj76NDGOtLTAfWmBeuo5+YMfLbFHI5p3kH0bsc11h8dtT+15iIokC1U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736257; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oyyg5KAs5qRNGGXNnqnV1KKSwlhes9323oqJd8dOK2U=; b=bJ4YetXbKy9WX9yvjA88rMey09DWl3TB5yLgUSAY6o2JltivV1orEExDfRKImSjl4t6DFcXPrEum1yjqOxTncwsyRD6zCB1btdVQpRll7YOARQpLvtcjKgl0UWdBxcFJNzDTamFBGtiOXluw4KWwfDq+aY7s6XjetWs8IVghVV4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622736257007497.4957021603459; Thu, 3 Jun 2021 09:04:17 -0700 (PDT) Received: from localhost ([::1]:34324 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loppP-00009S-Pq for importer2@patchew.org; Thu, 03 Jun 2021 12:04:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35338) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkY-0007xU-PM for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:14 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:35647) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkW-0006nc-TS for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:14 -0400 Received: by mail-wr1-x433.google.com with SMTP id m18so6399977wrv.2 for ; Thu, 03 Jun 2021 08:59:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oyyg5KAs5qRNGGXNnqnV1KKSwlhes9323oqJd8dOK2U=; b=kB2rfpQZLYALZWd8frAoAp614QV3UpJED4+bCpq27aGqHjemiOTBt0H6k/hMI9CO5i vEpnu1e+LpqIXYhuwR8lM9M5I09IuJ6M8VQxiQJmD/8VWo5dl+lUEi98/z5TnP9XSLMa iwdM+4DkPZV9Uh2gct/0mYoQyuC4p1d2a5c4HEKWrtsVpwZymhr0GE19PbD1j4BSF9WS dqkoi0jHDe21NUTuLH+hH8OXG13k920psjbldA4UFHxPhbSm8f+4d892KXNreqsQ8Vlk yBSDuEsatSP78nsJJ+zGzmrbAWAnfH5DKIsxhcEShYvDz+Z3DOKjD4E+9j3izfwRwHaA bRxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oyyg5KAs5qRNGGXNnqnV1KKSwlhes9323oqJd8dOK2U=; b=jy+xi8hUVsz60D1vYUS1XH0ukFNswieRjUrUqKPMuTwN7xP6IsZ28hcUFYw2yUD8A9 3N3cuWFP5RsdbrQSwE0MZ3s177RyeubtVJCqD0jIkqOWO/2Euyk6UWeebZRr7Np/XXJq IuuDZ9AQ+GvkT+Rw3sIqCseWQiMzYTaAR7YD8n0S8brCXEvaH1xqK12jHC3v3H1rz+Xi HBw8MWde2+yTsnnVqxcSecsncgvi+QgRgrHMC53V7GiM7wFSw3ZUTIAX+dyW548ZwOW6 1V64Sm8KtFjbJ6x4US3n6XPldU6V3kRlNNQrJMKjpp7xl9/NvU2aZdKnjvK372hXcDpx bHGQ== X-Gm-Message-State: AOAM530GrflHKxfRstxbV7i507PTKnil6q1qa5YuoVq+oZyNwNGVek7l AlxkgY37iiCOrWIZOReyrGtgEt2KIIrt0Bjw X-Google-Smtp-Source: ABdhPJyJ3wtj7tQvGfR7hd/vcAuPlBslCIny4OijO/9WLcd43o1n8krkWvvHGptSo005nkoHepmdAA== X-Received: by 2002:a05:6000:1b8a:: with SMTP id r10mr670507wru.296.1622735951455; Thu, 03 Jun 2021 08:59:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/45] target/arm: Implement M-profile VPR register Date: Thu, 3 Jun 2021 16:58:25 +0100 Message-Id: <20210603155904.26021-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" If MVE is implemented for an M-profile CPU then it has a VPR register, which tracks predication information. Implement the read and write handling of this register, and the migration of its state. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210520152840.24453-7-peter.maydell@linaro.org --- target/arm/cpu.h | 6 ++++++ target/arm/machine.c | 19 +++++++++++++++++++ target/arm/translate-vfp.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f1bd7d787cd..df2f189c49b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -564,6 +564,7 @@ typedef struct CPUARMState { uint32_t cpacr[M_REG_NUM_BANKS]; uint32_t nsacr; int ltpsize; + uint32_t vpr; } v7m; =20 /* Information associated with an exception about to be taken: @@ -1761,6 +1762,11 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1) R_V7M_FPCCR_UFRDY_MASK | \ R_V7M_FPCCR_ASPEN_MASK) =20 +/* v7M VPR bits */ +FIELD(V7M_VPR, P0, 0, 16) +FIELD(V7M_VPR, MASK01, 16, 4) +FIELD(V7M_VPR, MASK23, 20, 4) + /* * System register ID fields. */ diff --git a/target/arm/machine.c b/target/arm/machine.c index 6ad1d306b12..62a71a3b640 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -318,6 +318,24 @@ static const VMStateDescription vmstate_m_fp =3D { } }; =20 +static bool mve_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + return cpu_isar_feature(aa32_mve, cpu); +} + +static const VMStateDescription vmstate_m_mve =3D { + .name =3D "cpu/m/mve", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D mve_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(env.v7m.vpr, ARMCPU), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_m =3D { .name =3D "cpu/m", .version_id =3D 4, @@ -344,6 +362,7 @@ static const VMStateDescription vmstate_m =3D { &vmstate_m_other_sp, &vmstate_m_v8m, &vmstate_m_fp, + &vmstate_m_mve, NULL } }; diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 791c4f5f70b..2316e105acc 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -703,6 +703,12 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasConte= xt *s, int regno) return FPSysRegCheckFailed; } break; + case ARM_VFP_VPR: + case ARM_VFP_P0: + if (!dc_isar_feature(aa32_mve, s)) { + return FPSysRegCheckFailed; + } + break; default: return FPSysRegCheckFailed; } @@ -817,6 +823,25 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int= regno, tcg_temp_free_i32(sfpa); break; } + case ARM_VFP_VPR: + /* Behaves as NOP if not privileged */ + if (IS_USER(s)) { + break; + } + tmp =3D loadfn(s, opaque); + store_cpu_field(tmp, v7m.vpr); + break; + case ARM_VFP_P0: + { + TCGv_i32 vpr; + tmp =3D loadfn(s, opaque); + vpr =3D load_cpu_field(v7m.vpr); + tcg_gen_deposit_i32(vpr, vpr, tmp, + R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); + store_cpu_field(vpr, v7m.vpr); + tcg_temp_free_i32(tmp); + break; + } default: g_assert_not_reached(); } @@ -935,6 +960,19 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int = regno, tcg_temp_free_i32(fpscr); break; } + case ARM_VFP_VPR: + /* Behaves as NOP if not privileged */ + if (IS_USER(s)) { + break; + } + tmp =3D load_cpu_field(v7m.vpr); + storefn(s, opaque, tmp); + break; + case ARM_VFP_P0: + tmp =3D load_cpu_field(v7m.vpr); + tcg_gen_extract_i32(tmp, tmp, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LEN= GTH); + storefn(s, opaque, tmp); + break; default: g_assert_not_reached(); } --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736296; cv=none; d=zohomail.com; s=zohoarc; b=O2PI4ng+QF/IjL5PrbROQXdr2mZSxLHubOAXQ7zWhtfsd8Qt/5x7UEWDF8WQfndywiDNgiuRW5mQWK3ggZ2t5zhVqsavRU21rLBxjvhl/yYSlpAk1L2HfwzCK6mbawybyqzVvnf+x9m0lGYutNY7Mnwi4XqmBTdIaDxKHaZFqWQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736296; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z+tbQwBoE6ol9K1/Y5CjCzDYZXTy7W8OMuxCoCUNVPk=; b=hGyqP0O4h1laPNseQXB38ESHAg4AQLSWZLMyB3HhdPRZ1GjGmfcN+P5a6hEKwcC7xc5+uO+ePmW8YppybUlKaLNXt3fXtBh203kUznLBVfmHCPNDEz46oglrozOd84raWxq5vgfyV2SU7Iu6/pOC14UNPMyAwjPavloVoE9ryPQ= ARC-Authentication-Results: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=z+tbQwBoE6ol9K1/Y5CjCzDYZXTy7W8OMuxCoCUNVPk=; b=CaAFHhIg4ie2MVQiFkQfAcrO2xBKxs8k3fgRO5QRLWYShsAtfL1nYoIkwjI6Stot/E cooZLX0pMVzVEGZgpYfr+Y+wzCzzbuxpQcVbQiT/6gXmjKKqEfCG7N15Lwj0lIhhyCLr 4deqz/ImRu8qJ3hgFqbghF/vcA9OPMnMFjv6Xn8qe7sgMl77N40AvjJ8cew8nVyj7kr3 9c0oZ5uK30ETbmAlg0nmxnhCrzeZsk3N35bl29ZYSzGwF50gjkrqypwGOabtbXbZx6gS HIx4VwQQdysm5EKMqBHiZ5vT4vL0E9C39CgHDTN1JB2EqtGdLgBdiqaB7yX2kMuI5Mam 3+HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z+tbQwBoE6ol9K1/Y5CjCzDYZXTy7W8OMuxCoCUNVPk=; b=sot0vDwnqSAiaKPp391AGSiMs05xVlb9ExoAuVPWicW19ge5pfS/ilX1jLTrAo/bnT AGpwuFQEZDF8j+hw7e11pYIhRmGjZJ7ErYC47woqPVYfSbJJ7U7dfSz6i+xniZvL7jav fCj4KxhesIlj4n9fGtI4+srJbYi6QkelPgiPsVbI2BDsx1GSxd61GAhLNYkvRqrw7Lvc W5VBerq9o/AriPwaD/xutzs+HwCgrX0n9MXT04hc2474c/F/Tt8WfjHfg3zPLs0hWaqB UuGZh6LRY5GGTfFPMENd0pK+2r2IwpIf1aZ3xhhg6i6Z/fiEFI/weB3TCIQ5CTP1m3EW H/zw== X-Gm-Message-State: AOAM533/pJ3UA464h920RnQVQoixYy4cSSzoM3UXmfrnBtITU0jQD8K8 IAOhGYX3etCP/aiVqJ5gBrOfCifZYmJi6jwY X-Google-Smtp-Source: ABdhPJwvbhymPi9NMcXlBuFVfeDpPIp0QjxsD4Emt4dqOSRDuEr99PpLyXuGlWe8Vo+NcXCTqTRWfQ== X-Received: by 2002:adf:f382:: with SMTP id m2mr653786wro.394.1622735952216; Thu, 03 Jun 2021 08:59:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/45] target/arm: Make FPSCR.LTPSIZE writable for MVE Date: Thu, 3 Jun 2021 16:58:26 +0100 Message-Id: <20210603155904.26021-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The M-profile FPSCR has an LTPSIZE field, but if MVE is not implemented it is read-only and always reads as 4; this is how QEMU currently handles it. Make the field writable when MVE is implemented. We can safely add the field to the MVE migration struct because currently no CPUs enable MVE and so the migration struct is never used. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210520152840.24453-8-peter.maydell@linaro.org --- target/arm/cpu.h | 3 ++- target/arm/machine.c | 1 + target/arm/vfp_helper.c | 9 ++++++--- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df2f189c49b..c389b1e9691 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -563,7 +563,7 @@ typedef struct CPUARMState { uint32_t fpdscr[M_REG_NUM_BANKS]; uint32_t cpacr[M_REG_NUM_BANKS]; uint32_t nsacr; - int ltpsize; + uint32_t ltpsize; uint32_t vpr; } v7m; =20 @@ -1562,6 +1562,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); =20 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) +#define FPCR_LTPSIZE_LENGTH 3 =20 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) diff --git a/target/arm/machine.c b/target/arm/machine.c index 62a71a3b640..81e30de8243 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -332,6 +332,7 @@ static const VMStateDescription vmstate_m_mve =3D { .needed =3D mve_needed, .fields =3D (VMStateField[]) { VMSTATE_UINT32(env.v7m.vpr, ARMCPU), + VMSTATE_UINT32(env.v7m.ltpsize, ARMCPU), VMSTATE_END_OF_LIST() }, }; diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 01b9d8557f7..e0886ab5a56 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -195,8 +195,10 @@ uint32_t vfp_get_fpscr(CPUARMState *env) =20 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { + ARMCPU *cpu =3D env_archcpu(env); + /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(any_fp16, env_archcpu(env))) { + if (!cpu_isar_feature(any_fp16, cpu)) { val &=3D ~FPCR_FZ16; } =20 @@ -210,11 +212,12 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t= val) * because in v7A no-short-vector-support cores still had to * allow Stride/Len to be written with the only effect that * some insns are required to UNDEF if the guest sets them. - * - * TODO: if M-profile MVE implemented, set LTPSIZE. */ env->vfp.vec_len =3D extract32(val, 16, 3); env->vfp.vec_stride =3D extract32(val, 20, 2); + } else if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.ltpsize =3D extract32(val, FPCR_LTPSIZE_SHIFT, + FPCR_LTPSIZE_LENGTH); } =20 if (arm_feature(env, ARM_FEATURE_NEON)) { --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736589; cv=none; d=zohomail.com; s=zohoarc; b=K9nn7nmDnTn/9CYo5BgmHkt78QC2wAsGflY8k71F8AOtK417f4yjF+WrakQBuscWZTbb2dSCE+m0r/nDu2YKr1WeY93YvERGTKVpKaA/o3SFIPc51QvAJHB8A9Je/t868f745IJpcxLG71WTlD0BNClafSrHddKbWhVVEsMGsMA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736589; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=erORTaUTqeqMhwB2aGcjyyec1Pu49DLWWyr6aCbHmnI=; b=hfzT7S/72sdbnI18KZnHEhXYIXOcFarYmM6tkED6HgNE+FWwZuAPWP9GqfIGgyTIXieg9NMvgxUZ06RhR1EfcQhQpS4R7f9vwWcGOyY7vWVnkzlcDii55fjPvomMh0gBwp+HSD8NKPikdVR3dwDA6kee+qc+nKYdQT3gIUbdv3s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622736589085283.77895862236517; Thu, 3 Jun 2021 09:09:49 -0700 (PDT) Received: from localhost ([::1]:52174 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lopum-0004Xr-2m for importer2@patchew.org; Thu, 03 Jun 2021 12:09:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkb-000880-E8 for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:17 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:56110) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkY-0006pE-Ae for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:17 -0400 Received: by mail-wm1-x332.google.com with SMTP id g204so3704798wmf.5 for ; Thu, 03 Jun 2021 08:59:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=erORTaUTqeqMhwB2aGcjyyec1Pu49DLWWyr6aCbHmnI=; b=Oh+orNjnPbWseWFlWLlFwTHPpoR7Mxs1Mg+VTm3cybpvUMWEyfoyRbw/25di0sPoba NMpfvT83AgzOK8uVi5mS+jLM2WZqhY8GE6GnAcs5JeZtH9R8ZQWzNOMGvrfN4qGRh2hC YRLKGz8zjFPGjKg921lFslxESzyMylfcwjAJcpUm7asl0CWXzH/pBrSoprAsc25dnUzY w9Jbn37lRd+d5T6xsDjKOx10H8dIS6nfD3FAbFZQRGuSavtvLKQUJe42oGbHH5xorM78 Y6yNWZSqoiLxH998MwUGSq7rDrzCuPGffr6wuj4rkXek05etczHsZ0v5fKc1TGs/oaPg zrAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=erORTaUTqeqMhwB2aGcjyyec1Pu49DLWWyr6aCbHmnI=; b=BR2kE/8gZXKtkYcOIYU5BzgpTuM930Xlh+8rn58yna9O7nlvcoNupM5iJBpSFj/Qfs /4+c+vl3YPwBqFb03UzTdc1Bm0BNDqRKdGBr3fac52Ly8X4WqlfHmaSrLcaD6zqxZQk+ kZeeGHRNXEikDjeSjbO0M2JuCHtmMDALNq6B98wb8nnUjujfwUOmFdVitW2EsiP4wzMI 4qABZSaPQoT3AnvrwBe1WviVhY1DFJkSyDclLlsITvR518CSy8X+yN4Pwedg9yqnzlcd xapL2oLy0jjnTuxYojwGzK0xC0jEZA2Lx5VPT1qAdXwWGRFFRbI/bIcYbiEHLJrwKNgq af5A== X-Gm-Message-State: AOAM531w0m9pbNkhS+5OFP3BJaK3xofyi62WnC/FQVdC7cVM5rks74kr GentAru045DvEOMaP1qG7A9asANJWjCQxbDW X-Google-Smtp-Source: ABdhPJwbUQKT1ilExgeonIFYhpuNkGLBY5ecUvehBRD6TAZUDzuyKXwSBw5oRFybFi7B1Da4MpLkFg== X-Received: by 2002:a7b:c4d0:: with SMTP id g16mr20376402wmk.181.1622735952816; Thu, 03 Jun 2021 08:59:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/45] target/arm: Allow board models to specify initial NS VTOR Date: Thu, 3 Jun 2021 16:58:27 +0100 Message-Id: <20210603155904.26021-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Currently we allow board models to specify the initial value of the Secure VTOR register, using an init-svtor property on the TYPE_ARMV7M object which is plumbed through to the CPU. Allow board models to also specify the initial value of the Non-secure VTOR via a similar init-nsvtor property. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210520152840.24453-10-peter.maydell@linaro.org --- include/hw/arm/armv7m.h | 2 ++ target/arm/cpu.h | 2 ++ hw/arm/armv7m.c | 7 +++++++ target/arm/cpu.c | 10 ++++++++++ 4 files changed, 21 insertions(+) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 189b23a8ceb..bc6733c5184 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -46,6 +46,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) * devices will be automatically layered on top of this view.) * + Property "idau": IDAU interface (forwarded to CPU object) * + Property "init-svtor": secure VTOR reset value (forwarded to CPU obje= ct) + * + Property "init-nsvtor": non-secure VTOR reset value (forwarded to CPU= object) * + Property "vfp": enable VFP (forwarded to CPU object) * + Property "dsp": enable DSP (forwarded to CPU object) * + Property "enable-bitband": expose bitbanded IO @@ -69,6 +70,7 @@ struct ARMv7MState { MemoryRegion *board_memory; Object *idau; uint32_t init_svtor; + uint32_t init_nsvtor; bool enable_bitband; bool start_powered_off; bool vfp; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c389b1e9691..5f234834c0d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -869,6 +869,8 @@ struct ARMCPU { =20 /* For v8M, initial value of the Secure VTOR */ uint32_t init_svtor; + /* For v8M, initial value of the Non-secure VTOR */ + uint32_t init_nsvtor; =20 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU typ= e. diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index af0d935bf78..9ce5c30cd5c 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -176,6 +176,12 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) return; } } + if (object_property_find(OBJECT(s->cpu), "init-nsvtor")) { + if (!object_property_set_uint(OBJECT(s->cpu), "init-nsvtor", + s->init_nsvtor, errp)) { + return; + } + } if (object_property_find(OBJECT(s->cpu), "start-powered-off")) { if (!object_property_set_bool(OBJECT(s->cpu), "start-powered-off", s->start_powered_off, errp)) { @@ -254,6 +260,7 @@ static Property armv7m_properties[] =3D { MemoryRegion *), DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Objec= t *), DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0), + DEFINE_PROP_UINT32("init-nsvtor", ARMv7MState, init_nsvtor, 0), DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false), DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off, false), diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ad65b60b043..9ad6f5911b6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -327,6 +327,7 @@ static void arm_cpu_reset(DeviceState *dev) env->regs[14] =3D 0xffffffff; =20 env->v7m.vecbase[M_REG_S] =3D cpu->init_svtor & 0xffffff80; + env->v7m.vecbase[M_REG_NS] =3D cpu->init_nsvtor & 0xffffff80; =20 /* Load the initial SP and PC from offset 0 and 4 in the vector ta= ble */ vecbase =3D env->v7m.vecbase[env->v7m.secure]; @@ -1272,6 +1273,15 @@ void arm_cpu_post_init(Object *obj) &cpu->init_svtor, OBJ_PROP_FLAG_READWRITE); } + if (arm_feature(&cpu->env, ARM_FEATURE_M)) { + /* + * Initial value of the NS VTOR (for cores without the Security + * extension, this is the only VTOR) + */ + object_property_add_uint32_ptr(obj, "init-nsvtor", + &cpu->init_nsvtor, + OBJ_PROP_FLAG_READWRITE); + } =20 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); =20 --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OuMFA2eQdlNrszvmIFOtEWyVEhnqtmKjrHNCjbXVytw=; b=FlHjFmI6I9FvX7voLKBCUep7AKi2wJW7iNzNtF40PSQKC0gyvAsE5w1hiv+ng1UpbY Ewg1Nslg0lQk8MLyrqJAq9ypWShUFAgkz+hckXglv3qp1RhWWEb6vxHPo+GBxwyX/1ZF JUnfwkAo/jPehbkLXJpipXaXcUHExNty9Ajgt73s26WI+kwC9ZQL/0epROVMMircQhp0 YLiTRXNeEoQxQCDR5TxB7lHbummFQCD2PL0HhAnJdyDuAfQNAKQqhFYFQziKFuHn1HiX SRj7PACQPWvP1vQvEgLGbLnpeKoTuBtX8f77aoj/aoYLGBJL0UrMoeFtWaCWrHD/h0Xf Rhcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OuMFA2eQdlNrszvmIFOtEWyVEhnqtmKjrHNCjbXVytw=; b=P/xafd7BaXIgfqdQW4UApY4rTpE0xwrsnsVkQeL1Iwr01bQJ0m/l9KCOGWx/2EXvjl rGdnbGtHGSqXqpzOWXI5hpSe7MBForAVGoeNw/77cEYqqUvDWpVnHJaP7eNxEUSAkabB uTV6qXoUp2eU5Zn/lzIpKu3ImNJw29ifGmwYoknCqZAmM+A4OwwtGQTfRJhBtVCHvtiW yoBzjOQxbQEaKVcYcsPK169YazldK00mSCM636pVXXOl49xEA1qIy2EWhVhuBkjnWJcy Suxxmt6cOMtgcUgEDPe3fHK5BhrmHV/2VOrkmrJ/knGizGS1zRXrcjI1XE2XdNZLaXFL LA2w== X-Gm-Message-State: AOAM5305t1n/sWI9hHWkRaRmYNwUDHN9OVXZlNfYVf97Y+vBtqGWPxiT MirQmwaOLZC022sGrSIGGDL9ATBSVrieU1mJ X-Google-Smtp-Source: ABdhPJxUpxAPyS/nbZUl9hPSuarhQUascleSSOmX966WjDuUN53jmrVbsVlYcgw13lPakAAy0xuM5g== X-Received: by 2002:a1c:1b93:: with SMTP id b141mr26588317wmb.8.1622735953628; Thu, 03 Jun 2021 08:59:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/45] arm: Consistently use "Cortex-Axx", not "Cortex Axx" Date: Thu, 3 Jun 2021 16:58:28 +0100 Message-Id: <20210603155904.26021-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The official punctuation for Arm CPU names uses a hyphen, like "Cortex-A9". We mostly follow this, but in a few places usage without the hyphen has crept in. Fix those so we consistently use the same way of writing the CPU name. This commit was created with: git grep -z -l 'Cortex ' | xargs -0 sed -i 's/Cortex /Cortex-/' Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Message-id: 20210527095152.10968-1-peter.maydell@linaro.org --- docs/system/arm/aspeed.rst | 4 ++-- docs/system/arm/nuvoton.rst | 6 +++--- docs/system/arm/sabrelite.rst | 2 +- include/hw/arm/allwinner-h3.h | 2 +- hw/arm/aspeed.c | 6 +++--- hw/arm/mcimx6ul-evk.c | 2 +- hw/arm/mcimx7d-sabre.c | 2 +- hw/arm/npcm7xx_boards.c | 4 ++-- hw/arm/sabrelite.c | 2 +- hw/misc/npcm7xx_clk.c | 2 +- 10 files changed, 16 insertions(+), 16 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index a1911f94031..57ee2bd94fc 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -5,7 +5,7 @@ The QEMU Aspeed machines model BMCs of various OpenPOWER sy= stems and Aspeed evaluation boards. They are based on different releases of the Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600 -with dual cores ARM Cortex A7 CPUs (1.2GHz). +with dual cores ARM Cortex-A7 CPUs (1.2GHz). =20 The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C, etc. @@ -24,7 +24,7 @@ AST2500 SoC based machines : =20 AST2600 SoC based machines : =20 -- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex A7) +- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7) - ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC =20 Supported devices diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index d3cf2d9cd7e..ca011bd4797 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -3,19 +3,19 @@ Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``) =20 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are designed to be used as Baseboard Management Controllers (BMCs) in various -servers. They all feature one or two ARM Cortex A9 CPU cores, as well as an +servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an assortment of peripherals targeted for either Enterprise or Data Center / Hyperscale applications. The former is a superset of the latter, so NPCM75= 0 has all the peripherals of NPCM730 and more. =20 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/ =20 -The NPCM750 SoC has two Cortex A9 cores and is targeted for the Enterprise +The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise segment. The following machines are based on this chip : =20 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board =20 -The NPCM730 SoC has two Cortex A9 cores and is targeted for Data Center and +The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and Hyperscale applications. The following machines are based on this chip : =20 - ``quanta-gsj`` Quanta GSJ server BMC diff --git a/docs/system/arm/sabrelite.rst b/docs/system/arm/sabrelite.rst index 71713310e3a..4ccb0560afe 100644 --- a/docs/system/arm/sabrelite.rst +++ b/docs/system/arm/sabrelite.rst @@ -10,7 +10,7 @@ Supported devices =20 The SABRE Lite machine supports the following devices: =20 - * Up to 4 Cortex A9 cores + * Up to 4 Cortex-A9 cores * Generic Interrupt Controller * 1 Clock Controller Module * 1 System Reset Controller diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index cc308a5d2c9..63025fb27c8 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -18,7 +18,7 @@ */ =20 /* - * The Allwinner H3 is a System on Chip containing four ARM Cortex A7 + * The Allwinner H3 is a System on Chip containing four ARM Cortex-A7 * processor cores. Features and specifications include DDR2/DDR3 memory, * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and * various I/O modules. diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 3fe6c55744f..0eafc791540 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -947,7 +947,7 @@ static void aspeed_machine_ast2600_evb_class_init(Objec= tClass *oc, void *data) MachineClass *mc =3D MACHINE_CLASS(oc); AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); =20 - mc->desc =3D "Aspeed AST2600 EVB (Cortex A7)"; + mc->desc =3D "Aspeed AST2600 EVB (Cortex-A7)"; amc->soc_name =3D "ast2600-a1"; amc->hw_strap1 =3D AST2600_EVB_HW_STRAP1; amc->hw_strap2 =3D AST2600_EVB_HW_STRAP2; @@ -966,7 +966,7 @@ static void aspeed_machine_tacoma_class_init(ObjectClas= s *oc, void *data) MachineClass *mc =3D MACHINE_CLASS(oc); AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); =20 - mc->desc =3D "OpenPOWER Tacoma BMC (Cortex A7)"; + mc->desc =3D "OpenPOWER Tacoma BMC (Cortex-A7)"; amc->soc_name =3D "ast2600-a1"; amc->hw_strap1 =3D TACOMA_BMC_HW_STRAP1; amc->hw_strap2 =3D TACOMA_BMC_HW_STRAP2; @@ -1003,7 +1003,7 @@ static void aspeed_machine_rainier_class_init(ObjectC= lass *oc, void *data) MachineClass *mc =3D MACHINE_CLASS(oc); AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); =20 - mc->desc =3D "IBM Rainier BMC (Cortex A7)"; + mc->desc =3D "IBM Rainier BMC (Cortex-A7)"; amc->soc_name =3D "ast2600-a1"; amc->hw_strap1 =3D RAINIER_BMC_HW_STRAP1; amc->hw_strap2 =3D RAINIER_BMC_HW_STRAP2; diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index ce16b6b3174..77fae874b16 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -67,7 +67,7 @@ static void mcimx6ul_evk_init(MachineState *machine) =20 static void mcimx6ul_evk_machine_init(MachineClass *mc) { - mc->desc =3D "Freescale i.MX6UL Evaluation Kit (Cortex A7)"; + mc->desc =3D "Freescale i.MX6UL Evaluation Kit (Cortex-A7)"; mc->init =3D mcimx6ul_evk_init; mc->max_cpus =3D FSL_IMX6UL_NUM_CPUS; mc->default_ram_id =3D "mcimx6ul-evk.ram"; diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index e896222c34c..935d4b0f1cd 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -67,7 +67,7 @@ static void mcimx7d_sabre_init(MachineState *machine) =20 static void mcimx7d_sabre_machine_init(MachineClass *mc) { - mc->desc =3D "Freescale i.MX7 DUAL SABRE (Cortex A7)"; + mc->desc =3D "Freescale i.MX7 DUAL SABRE (Cortex-A7)"; mc->init =3D mcimx7d_sabre_init; mc->max_cpus =3D FSL_IMX7_NUM_CPUS; mc->default_ram_id =3D "mcimx7d-sabre.ram"; diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index d4553e37865..698be46d303 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -299,7 +299,7 @@ static void npcm750_evb_machine_class_init(ObjectClass = *oc, void *data) =20 npcm7xx_set_soc_type(nmc, TYPE_NPCM750); =20 - mc->desc =3D "Nuvoton NPCM750 Evaluation Board (Cortex A9)"; + mc->desc =3D "Nuvoton NPCM750 Evaluation Board (Cortex-A9)"; mc->init =3D npcm750_evb_init; mc->default_ram_size =3D 512 * MiB; }; @@ -311,7 +311,7 @@ static void gsj_machine_class_init(ObjectClass *oc, voi= d *data) =20 npcm7xx_set_soc_type(nmc, TYPE_NPCM730); =20 - mc->desc =3D "Quanta GSJ (Cortex A9)"; + mc->desc =3D "Quanta GSJ (Cortex-A9)"; mc->init =3D quanta_gsj_init; mc->default_ram_size =3D 512 * MiB; }; diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 42348e5cb15..29fc777b613 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -105,7 +105,7 @@ static void sabrelite_init(MachineState *machine) =20 static void sabrelite_machine_init(MachineClass *mc) { - mc->desc =3D "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)"; + mc->desc =3D "Freescale i.MX6 Quad SABRE Lite Board (Cortex-A9)"; mc->init =3D sabrelite_init; mc->max_cpus =3D FSL_IMX6_NUM_CPUS; mc->ignore_memory_transaction_failures =3D true; diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c index a1ee67dc9a1..0b61070c52f 100644 --- a/hw/misc/npcm7xx_clk.c +++ b/hw/misc/npcm7xx_clk.c @@ -35,7 +35,7 @@ #define NPCM7XX_CLOCK_REF_HZ (25000000) =20 /* Register Field Definitions */ -#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */ +#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex-A9 Cores */ =20 #define PLLCON_LOKI BIT(31) #define PLLCON_LOKS BIT(30) --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=y4A3loAc70aEORydGmS/pvr+AOBQjqbEeWONRvfjxfI=; b=gLZe1vL9Hrz9LlbSzVMEymjSuGRPPEjyRgPVdZIIYhFPYVk/nUHIPiLmq0aOkUmku/ L4PrkNHrDtTS6MexTHbyEw72LYtW+CjEnMJfs+CLVqaLdKYyGG8+2hiI4nlb9nBgLxs7 og0N4PZoKxj6rqk0+lRZ0kvONCkM7rN14TpwQfDl1kuiRNi3pxjEW/PrEtmAi4qUj+Oe hSqGD+81d1fL7SWK6gndlOSGARDy48kbVCz3VUT3MyhN8oV6tSbjLMYQuq314rCGtkvj 7jZMIhkvZ4kBKsXELyu4MVzD9p7DXe4commYL80iIhcqk87qfhzb2SMroRbxbtjwGimp OoTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y4A3loAc70aEORydGmS/pvr+AOBQjqbEeWONRvfjxfI=; b=U/LPtHUqR+D6ySaWfr6Q9H/+YHeEp8c1SlkKXX7tT8hg9LT0WQIOgQ81quP5cWlcQl 3f8ONzBA7KGR4HmTixBE/d1a3WMHSBcQav6nUtCdrA3HhulC+9tdU0erdplhEVnMU2O5 XpfFFz0eTl5+PW66ftmS8VMNBGSvhSHyo1WnP6KdhUVsBqj7D9857zHwdcYON6aJd2l0 KK+6lcORbDUJgPnCEjD2v83o2pElinqeZ1Mfe4QtzSHNIfyJfBu1sFGwjkGo1PYpRQld 34l7bexFI6096OgB81tLdR5UIoMMtUktQ85t9Gh+w+fbfG4Bwzx99XR447VIFyyFaZY8 4ZVA== X-Gm-Message-State: AOAM532lycU2z4t+oTuJV/NAq60rgWKvrte7k86qvTzT8kHVWY8SH3nz ms/oNNDEckRTNYn6OLmPwbR0eIWWkhVRukMC X-Google-Smtp-Source: ABdhPJxHPtQ1bdAUF9lBkdGgdrBqhmbH/pqA10JZkdTP5FIbAenUlv2XFE+b5Bnk4DY+M4UzLsR2Uw== X-Received: by 2002:a7b:c24e:: with SMTP id b14mr23132246wmj.6.1622735954278; Thu, 03 Jun 2021 08:59:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/45] docs: Fix installation of man pages with Sphinx 4.x Date: Thu, 3 Jun 2021 16:58:29 +0100 Message-Id: <20210603155904.26021-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Damien Goutte-Gattat The 4.x branch of Sphinx introduces a breaking change, as generated man pages are now written to subdirectories corresponding to the manual section they belong to. This results in `make install` erroring out when attempting to install the man pages, because they are not where it expects to find them. This patch restores the behavior of Sphinx 3.x regarding man pages. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/256 Signed-off-by: Damien Goutte-Gattat Message-id: 20210503161422.15028-1-dgouttegattat@incenp.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/conf.py | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/conf.py b/docs/conf.py index 00cf66ab546..42729e22bbe 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -279,6 +279,7 @@ ['Stefan Hajnoczi ', 'Masayoshi Mizuma '], 1), ] +man_make_section_directory =3D False =20 # -- Options for Texinfo output ------------------------------------------- =20 --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736793; cv=none; d=zohomail.com; s=zohoarc; b=kmVpTBQFaPQ8gtg5F1XxEaoWLWg12vLcZfyCYot3x6r6axqHgRwifCcnG7VuiV7l15JDeq7vvd3r/cfhidsfQHRdYYrr5xUc3b9w84QaiqAEoEAVPcjWfbXZPdw724DO1wpX6mctO7Rfh+LNQK6aNKJTV3CCn7n1DrgaHg6tRgE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736793; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LdNDwicn/e7UW7f5kbwzx9b+TmLTkd72n4ur6XKxILI=; b=mUb/X4elqzFa7suHiny9tbtktFCT8H5+KbgAN9lBLpJcLRlUtdQtJdt++Io7skNQFi+P1jhmTc6e8B8gd20rSUQD0NBhl0QiO3wFcqhXQBKilIRX8OT67MB8WrP2K/97vkkDg61A9d8es2K7zQltLpaB1+naIx/DIk6DpmhTeqw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16227367938083.152852069840719; Thu, 3 Jun 2021 09:13:13 -0700 (PDT) Received: from localhost ([::1]:60786 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lopy4-0002Id-Qh for importer2@patchew.org; Thu, 03 Jun 2021 12:13:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35484) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkc-0008Cs-KJ for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:18 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:44918) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopka-0006qS-Ca for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:18 -0400 Received: by mail-wr1-x430.google.com with SMTP id f2so6354146wri.11 for ; Thu, 03 Jun 2021 08:59:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LdNDwicn/e7UW7f5kbwzx9b+TmLTkd72n4ur6XKxILI=; b=EVkXuNWmIcWo2W1VjFfdp3Mj/LX1s9bRItnFrN6GG6e+2ZLjg1NjOCZ8fbbMHwjCOi 38XpZDTE1IFbld/dx5L9hH0hhAGBbnTMNWbjPMgg/kGOdnP4BhYBaVvA7NeF6tdPXitc mW3mbeUosPwrj7h1KxR1UTDcFyU/XY4G2YrRaId9IWTooT3mChniPk1echDKGs0kbFdK /poCYi6VmROS7ytVoD89wZydS6bX/RFBQvD2KTmMxcCl3tQ/gZOvnYDVWFAtrErbEzb8 O9jzEASoTzvc49CWtPj24GJEuEuXx2j8DE4Ktd5h4cG+csFj9feDc6MsAVjrxcXsZDwL GRhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LdNDwicn/e7UW7f5kbwzx9b+TmLTkd72n4ur6XKxILI=; b=S6sSvHsepKrZCfbLyB7A7MlpaFCIxFw29BICWJoylrqmfAqzSRLCok8ZMLK6cmJ0XS k12mY4HL0ZYCmpRHqL7msKqcwk2jtfZv468LJsjRcmeBUQoCzXoRT4kHhBNfzs3K9Qy3 x0qM+UrFeJztep+SEnwYB+acEO7+Tyh29GCAgp0KpWNSm8kDBuewA9PCfl3q/QRGt2sU AZDq+4/3RUvpiaBhJD4BtiP2Ofn5u1yhSjW+Y1ZqCFUqQpDy8fEOeKDPCKXTfx3hbWKu xcTeCyAounEbaor3avItRHNXQUaP2RSnIbfbh+q2oS7eCHss8eijK06E9wKAkHQO5BmB AvmA== X-Gm-Message-State: AOAM5334qfNCNn+r+v29NcoDQllen5EJSBlgajXMDHl+m1Pb/RosZp7n pzbFWh6suGA0UgYn11/QDl/SsBblz1iIgW4N X-Google-Smtp-Source: ABdhPJxlEDDPS+vXf3QIyZcoSm4aIYhzb3a2dgZZdr62+hUxwiyi71EdWfKWHgqOxE8P87AwIQ+whw== X-Received: by 2002:a5d:4a4e:: with SMTP id v14mr672551wrs.74.1622735954929; Thu, 03 Jun 2021 08:59:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/45] target/arm: Mark LDS{MIN,MAX} as signed operations Date: Thu, 3 Jun 2021 16:58:30 +0100 Message-Id: <20210603155904.26021-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson The operands to tcg_gen_atomic_fetch_s{min,max}_i64 must be signed, so that the inputs are properly extended. Zero extend the result afterward, as needed. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/364 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Message-id: 20210602020720.47679-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ceac0ee2bd6..d6906d9012c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3355,8 +3355,9 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, int o3_opc =3D extract32(insn, 12, 4); bool r =3D extract32(insn, 22, 1); bool a =3D extract32(insn, 23, 1); - TCGv_i64 tcg_rs, clean_addr; + TCGv_i64 tcg_rs, tcg_rt, clean_addr; AtomicThreeOpFn *fn =3D NULL; + MemOp mop =3D s->be_data | size | MO_ALIGN; =20 if (is_vector || !dc_isar_feature(aa64_atomics, s)) { unallocated_encoding(s); @@ -3377,9 +3378,11 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, break; case 004: /* LDSMAX */ fn =3D tcg_gen_atomic_fetch_smax_i64; + mop |=3D MO_SIGN; break; case 005: /* LDSMIN */ fn =3D tcg_gen_atomic_fetch_smin_i64; + mop |=3D MO_SIGN; break; case 006: /* LDUMAX */ fn =3D tcg_gen_atomic_fetch_umax_i64; @@ -3422,6 +3425,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, } =20 tcg_rs =3D read_cpu_reg(s, rs, true); + tcg_rt =3D cpu_reg(s, rt); =20 if (o3_opc =3D=3D 1) { /* LDCLR */ tcg_gen_not_i64(tcg_rs, tcg_rs); @@ -3430,8 +3434,11 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, /* The tcg atomic primitives are all full barriers. Therefore we * can ignore the Acquire and Release bits of this instruction. */ - fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), - s->be_data | size | MO_ALIGN); + fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop); + + if ((mop & MO_SIGN) && size !=3D MO_64) { + tcg_gen_ext32u_i64(tcg_rt, tcg_rt); + } } =20 /* --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736939; cv=none; d=zohomail.com; s=zohoarc; b=ld3LOJEHTv7bIN/B0CoYZMu/Bbw0o0xoNvdyv6vIBSqL2Jr7QaTL48wXCQrlGENvavckgX4+yNX+byRHlkrqiHu2Q9IyZ4P6I4bo6vCvxDtH+YK4IV/tJ/YXl3lCR84EelQqtqYE6pvayaiUrPCWhlP88TQ5mxO7bmmbSH3ba/0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736939; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=e18UyqU2eD7I5G09WnQcZF/NFS28TUDyqVO+oXWqCrE=; b=X/OG129F33SL39ado7b6LfNpchBq4sMC5f2PfWfjAcRHs0HJ4/bIRre96qxin/UJnhxt+lm3s5K893t4gk+S+C9kZ5KAPi6ST/prts4nSkLg8vsK9Rmc6p//KFY7B+SSVu7MIc20+BWHyDtib3c7wklIk4QGr64VyvtScEF9DQ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622736939537804.6064131737138; Thu, 3 Jun 2021 09:15:39 -0700 (PDT) Received: from localhost ([::1]:41038 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loq0Q-0008Ds-Fy for importer2@patchew.org; Thu, 03 Jun 2021 12:15:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35556) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkf-0008Mj-07 for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:21 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:42683) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkb-0006s8-1f for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:20 -0400 Received: by mail-wm1-x332.google.com with SMTP id o2-20020a05600c4fc2b029019a0a8f959dso4008968wmq.1 for ; Thu, 03 Jun 2021 08:59:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=e18UyqU2eD7I5G09WnQcZF/NFS28TUDyqVO+oXWqCrE=; b=zrhdj446QonT4WtFtWW0XFMA75zadna0J164675iGPNO/quBER5LsR0K950FD/lYxe 6kMZ1cUo79F0SA7TYI+5ytytJ/kxZo1JKNFoEmFYbdDCpGIiQZnQeWBPgRzPufRgdmPc UsmCNerAyMdJBfrOc6CApZvUNpUlowtB7nXxhykbHRMd4UKUtSi87PiD7Fcpapqpq3F+ HFtjGecktXZutI5m2XC2vrKQSSiDC5kubuwmyolYrME92kPLknEUJnPM89zgPN9xUH8V rkorimTJnq5/tr6sI0InwFXLOI2dJxl2ohrzhoBm7dcpKvhKpK33HGmcCn/h/ywWiDGp RbOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e18UyqU2eD7I5G09WnQcZF/NFS28TUDyqVO+oXWqCrE=; b=VTB1Vc7aGHOJR+JpujXIqNbb78IqaTODlL3mIsVxWS3+vnjdwvK8HhwxdCS9f/U3oM tqnsHfcLHFpOcF8jrt8A4jefshHJAdW+ki+O4xNg6w0mf47YEYMS46oi02c/iwUN/kjn vNdfGDaZGkK0Ngxdc8DhMlpqPxVmvdKq8E48c8RVxIIi2Whzexi335ffTsdAbzjCOK/S XWRApA9DcNfwyIpsG/Wv+RlLEis0zIi99U1VfUT/Kr9RCNLmFE8C8iRnYOPlIuFfpyJh 1qAzt5X8+A/nwuY/9s+GEEtu2x1Ghcml/KUo6yGE06adP6+a6hBnmWWR4JyXzCgTez9I IUvg== X-Gm-Message-State: AOAM5328tAv3clmxNNlxt2608bPAIwy3FFSnrOp4GGGoTcwWZ56nXroF kK2VQjjNOpkOGVNP9XyI5dqTATDNHmf1a/tL X-Google-Smtp-Source: ABdhPJx8Yb7iWHsfO9y1IUemPQYVpcgWElIssd2UdOH5FEYh58rrl59ptVBEhQ0Ejr2SPQnJWyZDMQ== X-Received: by 2002:a7b:c210:: with SMTP id x16mr9608354wmi.105.1622735955505; Thu, 03 Jun 2021 08:59:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/45] target/arm: fix missing exception class Date: Thu, 3 Jun 2021 16:58:31 +0100 Message-Id: <20210603155904.26021-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Jamie Iles The DAIF and PAC checks used raise_exception_ra to raise an exception and unwind CPU state but raise_exception_ra is currently designed for handling data aborts as the syndrome is partially precomputed and encoded in the TB and then merged in merge_syn_data_abort when handling the data abort. Using raise_exception_ra for DAIF and PAC checks results in an empty syndrome being retrieved from data[2] in restore_state_to_opc and setting ESR to 0. This manifested as: kvm [571]: Unknown exception class: esr: 0x000000 =E2=80=93 Unknown/Uncategorized when launching a KVM guest when the host qemu used a CPU supporting EL2+pointer authentication and enabling pointer authentication in the guest. Rework raise_exception_ra such that the state is restored before raising the exception so that the exception is not clobbered by restore_state_to_opc. Fixes: 0d43e1a2d29a ("target/arm: Add PAuth helpers") Cc: Richard Henderson Cc: Peter Maydell Signed-off-by: Jamie Iles [PMM: added comment] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/op_helper.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index efcb6009927..1a95972bcc5 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -63,8 +63,15 @@ void raise_exception(CPUARMState *env, uint32_t excp, void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t target_el, uintptr_t ra) { - CPUState *cs =3D do_raise_exception(env, excp, syndrome, target_el); - cpu_loop_exit_restore(cs, ra); + CPUState *cs =3D env_cpu(env); + + /* + * restore_state_to_opc() will set env->exception.syndrome, so + * we must restore CPU state here before setting the syndrome + * the caller passed us, and cannot use cpu_loop_exit_restore(). + */ + cpu_restore_state(cs, ra, true); + raise_exception(env, excp, syndrome, target_el); } =20 uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736287; cv=none; d=zohomail.com; s=zohoarc; b=Qwg6ek3n7GcRd9CtZCFMJpFqXmciNgIXOjw+nA/0axltrcpdNn0yB/20MWGNhApB6wb2rqPK0DorNyAglhM8e5ljjcNUiIXdohXN1x/clhLER/JGizRNhvMy4xDJTQjtn3ZlTMHaJf94F4uQWHOl9u71L144NuNyYbY9WQGsVQo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736287; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1HGwW18TMom6V5l1tSNExxNgCY2lniDgLOtuVE6oASQ=; b=JRNtAE7ZyRB8+OKDCSGG81fG9YfhQ589JPk2hS+YM6tf/514GhXLGZuT7A5r7LULhpwpi/FpPBApgQaHETBS0pHyhkmMT1ZubEDXkJFmfY5RPeivNH4CndrPcr/WEVA6mX10dT3v39QJdt9H4iBueVWJ0h82WvfMxX1K8SOjKuk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622736287357405.5523537338687; Thu, 3 Jun 2021 09:04:47 -0700 (PDT) Received: from localhost ([::1]:35512 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loppu-0000yG-A7 for importer2@patchew.org; Thu, 03 Jun 2021 12:04:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35574) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkf-0008Ow-IK for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:21 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:37661) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkb-0006sz-Mc for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:21 -0400 Received: by mail-wr1-x429.google.com with SMTP id i94so1345793wri.4 for ; Thu, 03 Jun 2021 08:59:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1HGwW18TMom6V5l1tSNExxNgCY2lniDgLOtuVE6oASQ=; b=BbpPOUxVlrgQ+aHjxZlWfiQxnjVFN01Nd3KWpSmRUbatZJU3QuyGc4sjVCW7gkMUmI 1abfIhaC8xGiLSLQjzM1e54PRVlR4+NGSdGqHWiKEjXE9dNX9u4rHLMsjVQ8F2HSePcy bTJz7KJuFpOvRtGk/ptIlj4fDzUS9e80/k92WRSgVVWKj0wEzO5tTo6pVoOTmqZNYU/t YTcmQmao9UxlvkLNzw5Bo+YGtOieVUuoyCxJzXf6x1Hd6goKlrwoAOuxgOAF2/OQVU8u TDYiBpX2wFDc0M1t0rxge3xP57F7Q35Rk8NsAXqg27o79CoIxgtNInoaOut0EoEEye0W LglA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1HGwW18TMom6V5l1tSNExxNgCY2lniDgLOtuVE6oASQ=; b=pfKq5Kd/INcq1JskvkL9mjkINtaVwn7L9XE5knYx8Wi0lROKHDfnFqupQw98x9RAyQ zNxpIxX1SuqVcCJpekW6lB1CSiExuV7ZbnYdLLX3WqECAfyN5+dD9p5RVJSWcl90HUcM dPPnV27vfgIcE5OKmtJJ7FuAOlSa//EPRiBGhCIW9qo23MAaqeoEUxDrYtLt/ZoJuKwV 9XdFLcJaMRESyNh90bzSHVb/N07NJXWXSILwrrOZRhb6NqgIo+pJlCelnLShkyzuoa7j Wcoce6LtZqc8n0Zh/H89THAV55fqNdobeT1WH+W7VXQyvnVDpDMJR1hGWyemboTAF7gC dUKA== X-Gm-Message-State: AOAM530DeYVXsqQUsC4WSym5SmXhKOzks+0pBFkdIbIseF/de/Ou/Q83 sWM4gGG3uut1ntEUUK6c6xoqBdng4QHNkIzE X-Google-Smtp-Source: ABdhPJwNUFKY7fDBbIrPO7+lJSXkn0lC18G3FP7yP3Bd7jij6ijlmfIOtPlOj7VFIFn0N/xNanaetg== X-Received: by 2002:a5d:6546:: with SMTP id z6mr682702wrv.100.1622735956096; Thu, 03 Jun 2021 08:59:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/45] target/arm: fold do_raise_exception into raise_exception Date: Thu, 3 Jun 2021 16:58:32 +0100 Message-Id: <20210603155904.26021-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Jamie Iles Now that there are no other users of do_raise_exception, fold it into raise_exception. Cc: Richard Henderson Cc: Peter Maydell Signed-off-by: Jamie Iles Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/op_helper.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 1a95972bcc5..4132f5e430f 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -27,8 +27,8 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) =20 -static CPUState *do_raise_exception(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el) +void raise_exception(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el) { CPUState *cs =3D env_cpu(env); =20 @@ -49,14 +49,6 @@ static CPUState *do_raise_exception(CPUARMState *env, ui= nt32_t excp, cs->exception_index =3D excp; env->exception.syndrome =3D syndrome; env->exception.target_el =3D target_el; - - return cs; -} - -void raise_exception(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el) -{ - CPUState *cs =3D do_raise_exception(env, excp, syndrome, target_el); cpu_loop_exit(cs); } =20 --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737102; cv=none; d=zohomail.com; s=zohoarc; b=Gm0l1NFUTGUZB983XgnCvFtl3UIDN81GmzixSQt6y6LXj6/opTyNPctv3xfJGkVackI3FOEBV+vrVf2duO0wnWXY9emZqjFDAIQvUf+f2cHq1ccrHwXFl8ENZ91+W2LMs5wWib1baV/esFBxH6/jrdBlimnYo4W6wXRRW6+mjaY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737102; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KKCQOZ52SBIC3x4D3HG5fH/KCqqTkgeULQLDUNHuAc8=; b=GWsDaudW2AWdQE3FHlB1fuJf14iAl4GapTK1ZYbKSGlF58ferKsVpPHCFdoEyt4CqpEJ/RgF7CMXYDFYwsuJazyqzs/jk40Sl269hA7hJr5KQf4RTJFR1nlxWxW5ywt/3OUU6sEr/zLp6srvZoyEkn/hoeMB1bQ/8QGudKHds1g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737102534612.5140770744389; Thu, 3 Jun 2021 09:18:22 -0700 (PDT) Received: from localhost ([::1]:49624 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loq33-0006WJ-E3 for importer2@patchew.org; Thu, 03 Jun 2021 12:18:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkf-0008NA-56 for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:21 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:52820) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkc-0006u6-4n for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:20 -0400 Received: by mail-wm1-x32a.google.com with SMTP id f17so3715950wmf.2 for ; Thu, 03 Jun 2021 08:59:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KKCQOZ52SBIC3x4D3HG5fH/KCqqTkgeULQLDUNHuAc8=; b=Uj2xj4YX3tLganT1LMuBpOAy57/3kk/7d49U7R4Ty7RKZlCXoOcjM2pK4AdqpALHYJ b7y9RZBYoKoxdXus6AdBDjEdcSD2PuThJ4ZBjfmWVh8Qee4+aa7l7ATJo+uLHF93muHa pc+gdUG4axqMap+O3RHPH7rLPMAAFUBGDheTSHR8zaIl+RwDnJ/CrKfq/C4jQRo7ONvs srK2Vy9hRy4wIvs3Bbvdxg2CaSAtiiQ4eRT54Eu3E0fbR+LHxKn3g9WEFowBTahqOtQe bE4TIIaZ9CiuYW/Y6z2m1XsHHAfPIlbJgGvU1dpUc+mmSw3/XLTfw1+Dts1Fg2C9TTTt gwFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KKCQOZ52SBIC3x4D3HG5fH/KCqqTkgeULQLDUNHuAc8=; b=p4Xz9zYvQHi/eOByvGwt0q/XcdmTfjYTJzcAjvlAMbPm1sNuJWk8C2KWGY1ybRRT0Y kjAWtAG2v1D1cOlUT+f3+A2jMCmdQcfUgmRK/3+3JJLhtWG2BOoJOn43qtxvDdkF5cgq KTRn47mO/CK4qS7Ge1rFHNWJj0t1KTQKtieKK8P/OzJJ2rSBIKWM5MftJe+nzXXif4MQ AretnUZSaNgnX+O7NLQmJrI5P8E8I04RX416t1xyuMyljxeqtympEzIInrL5gMWg13F1 d0FP4GhcWrG7I79RvxOH5FNEmaQZqufIwhdynlmSA0Q/Chc5UOcdV4D2dTZejPWBUkwg PlBA== X-Gm-Message-State: AOAM532BQKENsZheCHnm0Xay8dmVuOTxA07BFxqmSEhKpDeExVLdy4PZ H4h7aCOIM55kgtwAtK+qgoJEiLWOQVAD+HRG X-Google-Smtp-Source: ABdhPJyLa9eFOtKiKoVDAdSbwN/vX0tx+WSS8C+mt9f0DlJeR23eLeBO7q/9tkKDc1KKYcp0gcW+WQ== X-Received: by 2002:a1c:ddc3:: with SMTP id u186mr10842080wmg.44.1622735956701; Thu, 03 Jun 2021 08:59:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/45] target/arm: use raise_exception_ra for MTE check failure Date: Thu, 3 Jun 2021 16:58:33 +0100 Message-Id: <20210603155904.26021-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Jamie Iles Now that raise_exception_ra restores the state before raising the exception we can use restore_exception_ra to perform the state restore + exception raising without clobbering the syndrome. Cc: Richard Henderson Cc: Peter Maydell Signed-off-by: Jamie Iles [PMM: Keep the one line of the comment that is still relevant] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/mte_helper.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index a6fccc6e69e..166b9d260f8 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -563,20 +563,14 @@ static void mte_check_fail(CPUARMState *env, uint32_t= desc, =20 switch (tcf) { case 1: - /* - * Tag check fail causes a synchronous exception. - * - * In restore_state_to_opc, we set the exception syndrome - * for the load or store operation. Unwind first so we - * may overwrite that with the syndrome for the tag check. - */ - cpu_restore_state(env_cpu(env), ra, true); + /* Tag check fail causes a synchronous exception. */ env->exception.vaddress =3D dirty_ptr; =20 is_write =3D FIELD_EX32(desc, MTEDESC, WRITE); syn =3D syn_data_abort_no_iss(arm_current_el(env) !=3D 0, 0, 0, 0,= 0, is_write, 0x11); - raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env= )); + raise_exception_ra(env, EXCP_DATA_ABORT, syn, + exception_target_el(env), ra); /* noreturn, but fall through to the assert anyway */ =20 case 0: --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737283; cv=none; d=zohomail.com; s=zohoarc; b=dBHHmEFdmHjgEP+nofiNh8ypHEqpPnNmjLXMIjlvrsT+dIjL/aHL8WDvoPpRig89IAKueNREI3Rsof41Y3wVu2vCHVfRluVmJ2sShObvbTScY+OkJZLmU4Vz95K4l8o6rp4oVNBbh+02qs4kJbgr9eMLbi+RwDjchYVty1OEgbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737283; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ipQH9FuAs2789OheroE8XiY1nFKS7axl26Lt0pkbQjg=; b=HMm1+9RhmRvbsHf0FCC2o9Am/Vl2AyiBuvNky1iRzh/a3Wmrj3OWYNc6HPgBeQomOC8Cgrps5UhiYtp7qZmMjzN/sycM8v6gk3NJIrTjpUO8qGJVfYbzrGo1sFlxpReA4Lq/w+C1zbCtULv/HY7MOsYRLMxVsKiezgnQHyDpTSw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162273728346811.30052748301614; Thu, 3 Jun 2021 09:21:23 -0700 (PDT) Received: from localhost ([::1]:57960 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loq5y-00055I-EI for importer2@patchew.org; Thu, 03 Jun 2021 12:21:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkf-0008OB-CB for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:21 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:40571) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkd-0006ua-1o for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:21 -0400 Received: by mail-wr1-x431.google.com with SMTP id y7so1751532wrh.7 for ; Thu, 03 Jun 2021 08:59:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ipQH9FuAs2789OheroE8XiY1nFKS7axl26Lt0pkbQjg=; b=N2yHLRfEC7B5dRQAt6YxfyZsYlhXhwhCE/FKk4yBSGzhHno5HO1KkIQRS3SXi3iMHA pQzq6hj9EQr4acjjzvXRDNmozlv5RxdAN4DcGlvR/YQduOsR9a1uad5VJHQii2M/ggtA kt0KgFLhV42534ZPYBIvBtlEhaDnaI/13HGC0sfHqCbvPCrDH5WeFlVxYz8SdlpjKhFy aNghuST+gbWKw7+2tSe3Kzoqf1g1clfCiUXnZM+TuMYQV+PlC9fAhVke4VsB3ySRe5ru trqIWTXFRNAGhdSR956f82YWAdD5rQNKVY5ney+iW/ecaJTkVdJEZF1W2Cn/vhMBNJ1+ kEeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ipQH9FuAs2789OheroE8XiY1nFKS7axl26Lt0pkbQjg=; b=Gcska2nlo+Llu1RFXMCxg0apEQix/SrHdTktr1ev47YL2KzkJsqvGHMZ6BCYcDET4F T4D7j1wbis96bbr4r7Z29spYloUV8pw+B62rxUEgpwjebDy6TaV6uSW+me5Xs3I2SmK5 0VYUKl1XcCafQ9I64Rwylh9egC/rrIobgst/pRZ3tF5vBZTlhzYkeNnu5KvOB88U16kA GKoI9sOKf1W4WGZMidZa2tu3VskxcU3uX6VZpc4RXNJIqgOermqVVCWJS6r57nGSeJ+J yJ7w7J9I4+mZa1cWFCFfIVYFDFG/X5z4VWdXgmxry/jVURcIb0IDaq4dNHxAw6g43GHe e/fQ== X-Gm-Message-State: AOAM531xA5DLufjwyUP/s8HDPbvH8uV8dVPAIWipgWX4nIS4mponElcR ka2WFoOduKhvvBosLHymxGeYshk6zQ0DiP6u X-Google-Smtp-Source: ABdhPJxNjACtSVf2xKz7HRb+O//F95a8lWQhgsh1E3Fu/QUAiaOAjmcU2SGyXvc7s0yCE75RFqHbRw== X-Received: by 2002:adf:e54f:: with SMTP id z15mr637101wrm.141.1622735957379; Thu, 03 Jun 2021 08:59:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/45] target/arm: use raise_exception_ra for stack limit exception Date: Thu, 3 Jun 2021 16:58:34 +0100 Message-Id: <20210603155904.26021-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Jamie Iles The sequence cpu_restore_state() + raise_exception() is equivalent to raise_exception_ra(), so use that instead. (In this case we never cared about the syndrome value, because M-profile doesn't use the syndrome; the old code was just written unnecessarily awkwardly.) Cc: Richard Henderson Cc: Peter Maydell Signed-off-by: Jamie Iles [PMM: Retain edited version of comment; rewrite commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/m_helper.c | 5 +---- target/arm/op_helper.c | 9 +++------ 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index eda74e55450..074c5434550 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2601,10 +2601,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t mask= reg, uint32_t val) limit =3D is_psp ? env->v7m.psplim[false] : env->v7m.msplim[fa= lse]; =20 if (val < limit) { - CPUState *cs =3D env_cpu(env); - - cpu_restore_state(cs, GETPC(), true); - raise_exception(env, EXCP_STKOF, 0, 1); + raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC()); } =20 if (is_psp) { diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 4132f5e430f..e98fd863057 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -95,15 +95,12 @@ void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t = newvalue) * raising an exception if the limit is breached. */ if (newvalue < v7m_sp_limit(env)) { - CPUState *cs =3D env_cpu(env); - /* * Stack limit exceptions are a rare case, so rather than syncing - * PC/condbits before the call, we use cpu_restore_state() to - * get them right before raising the exception. + * PC/condbits before the call, we use raise_exception_ra() so + * that cpu_restore_state() will sort them out. */ - cpu_restore_state(cs, GETPC(), true); - raise_exception(env, EXCP_STKOF, 0, 1); + raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC()); } } =20 --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736443; cv=none; d=zohomail.com; s=zohoarc; b=kKM5L7tYS5fsCL++nF4Y+xxom5Y2EQl4RJXBBQL7dXIY2LI/8EtfzBeAl5rh2joE5ICx1OjH+JE2GbQeVrkZvzyHVpMZEfEmexrVJnZcJpUSyBcz3EU9yNXRBL+w3UqqNjEfHj5XHSfoty8ybSgnjmGytZZ97lUUwS977pI7Xjk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736443; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/gg8JIdwvW0DYrrjVDsWjQEmdjygTIDM1ioXoiWVJ3A=; b=DQEyXRuxPtmcX5MSK6Kzdr2e8OZSgZ0FGlIRelt9X+3PW1DwHVTn4WwSMf73qEjnrmP8E7pBHtJAvFZfhIT6WQ17h2JjbjaglWKjaEEPnXnMs4WCWcGeKNAANEUc7WUCguPWOGQeKeo7GkuYGIRPEA/uvp9gG+4JHd9IcYqoTFM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622736443542290.1899893747769; Thu, 3 Jun 2021 09:07:23 -0700 (PDT) Received: from localhost ([::1]:44154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lopsO-00071F-DR for importer2@patchew.org; Thu, 03 Jun 2021 12:07:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35586) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkf-0008Pp-Ok for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:21 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:42623) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkd-0006v3-Bz for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:21 -0400 Received: by mail-wr1-x42e.google.com with SMTP id c5so6356602wrq.9 for ; Thu, 03 Jun 2021 08:59:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/gg8JIdwvW0DYrrjVDsWjQEmdjygTIDM1ioXoiWVJ3A=; b=cLAxiIvbc2YBk81gNKQb3tXBjIZ8X7Ktv7lDlUYIIRm/lPnjoC7QITyOQPtQFASA49 EhK0+wkE1ojiTw+2Mg/UywTl/t/PUvb5noyTMqGtO0P9Rq00kCcNlN1jHzNV2BZWrbwo 3MPDIar+EkjHbTri96hyCWXLHiUdjCGDQ6VoJQQRtRMwIE9bNQOiWAvhW37hAU4a79HZ C9HLP3Ti4SXTKvJLugy9DbrDl07hETPhDI2RdjrID99GTvnxVT+hL95NyVSIlaLUThTJ IzN68WJBrQ70ulA3jTHOdLZDgzj3aJkI2QG32du+GL1mpAbihQMEn81pRfE4M/PG88TF HR0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/gg8JIdwvW0DYrrjVDsWjQEmdjygTIDM1ioXoiWVJ3A=; b=eb8VUx0RRcihVmfEOr8lstUdi/0ZwjvTPpA/8YpDbwjh1qFhVF64HQ5G6hR9r9wfgJ 6ysHsC60WYDavbaknLHZZ4xI7aNv6Zwc0GnvF7TOp+CGt4EdAekZh9LMgEksWy97ogY4 5CX6eCM75GDygS0u9Od3zvKhUtMj0l7xzvcAysZ+uDXkSQHwnBB6UN/d+mXRP8hX9r8u z+gbjZ8ITpELAGyetViqB3Fq4C3Vfmd3ecfYqIcUVvfw7TxchYUL7rizv4+9kuZpBtaT eFyp0YJQtIw6kUiEzXxDn+6Qd9r7vDqbgn4VqXQpEkYztnb7aW23TB8El5w+NTuTIiWh Ae4g== X-Gm-Message-State: AOAM531ZGw5oHPNAP0Gs0sZDnkczlo8J/Z0OeQu8l9jkfzDDaA3ESPu1 v9f9sgWgY7Cd4MRMH0avv3zstS9sKXsxoAIZ X-Google-Smtp-Source: ABdhPJzPFQkT/XzKiF95U4LYPNhN40p9xJcnsJ1O1/EtSlHu5O8ZlQLLJcM5DC4h8gmlZzsNF8haHA== X-Received: by 2002:adf:f346:: with SMTP id e6mr622841wrp.179.1622735958013; Thu, 03 Jun 2021 08:59:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/45] target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16 Date: Thu, 3 Jun 2021 16:58:35 +0100 Message-Id: <20210603155904.26021-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Note that the SVE BFLOAT16 support does not require SVE2, it is an independent extension. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5f234834c0d..be9a4dceae1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3792,6 +3792,11 @@ static inline bool isar_feature_aa32_predinv(const A= RMISARegisters *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) !=3D 0; } =20 +static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) !=3D 0; +} + static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) !=3D 0; @@ -4153,6 +4158,11 @@ static inline bool isar_feature_aa64_dcpodp(const AR= MISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >=3D 2; } =20 +static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) !=3D 0; +} + static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically. */ @@ -4297,6 +4307,11 @@ static inline bool isar_feature_aa64_sve2_bitperm(co= nst ARMISARegisters *id) return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) !=3D 0; } =20 +static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) !=3D 0; +} + static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) !=3D 0; --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736802; cv=none; d=zohomail.com; s=zohoarc; b=G6Ro5eoIFIlU5/BuYk3x1ImsWV90cWYKOYZYVCA8qDAIa9OislVNxTscnLuojAiV7SXYZH3Rpd6bvxyJ6kLEp1rRAN7gkMZsX/0kknI9wXbVvW//v6TIaTn10VMphbYluNhiz9vtWhUv+MjsXREpmhF6lEUd7Xs+Ek+LqB4VFg8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736802; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0dZUtAFjQWxKrKqvrClsTUtAI33YGQrz6/E16mdLOUw=; b=X8HIoip4EfTMx01z4QDuTSCqbaS0fm8Z6ZZy+2cbzN+MBkX7hquHYlXQkOqNAzVLOQJ+Y9RsyvLQYat8+HGyau/fEM3zJrdUxUoXDlZ203vtVMtLfIVOzYjZjZuWDhwnmmcJKEjotOz7p7NRAuGjVWfA5pujEsTb9Q2h7JS0zr8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622736802849373.88432571168767; Thu, 3 Jun 2021 09:13:22 -0700 (PDT) Received: from localhost ([::1]:33484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lopyD-0002xp-RE for importer2@patchew.org; Thu, 03 Jun 2021 12:13:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkk-0000L4-Li for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:26 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:37667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopke-0006wH-7V for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:26 -0400 Received: by mail-wr1-x42f.google.com with SMTP id i94so1345973wri.4 for ; Thu, 03 Jun 2021 08:59:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d6906d9012c..95c2853f39f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6501,8 +6501,7 @@ static void disas_fp_1src(DisasContext *s, uint32_t i= nsn) int rd =3D extract32(insn, 0, 5); =20 if (mos) { - unallocated_encoding(s); - return; + goto do_unallocated; } =20 switch (opcode) { @@ -6511,8 +6510,7 @@ static void disas_fp_1src(DisasContext *s, uint32_t i= nsn) /* FCVT between half, single and double precision */ int dtype =3D extract32(opcode, 0, 2); if (type =3D=3D 2 || dtype =3D=3D type) { - unallocated_encoding(s); - return; + goto do_unallocated; } if (!fp_access_check(s)) { return; @@ -6524,8 +6522,7 @@ static void disas_fp_1src(DisasContext *s, uint32_t i= nsn) =20 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */ if (type > 1 || !dc_isar_feature(aa64_frint, s)) { - unallocated_encoding(s); - return; + goto do_unallocated; } /* fall through */ case 0x0 ... 0x3: @@ -6547,8 +6544,7 @@ static void disas_fp_1src(DisasContext *s, uint32_t i= nsn) break; case 3: if (!dc_isar_feature(aa64_fp16, s)) { - unallocated_encoding(s); - return; + goto do_unallocated; } =20 if (!fp_access_check(s)) { @@ -6557,11 +6553,12 @@ static void disas_fp_1src(DisasContext *s, uint32_t= insn) handle_fp_1src_half(s, opcode, rd, rn); break; default: - unallocated_encoding(s); + goto do_unallocated; } break; =20 default: + do_unallocated: unallocated_encoding(s); break; } --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736598; cv=none; d=zohomail.com; s=zohoarc; b=Jjh8rc9I7Wz258NQuXbQRd7DZZe8KJaJRr9/C7ptD0a9SbHba/ZqPDwIwDPWL5QY8FUP/YQ51DHuLEzP+WnkEHLsqhyhCgVippWfprMx0XeMdOoMJy3wCcYNQQ64pL+hQd+E/sujNF5VA0swmRXiJI16QXK5K1azWOvTMaEbJBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736598; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Wqh7RQOq9hwUwMON5DQGW2Bekv7kpbEi7rQDGxxuy/Q=; b=ZTQtI5Vrw2PjArrj5ofkiQmOozic/vsdhB8IboBLfdg/YLHNPi3Ztje8ceWkRwr77b AfQDOI/zkbcfWfRQbjHSxNcMjpRW/p2mbDnB9xywa1DED6oHTHA6Z+uFNQz4SzUXutiH DrfaQYgf+8Pj7fPbIqSLEccMd7yIsbljErLbh7QW3EXR46haSDEKWGydHzSlwMWEiUQ6 oE7g4JCnU2m0zCb03gu7UfuIIP2dV5DMqTzXD+yQKGTFdl1Ea9FkHlCncx+Fm7IoRWey 9xqes3EkSs8q6cc2M0XYr2O793Pr+AKeTzl1y+zrrhP06gpJvQqUOx1c8LL3HaFYem7T xQHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wqh7RQOq9hwUwMON5DQGW2Bekv7kpbEi7rQDGxxuy/Q=; b=LT5m3KefopSFZR+sRe5IeY8FSkPqqeJfOtBejP7Alo0w1Y/selaqwpyVWUI4Dq9NIh e5H/b/Tde6Y0knca+Fn1obJdFwIK/yVxgyhuk5+7SLDNm1fq8GgB62jERL9AtlzVyBkY L22uCbCvGXvzQ1kD4FfH/CYw2hQX9RFhkkiIpgc3/O1XMHHx7JeIQJ0IHnuLw8RJsyjm oJ5rRMDGnfp12fbE4QJPqt6YdwpIxuXunO+d0nzsPVfqUygr2mkFrmCvZqLCifsSG5EU ZSifnZ4JZUjptepSsDffhBSI7ToP4+Odirh6OfFy0KtsrOY2/UG6pleepC9i6OoFi8zK /TFg== X-Gm-Message-State: AOAM533HxFBEaW3tBr371uEl+DgO5i49ZKSVmu35OE8hDPdYB0xpFSjG 6Mwwm0escpMm2unuFseI5xUmIpABRMmzsjfc X-Google-Smtp-Source: ABdhPJzCBCmd2b/5oxe4RGAaW59CczHKIah+zhpwUItOQXG5XRVDgh38hMqDgsDWvajrM9FYOTGqLw== X-Received: by 2002:a05:600c:4f01:: with SMTP id l1mr4510534wmq.123.1622735960070; Thu, 03 Jun 2021 08:59:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/45] target/arm: Implement scalar float32 to bfloat16 conversion Date: Thu, 3 Jun 2021 16:58:37 +0100 Message-Id: <20210603155904.26021-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is the 64-bit BFCVT and the 32-bit VCVT{B,T}.BF16.F32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 1 + target/arm/vfp.decode | 2 ++ target/arm/translate-a64.c | 19 +++++++++++++++++++ target/arm/translate-vfp.c | 24 ++++++++++++++++++++++++ target/arm/vfp_helper.c | 5 +++++ 5 files changed, 51 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index 23ccb0f72f6..9977a827e97 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -143,6 +143,7 @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env) =20 DEF_HELPER_2(vfp_fcvtds, f64, f32, env) DEF_HELPER_2(vfp_fcvtsd, f32, f64, env) +DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, ptr) =20 DEF_HELPER_2(vfp_uitoh, f16, i32, ptr) DEF_HELPER_2(vfp_uitos, f32, i32, ptr) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 6f7f28f9a46..52535d9b0b8 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -205,6 +205,8 @@ VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 ....= \ =20 # VCVTB and VCVTT to f16: Vd format is always vd_sp; # Vm format depends on size bit +VCVT_b16_f32 ---- 1110 1.11 0011 .... 1001 t:1 1.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_sp VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 95c2853f39f..b335ca87355 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6280,6 +6280,9 @@ static void handle_fp_1src_single(DisasContext *s, in= t opcode, int rd, int rn) case 0x3: /* FSQRT */ gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); goto done; + case 0x6: /* BFCVT */ + gen_fpst =3D gen_helper_bfcvt; + break; case 0x8: /* FRINTN */ case 0x9: /* FRINTP */ case 0xa: /* FRINTM */ @@ -6557,6 +6560,22 @@ static void disas_fp_1src(DisasContext *s, uint32_t = insn) } break; =20 + case 0x6: + switch (type) { + case 1: /* BFCVT */ + if (!dc_isar_feature(aa64_bf16, s)) { + goto do_unallocated; + } + if (!fp_access_check(s)) { + return; + } + handle_fp_1src_single(s, opcode, rd, rn); + break; + default: + goto do_unallocated; + } + break; + default: do_unallocated: unallocated_encoding(s); diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 2316e105acc..d01e465821b 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -3085,6 +3085,30 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) return true; } =20 +static bool trans_VCVT_b16_f32(DisasContext *s, arg_VCVT_b16_f32 *a) +{ + TCGv_ptr fpst; + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_bf16, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D fpstatus_ptr(FPST_FPCR); + tmp =3D tcg_temp_new_i32(); + + vfp_load_reg32(tmp, a->vm); + gen_helper_bfcvt(tmp, tmp, fpst); + tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} + static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a) { TCGv_ptr fpst; diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index e0886ab5a56..200439ad663 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -411,6 +411,11 @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *e= nv) return float64_to_float32(x, &env->vfp.fp_status); } =20 +uint32_t HELPER(bfcvt)(float32 x, void *status) +{ + return float32_to_bfloat16(x, status); +} + /* * VFP3 fixed point conversion. The AArch32 versions of fix-to-float * must always round-to-nearest; the AArch64 ones honour the FPSCR --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737398; cv=none; d=zohomail.com; s=zohoarc; b=dEBcru1kTpo0UqaESLX134962X1noMgTNC/Xwcgzv6BA6EbRKqN8GHSH5arrP8vHaydnnOKdcBln9gSMpFQTNBMeoEdYseVr22NunQdDzL/h2we9sS56g1nBsRoskeKXvXCBW3f7jSUO5e4P4iH13FCoF7lPnYBNeg5R5AIHFWM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737398; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DHVb1tnpy0DBJtmw7btlmbFe9TBN5mVPiuiCOc9VpHs=; b=CioQkoDSW0ZDl6RI8nvx9Ys9EfHK/nVbAvvEfPGs209Zz4W57rVH8T7t/AbL/7tuZ7pwsz50rIiL1PsaprreLI3e1ParkDV62tYCScHPzUKUcwgNBksz8nyPpBVIxbtTFT5AyDnvE/vvL0yU08E3AL7fUS3Yhy+43OtkRwKukrA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737398412311.81280269799447; Thu, 3 Jun 2021 09:23:18 -0700 (PDT) Received: from localhost ([::1]:38554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loq7p-0002ww-4A for importer2@patchew.org; Thu, 03 Jun 2021 12:23:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35678) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkk-0000K8-F5 for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:26 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:40570) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkg-0006za-Nl for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:26 -0400 Received: by mail-wr1-x42f.google.com with SMTP id y7so1751757wrh.7 for ; Thu, 03 Jun 2021 08:59:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DHVb1tnpy0DBJtmw7btlmbFe9TBN5mVPiuiCOc9VpHs=; b=MdvDLKjZR6PGDqMzg92w4mhORS966G4w9C6Zmwbgg0nHkgI+2OYSVZHXQXLueuYIXw 7rz3b6u0iCpBwZC7jRgUIr4AEXsxQyTEx+0eDJEJKzSHVpiJxLSiDJjrdl/at5G6buDw b20/j5rCcgpgq24VFZJppKHCSqBWro1mE1v5XMjPKp3GOK09U4DHdWxwQfWb4nXWA5yL D+lkLwIl1ghUtswQcezsCLBxqqNCEDvyQuOmVXto0aCtp7GWyvtw6cMCRKqvnW2R9c/h 9Jf2ZDF3F5uuOdtqH7bsPLLozYtng5K00/1v6QYisP55R2cTl1FMtYZtFrlP+T8x0jXx k5JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DHVb1tnpy0DBJtmw7btlmbFe9TBN5mVPiuiCOc9VpHs=; b=RM72gIO/4f/slqjS0qpd06cBzFzrjiTRxD71//dDVDdrlto7+Cz3JoxvKnGjbrlgYN zXBbALLyRY2gK4nUq+777hnb6LJ/4/Os17BCUNYRz4CMNeJI1Sj3LND6gWSJjkvOvsDT jfgcb1pSC2yWwEdBI1ZC/tYlOa0B/jm7S+4qaT79+iahvpv+Vq//TZIbvlWx6g21xq1X 0KYonybiYtqqzvoQ+vp/dng1syOqUrGwX+rsoAnyhJx4mgMMzJhl5HJBqx9N5/0JSnC3 3T4JDvkl2H0PYallV2rSO+k5QtetS2wwfac2D+M6xLc1tKpm23sBsm7Mne78mNQqFudB 8DoA== X-Gm-Message-State: AOAM530+SvMqxOPNHBSI2xm2oMwhS5+3b9H3C88U5tib3YuolL5CwFHz HIWpLtsR5Gd839eJIuV+QwSXgmlJ2UKN/DSS X-Google-Smtp-Source: ABdhPJxpDg0GnzcNIZRMf/c+qko8qI0h9/oWvTrM/pONRRNfEd+KTjqd1gkffRuVx1VNBPGyJdNhCw== X-Received: by 2002:a5d:4dc2:: with SMTP id f2mr680772wru.124.1622735961460; Thu, 03 Jun 2021 08:59:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/45] target/arm: Implement vector float32 to bfloat16 conversion Date: Thu, 3 Jun 2021 16:58:38 +0100 Message-Id: <20210603155904.26021-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is BFCVT{N,T} for both AArch64 AdvSIMD and SVE, and VCVT.BF16.F32 for AArch32 NEON. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-sve.h | 4 ++++ target/arm/helper.h | 1 + target/arm/neon-dp.decode | 1 + target/arm/sve.decode | 2 ++ target/arm/sve_helper.c | 2 ++ target/arm/translate-a64.c | 17 ++++++++++++++ target/arm/translate-neon.c | 45 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 16 +++++++++++++ target/arm/vfp_helper.c | 7 ++++++ 9 files changed, 95 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 29a14a21f50..dc629f851a3 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -1197,6 +1197,8 @@ DEF_HELPER_FLAGS_5(sve_fcvt_hd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_fcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_bfcvt, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_5(sve_fcvtzs_hh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) @@ -2752,6 +2754,8 @@ DEF_HELPER_FLAGS_5(sve2_fcvtnt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve2_fcvtnt_ds, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_bfcvtnt, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_5(sve2_fcvtlt_hs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/helper.h b/target/arm/helper.h index 9977a827e97..8b4b7d92f36 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -144,6 +144,7 @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env) DEF_HELPER_2(vfp_fcvtds, f64, f32, env) DEF_HELPER_2(vfp_fcvtsd, f32, f64, env) DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, ptr) +DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, ptr) =20 DEF_HELPER_2(vfp_uitoh, f16, i32, ptr) DEF_HELPER_2(vfp_uitos, f32, i32, ptr) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index ec83f10ab35..fd3a01bfa0b 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -521,6 +521,7 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 = . op:1 1 .... @1reg_imm VRINTZ 1111 001 11 . 11 .. 10 .... 0 1011 . . 0 .... @2misc =20 VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0 + VCVT_B16_F32 1111 001 11 . 11 .. 10 .... 0 1100 1 . 0 .... @2misc_q0 =20 VRINTM 1111 001 11 . 11 .. 10 .... 0 1101 . . 0 .... @2misc =20 diff --git a/target/arm/sve.decode b/target/arm/sve.decode index cb077bfde90..18d1a0eecc5 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1036,6 +1036,7 @@ FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ...= .. @rdn_pg_rm_ra # SVE floating-point convert precision FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_= e0 FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_= e0 +BFCVT 01100101 10 0010 10 101 ... ..... ..... @rd_pg_rn_= e0 FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_= e0 FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_= e0 FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_= e0 @@ -1610,6 +1611,7 @@ RAX1 01000101 00 1 ..... 11110 1 ..... ...= .. @rd_rn_rm_e0 FCVTXNT_ds 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 FCVTX_ds 01100101 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 +BFCVTNT 01100100 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0 FCVTLT_hs 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 FCVTLT_sd 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 40af3024dfb..46a957b6fb0 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4708,6 +4708,7 @@ static inline uint64_t vfp_float64_to_uint64_rtz(floa= t64 f, float_status *s) =20 DO_ZPZ_FP(sve_fcvt_sh, uint32_t, H1_4, sve_f32_to_f16) DO_ZPZ_FP(sve_fcvt_hs, uint32_t, H1_4, sve_f16_to_f32) +DO_ZPZ_FP(sve_bfcvt, uint32_t, H1_4, float32_to_bfloat16) DO_ZPZ_FP(sve_fcvt_dh, uint64_t, , sve_f64_to_f16) DO_ZPZ_FP(sve_fcvt_hd, uint64_t, , sve_f16_to_f64) DO_ZPZ_FP(sve_fcvt_ds, uint64_t, , float64_to_float32) @@ -7740,6 +7741,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, void = *status, uint32_t desc) \ } while (i !=3D 0); = \ } =20 +DO_FCVTNT(sve_bfcvtnt, uint32_t, uint16_t, H1_4, H1_2, float32_to_bfloa= t16) DO_FCVTNT(sve2_fcvtnt_sh, uint32_t, uint16_t, H1_4, H1_2, sve_f32_to_f16) DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, , H1_4, float64_to_float= 32) =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b335ca87355..0f15fa42fc3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10353,6 +10353,13 @@ static void handle_2misc_narrow(DisasContext *s, b= ool scalar, tcg_temp_free_i32(ahp); } break; + case 0x36: /* BFCVTN, BFCVTN2 */ + { + TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR); + gen_helper_bfcvt_pair(tcg_res[pass], tcg_op, fpst); + tcg_temp_free_ptr(fpst); + } + break; case 0x56: /* FCVTXN, FCVTXN2 */ /* 64 bit to 32 bit float conversion * with von Neumann rounding (round to odd) @@ -12753,6 +12760,16 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) } handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, r= d); return; + case 0x36: /* BFCVTN, BFCVTN2 */ + if (!dc_isar_feature(aa64_bf16, s) || size !=3D 2) { + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { + return; + } + handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, r= d); + return; case 0x17: /* FCVTL, FCVTL2 */ if (!fp_access_check(s)) { return; diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 9e990b41eda..6d94229c691 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -3422,6 +3422,51 @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *= a) return true; } =20 +static bool trans_VCVT_B16_F32(DisasContext *s, arg_2misc *a) +{ + TCGv_ptr fpst; + TCGv_i64 tmp; + TCGv_i32 dst0, dst1; + + if (!dc_isar_feature(aa32_bf16, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm & 1) || (a->size !=3D 1)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D fpstatus_ptr(FPST_STD); + tmp =3D tcg_temp_new_i64(); + dst0 =3D tcg_temp_new_i32(); + dst1 =3D tcg_temp_new_i32(); + + read_neon_element64(tmp, a->vm, 0, MO_64); + gen_helper_bfcvt_pair(dst0, tmp, fpst); + + read_neon_element64(tmp, a->vm, 1, MO_64); + gen_helper_bfcvt_pair(dst1, tmp, fpst); + + write_neon_element32(dst0, a->vd, 0, MO_32); + write_neon_element32(dst1, a->vd, 1, MO_32); + + tcg_temp_free_i64(tmp); + tcg_temp_free_i32(dst0); + tcg_temp_free_i32(dst1); + tcg_temp_free_ptr(fpst); + return true; +} + static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a) { TCGv_ptr fpst; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9574efe9578..fb692a18351 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4777,6 +4777,14 @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_e= sz *a) return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_h= s); } =20 +static bool trans_BFCVT(DisasContext *s, arg_rpr_esz *a) +{ + if (!dc_isar_feature(aa64_sve_bf16, s)) { + return false; + } + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvt); +} + static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_d= h); @@ -8472,6 +8480,14 @@ static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr= _esz *a) return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtn= t_sh); } =20 +static bool trans_BFCVTNT(DisasContext *s, arg_rpr_esz *a) +{ + if (!dc_isar_feature(aa64_sve_bf16, s)) { + return false; + } + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvtn= t); +} + static bool trans_FCVTNT_ds(DisasContext *s, arg_rpr_esz *a) { if (!dc_isar_feature(aa64_sve2, s)) { diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 200439ad663..496f0034772 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -416,6 +416,13 @@ uint32_t HELPER(bfcvt)(float32 x, void *status) return float32_to_bfloat16(x, status); } =20 +uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status) +{ + bfloat16 lo =3D float32_to_bfloat16(extract64(pair, 0, 32), status); + bfloat16 hi =3D float32_to_bfloat16(extract64(pair, 32, 32), status); + return deposit32(lo, 16, 16, hi); +} + /* * VFP3 fixed point conversion. The AArch32 versions of fix-to-float * must always round-to-nearest; the AArch64 ones honour the FPSCR --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736683; cv=none; d=zohomail.com; s=zohoarc; b=fVmP4bZAj0lgAp7i3wt2fF9zAYRzM/Lx2FjfgSMH81L0hJCKz4gNdm7vyP25GO//LYTFI4stsHyY4snz5vvKzS75WGNVCCsrKHpzKuwXl7GzsSdzVQuvgmS/Ba6KUkvoM94ObWpH5/4In2n0l1xxw+z4uctoD+YTXd+g1eTmknw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736683; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sDoUJAYn0yIc6w7KX8ASaLZmx5h0oxVG9cXFpdPESQk=; b=jWoey5BIU7UZCjUM/C1Z0suVg9sJiuSxqfM9DdsjYhinP6GokoofrbcHdK3RkZu2wf6lWHyuE1pPLNSBSdW3Sr81NgDQqGJpkAn0Xy9pC0vuEfiDqVlGGABBL0BxVMET2CfBx152jskDh1UB8qihIoEa8SSMRBzAr9wudZGxMFY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622736683615347.5952193057834; Thu, 3 Jun 2021 09:11:23 -0700 (PDT) Received: from localhost ([::1]:55780 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lopwI-00070g-IM for importer2@patchew.org; Thu, 03 Jun 2021 12:11:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkj-0000Ek-DD for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:25 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:43608) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkh-0006zx-Ej for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:25 -0400 Received: by mail-wr1-x436.google.com with SMTP id u7so938697wrs.10 for ; Thu, 03 Jun 2021 08:59:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sDoUJAYn0yIc6w7KX8ASaLZmx5h0oxVG9cXFpdPESQk=; b=A/fGlAUgazC5srhZmgdLJm/JgP9pveOOe4+IMkcFBMV1bZ1Dyf3n4dJvetVV6xH2hL Tma7W4HpAbkwoEVeMhujEdwK/nEz4ktfqrBf0oRsmwkSEDjpiJFU39bWUo4q9GPBrP4e wwHW67eIfv6pS5a1RTMNfxYKr3hOqsUg150jgej0sYuKr85INEAo0ogqLuuDMKjVd0tu +r6L6IBGiAC+ea9TIPIH+3iMUOMXEIkuDkrXAVc/9khOXcaUYn5E+txfediBZC8OW8Cp LNPqC+Gi319dpIvex+EgdyBV6UwKuOudatemtPpECkSp1mp639wZzyabpTQis9E6H5Za CcPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sDoUJAYn0yIc6w7KX8ASaLZmx5h0oxVG9cXFpdPESQk=; b=Z9sl6D+Owu5iNsxyPxrVJhcTJ/BeixrFfhGFZGuNdM2+ux5NIJ0WQzW54Jpls3CwcK yqXYENp8G+2WisVLYBbE0SL3LtgDKVgsR8AWzFRloGhIUt79DQ1vuoVV5iLgiu7+igkZ cOmKG6JyJ1hbWW/uBlvkKdxKKIQDgMVrL9F7705b9OvY4A+MR5o1P9Nlb6MKxuJu4Kiw XanxG+sJvwNVfR55ZTkUrUIVuVFGPBFciglyA06a/mbfj+R0mKp7fVmbBcJp/Bl0a1Cg Q0xAysovTJvA1PTe1/K3b3+/w4yGv8qvW4WBrFUiIpwnz2i0l3E1w8Xp01iM2av+vaxJ xSgw== X-Gm-Message-State: AOAM532c382f4et/G5rPpqukx/H3ebmUFjcU+iTjFqBSyCQWY1S/bvQ3 XTceVAO0AoPABGLupOMEdrxFLkuYdRc31BkZ X-Google-Smtp-Source: ABdhPJyVdXIGA/r1MnlzZwZmfkm6z1/ydsWqbBpTdN+Fq552nbkHtH25+XxVp0Nm08bbclC665aMgA== X-Received: by 2002:a5d:4dd0:: with SMTP id f16mr668000wru.192.1622735962170; Thu, 03 Jun 2021 08:59:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/45] softfpu: Add float_round_to_odd_inf Date: Thu, 3 Jun 2021 16:58:39 +0100 Message-Id: <20210603155904.26021-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson For Arm BFDOT and BFMMLA, we need a version of round-to-odd that overflows to infinity, instead of the max normal number. Cc: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/fpu/softfloat-types.h | 4 +++- fpu/softfloat-parts.c.inc | 6 ++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8a3f20fae9e..3b757c3d6a6 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -134,8 +134,10 @@ typedef enum __attribute__((__packed__)) { float_round_up =3D 2, float_round_to_zero =3D 3, float_round_ties_away =3D 4, - /* Not an IEEE rounding mode: round to the closest odd mantissa value = */ + /* Not an IEEE rounding mode: round to closest odd, overflow to max */ float_round_to_odd =3D 5, + /* Not an IEEE rounding mode: round to closest odd, overflow to inf */ + float_round_to_odd_inf =3D 6, } FloatRoundMode; =20 /* diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index a897a5a743d..7f69da1d8fa 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -176,13 +176,12 @@ static void partsN(uncanon)(FloatPartsN *p, float_sta= tus *s, g_assert_not_reached(); } =20 + overflow_norm =3D false; switch (s->float_rounding_mode) { case float_round_nearest_even: - overflow_norm =3D false; inc =3D ((p->frac_lo & roundeven_mask) !=3D frac_lsbm1 ? frac_lsbm= 1 : 0); break; case float_round_ties_away: - overflow_norm =3D false; inc =3D frac_lsbm1; break; case float_round_to_zero: @@ -199,6 +198,8 @@ static void partsN(uncanon)(FloatPartsN *p, float_statu= s *s, break; case float_round_to_odd: overflow_norm =3D true; + /* fall through */ + case float_round_to_odd_inf: inc =3D p->frac_lo & frac_lsb ? 0 : round_mask; break; default: @@ -259,6 +260,7 @@ static void partsN(uncanon)(FloatPartsN *p, float_statu= s *s, ? frac_lsbm1 : 0); break; case float_round_to_odd: + case float_round_to_odd_inf: inc =3D p->frac_lo & frac_lsb ? 0 : round_mask; break; default: --=20 2.20.1 From nobody Thu May 2 09:20:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737547; cv=none; d=zohomail.com; s=zohoarc; b=ghRS3IRhEtKhWy3ZRGXq3thmUwEH6V7vJY+pMeeSIp/gBcZggZ2wlFZVmlw1xHAOC9sXIpD0FDfLswruMZyPPkLv6tj+dpMVYVOW5lXYTF9CqwDvm6zIdzwUmV31/R8cWXinfD48nMSl/DMeCML1BSW81MEb4hNLBmmNBsxIVxM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737547; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0+RSwT/M706THEo6qExc/FLr5Pmb3+OcBuvoHO4Dy10=; b=FqrHyjNzjq4qem/qxkA6tSyrD7EDNdK4w6feoPRrVvAkXcqh21X/vMWR5ZNq/Ye5t1xeSE09U4bI0u1W2YuH2dMVipbs9cvoGO+rZWSKF08jLHSnwMeVVhCc7q27AGOL4Cm5PyNK2CvRQz792PaUMVF1F3FYV5d75rQH78h+tLQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737547171461.97477565857776; Thu, 3 Jun 2021 09:25:47 -0700 (PDT) Received: from localhost ([::1]:47224 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loqAE-0000SW-2q for importer2@patchew.org; Thu, 03 Jun 2021 12:25:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35696) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopkl-0000Nn-5b for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:27 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:39452) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkj-00072T-3D for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:26 -0400 Received: by mail-wm1-x329.google.com with SMTP id l18-20020a1ced120000b029014c1adff1edso6212312wmh.4 for ; Thu, 03 Jun 2021 08:59:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0+RSwT/M706THEo6qExc/FLr5Pmb3+OcBuvoHO4Dy10=; b=p49SvcRtaVHwE+SkRUyHOS+Zhvc/8RejrLFWYx3KIVw5fNuyTU9jyVP6h89vWcqwx6 gsmsnNYSV+TkACv5jssbENHbSLlHzGcAmGlmsNUQdWkNISbrSKhcUC6w8lEsA5f2KC9g K+51nW87DBLqOkkt4GOfLa/p8xfFbUKZjX2u/6NEQHOwIqkMHs9mdqbbemzpwJQUCpO4 bluikou2OaCcnnpE845oVN0ww25bT3IQw+tGq/Fix0bRe/o6Ku/Wla4mAd6k/o0rcWT8 GydhryddsgCiqw6cxfNr6lLWerKsQNAb+waRqNMefK0JGihwk3mTQppXgk8b3UvIcLeD nCpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0+RSwT/M706THEo6qExc/FLr5Pmb3+OcBuvoHO4Dy10=; b=jAW32vq6pio9y/8Ptba+MZKQwzOoJzsLe3hPD/eQr4TkxAahM5ngA/iu6xC2lPr3b1 ru/Ts01i4BDytUjCUmlhnlWKTLUp6QOA76DM4SimKFNhA4um6fx/f89ZY8ruCpJ1F7mE 8jpN2xvS5bYwnKv1D+sjKIM0DYmZOPAxTRFXw01RzZCSXOxREg4YP2lcWC1gP78m/GxA gdfh6vTrUn65L+qolQVCXa5+CTec0R4iWLrYx4UeDkPI29jTeYOf3bW5PN6/zE0F+bKZ oSfCLmYbDof4X7DPMj4nMmLhBOYGGQ4dsNIEpSIk/Ps1vFXLPTJDwIKI+ltDV176GiOj Aj7A== X-Gm-Message-State: AOAM5309walrDhne1vHT2tBrXLGuTHcevDIukiryABTDnAGtCfK14N2i pbWHF8xzNWxHrpZSsyG2/DxQCXLkClKox/qB X-Google-Smtp-Source: ABdhPJzewl+e4N4RCHDtRDBclkizM8BwtZble+rxQp2Ux68zm66yZbhpsufBHR3nDKXTRAHgIuN28A== X-Received: by 2002:a1c:a516:: with SMTP id o22mr11053728wme.136.1622735963620; Thu, 03 Jun 2021 08:59:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/45] target/arm: Implement bfloat16 dot product (vector) Date: Thu, 3 Jun 2021 16:58:40 +0100 Message-Id: <20210603155904.26021-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is BFDOT for both AArch64 AdvSIMD and SVE, and VDOT.BF16 for AArch32 NEON. Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-7-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.h | 3 +++ target/arm/neon-shared.decode | 2 ++ target/arm/sve.decode | 3 +++ target/arm/translate-a64.c | 20 ++++++++++++++++++ target/arm/translate-neon.c | 9 ++++++++ target/arm/translate-sve.c | 12 +++++++++++ target/arm/vec_helper.c | 40 +++++++++++++++++++++++++++++++++++ 7 files changed, 89 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index 8b4b7d92f36..de2f5331dcc 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1002,6 +1002,9 @@ DEF_HELPER_FLAGS_5(gvec_ummla_b, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_usmmla_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_bfdot, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode index cc9f4cdd85b..31a0839bbb0 100644 --- a/target/arm/neon-shared.decode +++ b/target/arm/neon-shared.decode @@ -52,6 +52,8 @@ VUDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 1 = .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp VUSDOT 1111 110 01 . 10 .... .... 1101 . q:1 . 0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VDOT_b16 1111 110 00 . 00 .... .... 1101 . q:1 . 0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp =20 # VFM[AS]L VFML 1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 18d1a0eecc5..a7429b293fe 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1625,6 +1625,9 @@ FMLALT_zzzw 01100100 10 1 ..... 10 0 00 1 ..... .= .... @rda_rn_rm_e0 FMLSLB_zzzw 01100100 10 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_e0 FMLSLT_zzzw 01100100 10 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_e0 =20 +### SVE2 floating-point bfloat16 dot-product +BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_e0 + ### SVE2 floating-point multiply-add long (indexed) FMLALB_zzxw 01100100 10 1 ..... 0100.0 ..... ..... @rrxr_3a esz=3D2 FMLALT_zzxw 01100100 10 1 ..... 0100.1 ..... ..... @rrxr_3a esz=3D2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0f15fa42fc3..3c36de3df20 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -12235,6 +12235,16 @@ static void disas_simd_three_reg_same_extra(DisasC= ontext *s, uint32_t insn) } feature =3D dc_isar_feature(aa64_fcma, s); break; + case 0x1f: /* BFDOT */ + switch (size) { + case 1: + feature =3D dc_isar_feature(aa64_bf16, s); + break; + default: + unallocated_encoding(s); + return; + } + break; default: unallocated_encoding(s); return; @@ -12318,6 +12328,16 @@ static void disas_simd_three_reg_same_extra(DisasC= ontext *s, uint32_t insn) } return; =20 + case 0xf: /* BFDOT */ + switch (size) { + case 1: + gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, gen_helper_gvec_b= fdot); + break; + default: + g_assert_not_reached(); + } + return; + default: g_assert_not_reached(); } diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 6d94229c691..9460857b2ad 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -296,6 +296,15 @@ static bool trans_VUSDOT(DisasContext *s, arg_VUSDOT *= a) gen_helper_gvec_usdot_b); } =20 +static bool trans_VDOT_b16(DisasContext *s, arg_VDOT_b16 *a) +{ + if (!dc_isar_feature(aa32_bf16, s)) { + return false; + } + return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0, + gen_helper_gvec_bfdot); +} + static bool trans_VFML(DisasContext *s, arg_VFML *a) { int opr_sz; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index fb692a18351..ed290827ad2 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -8653,3 +8653,15 @@ static bool trans_UMMLA(DisasContext *s, arg_rrrr_es= z *a) { return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_ummla_b, 0); } + +static bool trans_BFDOT_zzzz(DisasContext *s, arg_rrrr_esz *a) +{ + if (!dc_isar_feature(aa64_sve_bf16, s)) { + return false; + } + if (sve_access_check(s)) { + gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot, + a->rd, a->rn, a->rm, a->ra, 0); + } + return true; +} diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index e84b438340e..7eefcd06eae 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2412,3 +2412,43 @@ static void do_mmla_b(void *vd, void *vn, void *vm, = void *va, uint32_t desc, DO_MMLA_B(gvec_smmla_b, do_smmla_b) DO_MMLA_B(gvec_ummla_b, do_ummla_b) DO_MMLA_B(gvec_usmmla_b, do_usmmla_b) + +/* + * BFloat16 Dot Product + */ + +static float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2) +{ + /* FPCR is ignored for BFDOT and BFMMLA. */ + float_status bf_status =3D { + .tininess_before_rounding =3D float_tininess_before_rounding, + .float_rounding_mode =3D float_round_to_odd_inf, + .flush_to_zero =3D true, + .flush_inputs_to_zero =3D true, + .default_nan_mode =3D true, + }; + float32 t1, t2; + + /* + * Extract each BFloat16 from the element pair, and shift + * them such that they become float32. + */ + t1 =3D float32_mul(e1 << 16, e2 << 16, &bf_status); + t2 =3D float32_mul(e1 & 0xffff0000u, e2 & 0xffff0000u, &bf_status); + t1 =3D float32_add(t1, t2, &bf_status); + t1 =3D float32_add(sum, t1, &bf_status); + + return t1; +} + +void HELPER(gvec_bfdot)(void *vd, void *vn, void *vm, void *va, uint32_t d= esc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc); + float32 *d =3D vd, *a =3D va; + uint32_t *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 4; ++i) { + d[i] =3D bfdotadd(a[i], n[i], m[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.h | 2 ++ target/arm/neon-shared.decode | 2 ++ target/arm/sve.decode | 3 +++ target/arm/translate-a64.c | 41 +++++++++++++++++++++++++++-------- target/arm/translate-neon.c | 9 ++++++++ target/arm/translate-sve.c | 12 ++++++++++ target/arm/vec_helper.c | 20 +++++++++++++++++ 7 files changed, 80 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index de2f5331dcc..376c1cef0f6 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1004,6 +1004,8 @@ DEF_HELPER_FLAGS_5(gvec_usmmla_b, TCG_CALL_NO_RWG, =20 DEF_HELPER_FLAGS_5(gvec_bfdot, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_bfdot_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) =20 #ifdef TARGET_AARCH64 #include "helper-a64.h" diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode index 31a0839bbb0..fa3cf14e3a6 100644 --- a/target/arm/neon-shared.decode +++ b/target/arm/neon-shared.decode @@ -81,6 +81,8 @@ VUSDOT_scalar 1111 1110 1 . 00 .... .... 1101 . q:1 inde= x:1 0 vm:4 \ vn=3D%vn_dp vd=3D%vd_dp VSUDOT_scalar 1111 1110 1 . 00 .... .... 1101 . q:1 index:1 1 vm:4 \ vn=3D%vn_dp vd=3D%vd_dp +VDOT_b16_scal 1111 1110 0 . 00 .... .... 1101 . q:1 index:1 0 vm:4 \ + vn=3D%vn_dp vd=3D%vd_dp =20 %vfml_scalar_q0_rm 0:3 5:1 %vfml_scalar_q1_index 5:1 3:1 diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a7429b293fe..51f87e8937e 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1633,3 +1633,6 @@ FMLALB_zzxw 01100100 10 1 ..... 0100.0 ..... ....= . @rrxr_3a esz=3D2 FMLALT_zzxw 01100100 10 1 ..... 0100.1 ..... ..... @rrxr_3a esz=3D2 FMLSLB_zzxw 01100100 10 1 ..... 0110.0 ..... ..... @rrxr_3a esz=3D2 FMLSLT_zzxw 01100100 10 1 ..... 0110.1 ..... ..... @rrxr_3a esz=3D2 + +### SVE2 floating-point bfloat16 dot-product (indexed) +BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=3D2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3c36de3df20..71de75e568b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13449,8 +13449,22 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) return; } break; - case 0x0f: /* SUDOT, USDOT */ - if (is_scalar || (size & 1) || !dc_isar_feature(aa64_i8mm, s)) { + case 0x0f: + switch (size) { + case 0: /* SUDOT */ + case 2: /* USDOT */ + if (is_scalar || !dc_isar_feature(aa64_i8mm, s)) { + unallocated_encoding(s); + return; + } + break; + case 1: /* BFDOT */ + if (is_scalar || !dc_isar_feature(aa64_bf16, s)) { + unallocated_encoding(s); + return; + } + break; + default: unallocated_encoding(s); return; } @@ -13570,13 +13584,22 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b); return; - case 0x0f: /* SUDOT, USDOT */ - gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index, - extract32(insn, 23, 1) - ? gen_helper_gvec_usdot_idx_b - : gen_helper_gvec_sudot_idx_b); - return; - + case 0x0f: + switch (extract32(insn, 22, 2)) { + case 0: /* SUDOT */ + gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index, + gen_helper_gvec_sudot_idx_b); + return; + case 1: /* BFDOT */ + gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index, + gen_helper_gvec_bfdot_idx); + return; + case 2: /* USDOT */ + gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index, + gen_helper_gvec_usdot_idx_b); + return; + } + g_assert_not_reached(); case 0x11: /* FCMLA #0 */ case 0x13: /* FCMLA #90 */ case 0x15: /* FCMLA #180 */ diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 9460857b2ad..8099767792b 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -390,6 +390,15 @@ static bool trans_VSUDOT_scalar(DisasContext *s, arg_V= SUDOT_scalar *a) gen_helper_gvec_sudot_idx_b); } =20 +static bool trans_VDOT_b16_scal(DisasContext *s, arg_VDOT_b16_scal *a) +{ + if (!dc_isar_feature(aa32_bf16, s)) { + return false; + } + return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index, + gen_helper_gvec_bfdot_idx); +} + static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a) { int opr_sz; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index ed290827ad2..6f020306357 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -8665,3 +8665,15 @@ static bool trans_BFDOT_zzzz(DisasContext *s, arg_rr= rr_esz *a) } return true; } + +static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a) +{ + if (!dc_isar_feature(aa64_sve_bf16, s)) { + return false; + } + if (sve_access_check(s)) { + gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot_idx, + a->rd, a->rn, a->rm, a->ra, a->index); + } + return true; +} diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 7eefcd06eae..74a497f38ca 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2452,3 +2452,23 @@ void HELPER(gvec_bfdot)(void *vd, void *vn, void *vm= , void *va, uint32_t desc) } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +void HELPER(gvec_bfdot_idx)(void *vd, void *vn, void *vm, + void *va, uint32_t desc) +{ + intptr_t i, j, opr_sz =3D simd_oprsz(desc); + intptr_t index =3D simd_data(desc); + intptr_t elements =3D opr_sz / 4; + intptr_t eltspersegment =3D MIN(16 / 4, elements); + float32 *d =3D vd, *a =3D va; + uint32_t *n =3D vn, *m =3D vm; + + for (i =3D 0; i < elements; i +=3D eltspersegment) { + uint32_t m_idx =3D m[i + H4(index)]; + + for (j =3D i; j < i + eltspersegment; j++) { + d[j] =3D bfdotadd(a[j], n[j], m_idx); + } + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736842; cv=none; d=zohomail.com; s=zohoarc; b=Z3akq5s8eqPm6bsXkFBHg+VF0UYYbhKMRVZQvQdISNNoKl58fvvhXjSYRra+LXG4/9laOW8RtN4bYYFLxDevTp6kwMoA/knO6dPCNnEWSWzmnaMabBhIXE5/71X7an5WvhWHVj+R8ZS3b8bPW4qEqPivGeLpvZWHuV87Datr/uo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736842; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Aj1Km1MiMk9Lh1J6X4cFHMg3xXpJIdcMFaRVOA0WAbw=; b=nKIKci65m4T9JoYhNsq8YXEu0O6ujBGlRFRtCqBkjKiu+t1YLiURe8A1QOtgnAeUeJ GNuywaGSpOmtbarfLGiOgAAx9Se9XNhwk/g7TIxvVDtXFH+780ooja7bqNdmI7vzBEkv YY8YDqiud+o70za2ONoPrQK1WtGkcxXH1l6LnZTwrfQr1fvAJCFVnYaQcMZf4L9ii9N7 0tM0bTPnv/8/zvIPOEHOzxt+x9K3US5lObD5Ugzge1dWZgeE0wp+lO6ddtcTk7HiUprW wd/aVZb6OBk9rmHZIPKiGp2tlo8xy/asrsltJyf5Ny7E6nQ5X+XZisxN/UOwHe+Nu4OO 3sCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Aj1Km1MiMk9Lh1J6X4cFHMg3xXpJIdcMFaRVOA0WAbw=; b=WSFSco8C12uKtLdNXDlJ5t2OSIlH+jx4dRAKJe9ccnrNx+DK5ZOTnl/Rnvdz3EfBOV cLyawlQwfKbramxzsHri4wELoH6YAS0DU3DmzPtzmSBaE76eo6tNw/qyNt0Cf8iadvFh zfu3zzzn+odpw2mieuoMiRmyvb4L1cqBGhoysA5ean/gmZx1wZPrqLM3xZUF0AvfoyLn O0o/v6grZU626dgq3Ih2dkoefwOQ6VNS1lA+QVqr1SE9zfsoJ6cnWU/KTYtjOP/X7enh snbbxT8YrbrPeGDwQG9xKIWRe6ojcmay5XoQBAOVJFhZw53xsNMwFlYumqIhOht75TUi 7zmA== X-Gm-Message-State: AOAM533zIPBRzK98f3OGMtiJDNAvG84fitEV8HHunsD79RkaMhWMLrIb iiIg0fdnrYcpNW/Qa3mT9SZqzlael/wKtD0h X-Google-Smtp-Source: ABdhPJyAqHSoAH0mVGthYRMmmuV+VafcEIwyjhoL386GaSx7pkK1UL9yKF3Qq+fU2/w2Fl0rjC+qRw== X-Received: by 2002:adf:f382:: with SMTP id m2mr654722wro.394.1622735966523; Thu, 03 Jun 2021 08:59:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/45] target/arm: Implement bfloat16 matrix multiply accumulate Date: Thu, 3 Jun 2021 16:58:42 +0100 Message-Id: <20210603155904.26021-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is BFMMLA for both AArch64 AdvSIMD and SVE, and VMMLA.BF16 for AArch32 NEON. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 3 +++ target/arm/neon-shared.decode | 2 ++ target/arm/sve.decode | 6 +++-- target/arm/translate-a64.c | 10 +++++++++ target/arm/translate-neon.c | 9 ++++++++ target/arm/translate-sve.c | 12 ++++++++++ target/arm/vec_helper.c | 42 ++++++++++++++++++++++++++++++++++- 7 files changed, 81 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 376c1cef0f6..af75d7f25f2 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1007,6 +1007,9 @@ DEF_HELPER_FLAGS_5(gvec_bfdot, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_bfdot_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_bfmmla, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode index fa3cf14e3a6..4e0a25d27c1 100644 --- a/target/arm/neon-shared.decode +++ b/target/arm/neon-shared.decode @@ -67,6 +67,8 @@ VUMMLA 1111 1100 0.10 .... .... 1100 .1.1 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp VUSMMLA 1111 1100 1.10 .... .... 1100 .1.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VMMLA_b16 1111 1100 0.00 .... .... 1100 .1.0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp =20 VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \ vn=3D%vn_dp vd=3D%vd_dp size=3D1 diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 51f87e8937e..6c17898deed 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1568,8 +1568,10 @@ SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:= 5 rd:5 ra=3D%reg_movprfx USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm =20 ### SVE2 floating point matrix multiply accumulate - -FMMLA 01100100 .. 1 ..... 111001 ..... ..... @rda_rn_rm +{ + BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0 + FMMLA 01100100 .. 1 ..... 111 001 ..... ..... @rda_rn_rm +} =20 ### SVE2 Memory Gather Load Group =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 71de75e568b..9ce2f5a7d43 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -12235,6 +12235,13 @@ static void disas_simd_three_reg_same_extra(DisasC= ontext *s, uint32_t insn) } feature =3D dc_isar_feature(aa64_fcma, s); break; + case 0x1d: /* BFMMLA */ + if (size !=3D MO_16 || !is_q) { + unallocated_encoding(s); + return; + } + feature =3D dc_isar_feature(aa64_bf16, s); + break; case 0x1f: /* BFDOT */ switch (size) { case 1: @@ -12328,6 +12335,9 @@ static void disas_simd_three_reg_same_extra(DisasCo= ntext *s, uint32_t insn) } return; =20 + case 0xd: /* BFMMLA */ + gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, gen_helper_gvec_bfmml= a); + return; case 0xf: /* BFDOT */ switch (size) { case 1: diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 8099767792b..9d227a1e13d 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -4126,3 +4126,12 @@ static bool trans_VUSMMLA(DisasContext *s, arg_VUSMM= LA *a) return do_neon_ddda(s, 7, a->vd, a->vn, a->vm, 0, gen_helper_gvec_usmmla_b); } + +static bool trans_VMMLA_b16(DisasContext *s, arg_VMMLA_b16 *a) +{ + if (!dc_isar_feature(aa32_bf16, s)) { + return false; + } + return do_neon_ddda(s, 7, a->vd, a->vn, a->vm, 0, + gen_helper_gvec_bfmmla); +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 6f020306357..4f575dc3343 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -8677,3 +8677,15 @@ static bool trans_BFDOT_zzxz(DisasContext *s, arg_rr= xr_esz *a) } return true; } + +static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a) +{ + if (!dc_isar_feature(aa64_sve_bf16, s)) { + return false; + } + if (sve_access_check(s)) { + gen_gvec_ool_zzzz(s, gen_helper_gvec_bfmmla, + a->rd, a->rn, a->rm, a->ra, 0); + } + return true; +} diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 74a497f38ca..27e9bdd3299 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2385,7 +2385,7 @@ static void do_mmla_b(void *vd, void *vn, void *vm, v= oid *va, uint32_t desc, * Process the entire segment at once, writing back the * results only after we've consumed all of the inputs. * - * Key to indicies by column: + * Key to indices by column: * i j i j */ sum0 =3D a[H4(0 + 0)]; @@ -2472,3 +2472,43 @@ void HELPER(gvec_bfdot_idx)(void *vd, void *vn, void= *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +void HELPER(gvec_bfmmla)(void *vd, void *vn, void *vm, void *va, uint32_t = desc) +{ + intptr_t s, opr_sz =3D simd_oprsz(desc); + float32 *d =3D vd, *a =3D va; + uint32_t *n =3D vn, *m =3D vm; + + for (s =3D 0; s < opr_sz / 4; s +=3D 4) { + float32 sum00, sum01, sum10, sum11; + + /* + * Process the entire segment at once, writing back the + * results only after we've consumed all of the inputs. + * + * Key to indicies by column: + * i j i k j k + */ + sum00 =3D a[s + H4(0 + 0)]; + sum00 =3D bfdotadd(sum00, n[s + H4(0 + 0)], m[s + H4(0 + 0)]); + sum00 =3D bfdotadd(sum00, n[s + H4(0 + 1)], m[s + H4(0 + 1)]); + + sum01 =3D a[s + H4(0 + 1)]; + sum01 =3D bfdotadd(sum01, n[s + H4(0 + 0)], m[s + H4(2 + 0)]); + sum01 =3D bfdotadd(sum01, n[s + H4(0 + 1)], m[s + H4(2 + 1)]); + + sum10 =3D a[s + H4(2 + 0)]; + sum10 =3D bfdotadd(sum10, n[s + H4(2 + 0)], m[s + H4(0 + 0)]); + sum10 =3D bfdotadd(sum10, n[s + H4(2 + 1)], m[s + H4(0 + 1)]); + + sum11 =3D a[s + H4(2 + 1)]; + sum11 =3D bfdotadd(sum11, n[s + H4(2 + 0)], m[s + H4(2 + 0)]); + sum11 =3D bfdotadd(sum11, n[s + H4(2 + 1)], m[s + H4(2 + 1)]); + + d[s + H4(0 + 0)] =3D sum00; + d[s + H4(0 + 1)] =3D sum01; + d[s + H4(2 + 0)] =3D sum10; + d[s + H4(2 + 1)] =3D sum11; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737655; cv=none; d=zohomail.com; s=zohoarc; b=mC6OkXGS/h0CW8rWZ38RyxbA+tmKBzfeWorluHjSt5IfoqPvm9gWHLCxjuQQhgXFXASAzWNtJFzj/Ym/1KFeBzt/EgrgPEN+E2Tf32+UV59+SJLIGUZmYPy8lYNDr1cwTsxv19sGOpbX6WNe2M5re4ujALoQ7T4P+2NMrJsT1hw= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eUx6yMvYeVEyQOg6iQGEWlrRdiPFSRwrc8Kv/X8CupI=; b=Zjjt4sINv+TCixbKtCQL01ocmRAZ+OVRXaQVsjgchVOJlVMQChtjs47SlTSMlcwIQ8 EHHr9KW89VzaqvzLt+ZoxJt0ui6qGFS2yVrNOOUf3xRtN58Mhr5MPFSqkkjRug5/ROzM G/jGKZhL96sWP4hWherF9alZl+I96kFSHqZE2csEBnJv5T1gAWLl2RaGwqTLzrxqcoEy xHHxs2VQ4WABZEzfzFkOJRzu9jdD9jODzoXct1Jc0l7SMFWUVyLn37Jj0QfwAJr+MPMh LUh1H4JVdfc0FnEWbefz6QnPCDbvP41Hua8UN8DH/Kcomdc1zpQc23nsQhGjKXCVvhB0 RB0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eUx6yMvYeVEyQOg6iQGEWlrRdiPFSRwrc8Kv/X8CupI=; b=lH1MUBxIQbcQ83YBqBy3m0hMnUh0/d3/bZ7HtZhq69PV0U+6OJKHeWTPFvBKfQaIAz P0iaRME2gvEsPMPgt3V4nJf9e7RmshBZ37qk6tDA16Js/AbB6nZrVti886cExThfUDzv S/oH/y5HlASjhbnyEwEUjhtvXRFQduwqKw1hc2LkKiQDmeVyn/f+rE7l7f5hhLLTvf6E RS09a56h7KZDJan8OtebyKc6LasKg681lPJQg+VTyhfMXRLxvGdcdS9j+E+0yqaONYOu B5vG5f7rlT2ydvjEW0UFQJdAPiZtg60J1Z9bOWiC8NqJNK2VE5/DbXGDVD7Fl4F+0Sj3 os6A== X-Gm-Message-State: AOAM533NWLPmQ9NUStU5F4n5CyJvqkaqlwPINMDjss/2tyeeP5QGmw8B fVSakdAHQ82qnVEntWbDevxZ299US7DCW1Ni X-Google-Smtp-Source: ABdhPJy7iXnZNi3/d8JXwn7UN0RoP/toymAVYeZn7EqI+vZRL+nL1Eca+UaL3pMUgCKreRzOJXuCmg== X-Received: by 2002:a1c:9a84:: with SMTP id c126mr37435372wme.160.1622735967628; Thu, 03 Jun 2021 08:59:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/45] target/arm: Implement bfloat widening fma (vector) Date: Thu, 3 Jun 2021 16:58:43 +0100 Message-Id: <20210603155904.26021-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is BFMLAL{B,T} for both AArch64 AdvSIMD and SVE, and VFMA{B,T}.BF16 for AArch32 NEON. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 3 +++ target/arm/neon-shared.decode | 3 +++ target/arm/sve.decode | 3 +++ target/arm/translate-a64.c | 13 +++++++++---- target/arm/translate-neon.c | 9 +++++++++ target/arm/translate-sve.c | 30 ++++++++++++++++++++++++++++++ target/arm/vec_helper.c | 16 ++++++++++++++++ 7 files changed, 73 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index af75d7f25f2..36b3c9dd2d0 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1010,6 +1010,9 @@ DEF_HELPER_FLAGS_5(gvec_bfdot_idx, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_bfmmla, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode index 4e0a25d27c1..b61addd98b7 100644 --- a/target/arm/neon-shared.decode +++ b/target/arm/neon-shared.decode @@ -70,6 +70,9 @@ VUSMMLA 1111 1100 1.10 .... .... 1100 .1.0 .... \ VMMLA_b16 1111 1100 0.00 .... .... 1100 .1.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp =20 +VFMA_b16 1111 110 0 0.11 .... .... 1000 . q:1 . 1 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp + VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \ vn=3D%vn_dp vd=3D%vd_dp size=3D1 VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 6c17898deed..5281164eeae 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1627,6 +1627,9 @@ FMLALT_zzzw 01100100 10 1 ..... 10 0 00 1 ..... .= .... @rda_rn_rm_e0 FMLSLB_zzzw 01100100 10 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_e0 FMLSLT_zzzw 01100100 10 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_e0 =20 +BFMLALB_zzzw 01100100 11 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_e0 +BFMLALT_zzzw 01100100 11 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_e0 + ### SVE2 floating-point bfloat16 dot-product BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_e0 =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9ce2f5a7d43..8dcb15ac0f7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -12242,9 +12242,10 @@ static void disas_simd_three_reg_same_extra(DisasC= ontext *s, uint32_t insn) } feature =3D dc_isar_feature(aa64_bf16, s); break; - case 0x1f: /* BFDOT */ + case 0x1f: switch (size) { - case 1: + case 1: /* BFDOT */ + case 3: /* BFMLAL{B,T} */ feature =3D dc_isar_feature(aa64_bf16, s); break; default: @@ -12338,11 +12339,15 @@ static void disas_simd_three_reg_same_extra(Disas= Context *s, uint32_t insn) case 0xd: /* BFMMLA */ gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, gen_helper_gvec_bfmml= a); return; - case 0xf: /* BFDOT */ + case 0xf: switch (size) { - case 1: + case 1: /* BFDOT */ gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, gen_helper_gvec_b= fdot); break; + case 3: /* BFMLAL{B,T} */ + gen_gvec_op4_fpst(s, 1, rd, rn, rm, rd, false, is_q, + gen_helper_gvec_bfmlal); + break; default: g_assert_not_reached(); } diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 9d227a1e13d..4d0c2494dc5 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -4135,3 +4135,12 @@ static bool trans_VMMLA_b16(DisasContext *s, arg_VMM= LA_b16 *a) return do_neon_ddda(s, 7, a->vd, a->vn, a->vm, 0, gen_helper_gvec_bfmmla); } + +static bool trans_VFMA_b16(DisasContext *s, arg_VFMA_b16 *a) +{ + if (!dc_isar_feature(aa32_bf16, s)) { + return false; + } + return do_neon_ddda_fpst(s, 7, a->vd, a->vn, a->vm, a->q, FPST_STD, + gen_helper_gvec_bfmlal); +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 4f575dc3343..ba8f5d7b7db 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -8689,3 +8689,33 @@ static bool trans_BFMMLA(DisasContext *s, arg_rrrr_e= sz *a) } return true; } + +static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) +{ + if (!dc_isar_feature(aa64_sve_bf16, s)) { + return false; + } + if (sve_access_check(s)) { + TCGv_ptr status =3D fpstatus_ptr(FPST_FPCR); + unsigned vsz =3D vec_full_reg_size(s); + + tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + vec_full_reg_offset(s, a->ra), + status, vsz, vsz, sel, + gen_helper_gvec_bfmlal); + tcg_temp_free_ptr(status); + } + return true; +} + +static bool trans_BFMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a) +{ + return do_BFMLAL_zzzw(s, a, false); +} + +static bool trans_BFMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a) +{ + return do_BFMLAL_zzzw(s, a, true); +} diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 27e9bdd3299..d82736b5e66 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2512,3 +2512,19 @@ void HELPER(gvec_bfmmla)(void *vd, void *vn, void *v= m, void *va, uint32_t desc) } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +void HELPER(gvec_bfmlal)(void *vd, void *vn, void *vm, void *va, + void *stat, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc); + intptr_t sel =3D simd_data(desc); + float32 *d =3D vd, *a =3D va; + bfloat16 *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 4; ++i) { + float32 nn =3D n[H2(i * 2 + sel)] << 16; + float32 mm =3D m[H2(i * 2 + sel)] << 16; + d[H4(i)] =3D float32_muladd(nn, mm, a[H4(i)], 0, stat); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=l2eo90OEtfiRDcQjeP80CCeDmi47iLNOmpTkUiGTR+k=; b=hRTDgapIuEUe38o/TGPnnBhqOgD67myNenDD1MTgZHr71LE38y6EyaiJlTtrrKbTi5 X1S8rVU0QK3HXIoifU6e2u7YK3Xr/wTLbnKe7puiv9JURCbv4bCTVC2LmBynpAH/k7x6 heEo6euCikqj5kvwoeoLZDlWufjZJHv079lrEVJbmM9Oa810QGY37pd8NbYILc0ZZm4b oEKF38Ls3uM1TnZKm5siN3O3uFIEINJTV76wdFabVSFMrl8zh/1BjDK4K85UH0sPvmtB S9kH9aQvv4gjdZh3WC5idAPOp2WIGTgb8cP5cz/+YXIoGPqj0YPvea1KJSAs430IV3dl dGBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l2eo90OEtfiRDcQjeP80CCeDmi47iLNOmpTkUiGTR+k=; b=ad/C/f2xWIoZi/Jzpm1M4Bm3rYj+pie+p6fa6GdjFG/8lj4GAM1m1wz/ffHBCCmOVV P27kWpy098BzEjmkORtANFNos1bhABNTtksJQndDYXeDZo7shOWb4SodpiTe/qdc/QKP yXzeevkI3WKR+f/o6e/bop1YYKIyDUy+zwF6dHUpmlj6Xq/HBfdnilxy0OvHAkQWFiGW tb7umtGBYMPik41xYGQIsL1DLDzMFYiD/9NfTvvLtfO9fygOw0S4PyIyBai9SZA0sDpD M9+xsexg3CDsV6GE3JKEq2MT+QpCYwum63CAk3FUb1OZX0hYXknY+kF3DUBUGhZ0pK1y WAMg== X-Gm-Message-State: AOAM533LlU/UQ6vbSsW/YoYHMV3wwLOtjbn8G6VAo3HcoPZIOhr6qmLr C3kDtirAO0coOcu+46xdnc/ZE6y0ohE+MgvD X-Google-Smtp-Source: ABdhPJyoB2qEDVHQHhtqvkGNGHcXbBRbB/kJtjgFV5whxZUHxByINWw98c91niKfqqo0tvA+I2ybXQ== X-Received: by 2002:a05:600c:3647:: with SMTP id y7mr10936209wmq.149.1622735969065; Thu, 03 Jun 2021 08:59:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/45] target/arm: Implement bfloat widening fma (indexed) Date: Thu, 3 Jun 2021 16:58:44 +0100 Message-Id: <20210603155904.26021-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is BFMLAL{B,T} for both AArch64 AdvSIMD and SVE, and VFMA{B,T}.BF16 for AArch32 NEON. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 2 ++ target/arm/neon-shared.decode | 2 ++ target/arm/sve.decode | 2 ++ target/arm/translate-a64.c | 15 ++++++++++++++- target/arm/translate-neon.c | 10 ++++++++++ target/arm/translate-sve.c | 30 ++++++++++++++++++++++++++++++ target/arm/vec_helper.c | 22 ++++++++++++++++++++++ 7 files changed, 82 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 36b3c9dd2d0..dc6eb96d439 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1012,6 +1012,8 @@ DEF_HELPER_FLAGS_5(gvec_bfmmla, TCG_CALL_NO_RWG, =20 DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) =20 #ifdef TARGET_AARCH64 #include "helper-a64.h" diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode index b61addd98b7..df80e6ebf66 100644 --- a/target/arm/neon-shared.decode +++ b/target/arm/neon-shared.decode @@ -95,3 +95,5 @@ VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 0 . 1= index:1 ... \ rm=3D%vfml_scalar_q0_rm vn=3D%vn_sp vd=3D%vd_dp q=3D0 VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 1 . 1 . rm:3 \ index=3D%vfml_scalar_q1_index vn=3D%vn_dp vd=3D%vd_dp q=3D1 +VFMA_b16_scal 1111 1110 0.11 .... .... 1000 . q:1 . 1 . vm:3 \ + index=3D%vfml_scalar_q1_index vn=3D%vn_dp vd=3D%vd_dp diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 5281164eeae..a62c169f1a8 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1638,6 +1638,8 @@ FMLALB_zzxw 01100100 10 1 ..... 0100.0 ..... ....= . @rrxr_3a esz=3D2 FMLALT_zzxw 01100100 10 1 ..... 0100.1 ..... ..... @rrxr_3a esz=3D2 FMLSLB_zzxw 01100100 10 1 ..... 0110.0 ..... ..... @rrxr_3a esz=3D2 FMLSLT_zzxw 01100100 10 1 ..... 0110.1 ..... ..... @rrxr_3a esz=3D2 +BFMLALB_zzxw 01100100 11 1 ..... 0100.0 ..... ..... @rrxr_3a esz=3D2 +BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=3D2 =20 ### SVE2 floating-point bfloat16 dot-product (indexed) BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=3D2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8dcb15ac0f7..8713dfec174 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13472,18 +13472,27 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) unallocated_encoding(s); return; } + size =3D MO_32; break; case 1: /* BFDOT */ if (is_scalar || !dc_isar_feature(aa64_bf16, s)) { unallocated_encoding(s); return; } + size =3D MO_32; + break; + case 3: /* BFMLAL{B,T} */ + if (is_scalar || !dc_isar_feature(aa64_bf16, s)) { + unallocated_encoding(s); + return; + } + /* can't set is_fp without other incorrect size checks */ + size =3D MO_16; break; default: unallocated_encoding(s); return; } - size =3D MO_32; break; case 0x11: /* FCMLA #0 */ case 0x13: /* FCMLA #90 */ @@ -13613,6 +13622,10 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index, gen_helper_gvec_usdot_idx_b); return; + case 3: /* BFMLAL{B,T} */ + gen_gvec_op4_fpst(s, 1, rd, rn, rm, rd, 0, (index << 1) | is_q, + gen_helper_gvec_bfmlal_idx); + return; } g_assert_not_reached(); case 0x11: /* FCMLA #0 */ diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 4d0c2494dc5..633fef3bf76 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -4144,3 +4144,13 @@ static bool trans_VFMA_b16(DisasContext *s, arg_VFMA= _b16 *a) return do_neon_ddda_fpst(s, 7, a->vd, a->vn, a->vm, a->q, FPST_STD, gen_helper_gvec_bfmlal); } + +static bool trans_VFMA_b16_scal(DisasContext *s, arg_VFMA_b16_scal *a) +{ + if (!dc_isar_feature(aa32_bf16, s)) { + return false; + } + return do_neon_ddda_fpst(s, 6, a->vd, a->vn, a->vm, + (a->index << 1) | a->q, FPST_STD, + gen_helper_gvec_bfmlal_idx); +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index ba8f5d7b7db..46210eb696d 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -8719,3 +8719,33 @@ static bool trans_BFMLALT_zzzw(DisasContext *s, arg_= rrrr_esz *a) { return do_BFMLAL_zzzw(s, a, true); } + +static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) +{ + if (!dc_isar_feature(aa64_sve_bf16, s)) { + return false; + } + if (sve_access_check(s)) { + TCGv_ptr status =3D fpstatus_ptr(FPST_FPCR); + unsigned vsz =3D vec_full_reg_size(s); + + tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + vec_full_reg_offset(s, a->ra), + status, vsz, vsz, (a->index << 1) | sel, + gen_helper_gvec_bfmlal_idx); + tcg_temp_free_ptr(status); + } + return true; +} + +static bool trans_BFMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a) +{ + return do_BFMLAL_zzxw(s, a, false); +} + +static bool trans_BFMLALT_zzxw(DisasContext *s, arg_rrxr_esz *a) +{ + return do_BFMLAL_zzxw(s, a, true); +} diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index d82736b5e66..5862f187cdc 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2528,3 +2528,25 @@ void HELPER(gvec_bfmlal)(void *vd, void *vn, void *v= m, void *va, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm, + void *va, void *stat, uint32_t desc) +{ + intptr_t i, j, opr_sz =3D simd_oprsz(desc); + intptr_t sel =3D extract32(desc, SIMD_DATA_SHIFT, 1); + intptr_t index =3D extract32(desc, SIMD_DATA_SHIFT + 1, 3); + intptr_t elements =3D opr_sz / 4; + intptr_t eltspersegment =3D MIN(16 / 4, elements); + float32 *d =3D vd, *a =3D va; + bfloat16 *n =3D vn, *m =3D vm; + + for (i =3D 0; i < elements; i +=3D eltspersegment) { + float32 m_idx =3D m[H2(2 * i + index)] << 16; + + for (j =3D i; j < i + eltspersegment; j++) { + float32 n_j =3D n[H2(2 * j + sel)] << 16; + d[H4(j)] =3D float32_muladd(n_j, m_idx, a[H4(j)], 0, stat); + } + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736956; cv=none; d=zohomail.com; s=zohoarc; b=lk0ympzlbtDiEJuQCoTmhVxWC8bk/t5luUsNf1tT4mqyn895dv5h/1LJZ2ZD96hMZctzMMxCWuA1A2KGT4LimAVJIhH3bZxpNGEx9OSQ5/wnnZb3sg9SSeUcvRf2RGibTQqJe6vuvtqa6C6NiXyB01MAWwpSlUkpPRt5KqEbaC4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736956; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WtEpVmIvsaRaNzylpQMHyWPaveoMgdHxl+rJ1pUl7k8=; b=UvcCHVrKNejoF//0gp+aGw5BHufs8FRKS4pX+yTzC24hNRmaXkHa7WsvdX7gGNZprp X7GUlULBwujkarqqRQsqvmGi891CNXs4+Esjizevboysu1Sj1nzrUwryChJ5tURk6lRr bnZa1sR3tAcv1b04zcT0DmVaU7jy0eIKhXT3Vy20UJ6LpXMeDbWPOmbqTy2loWsSP61G U1Y8sChGU6zN/4l2CdAcZ5vI8tTa8Ac3IK3TCSnoIpru0rFDEeQ9ZjyT5Dm4sKvqPeZV jMSC1KZdSxRNHp9sU29Xq8oMQcPBt81+cntPpE/cW8VFBY/QaF/zkOTs/wXj86KJbmCs AU1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WtEpVmIvsaRaNzylpQMHyWPaveoMgdHxl+rJ1pUl7k8=; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-12-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- linux-user/elfload.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 1ab97e38e08..17ab06f612d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -659,7 +659,9 @@ static uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM); GET_FEATURE_ID(aa64_sve_f32mm, ARM_HWCAP2_A64_SVEF32MM); GET_FEATURE_ID(aa64_sve_f64mm, ARM_HWCAP2_A64_SVEF64MM); + GET_FEATURE_ID(aa64_sve_bf16, ARM_HWCAP2_A64_SVEBF16); GET_FEATURE_ID(aa64_i8mm, ARM_HWCAP2_A64_I8MM); + GET_FEATURE_ID(aa64_bf16, ARM_HWCAP2_A64_BF16); GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737118; cv=none; d=zohomail.com; s=zohoarc; b=kOVKik0iD+ZEH1MHRrlPeOML8cVmfzlvoh0gtLpr4geC28Qqg5WHIo67sbAlgWwLnLprzhbVuxBeDQ/tdOiNZZFcDWtdnKMJ+Bu+jQTb9O3RMY7CoUjsiV4C/DQ+foiMOuqADX95UtEpPEti18eVRD1+QopVY6Kr80uA9uI2vgs= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VDBN3NMYfdiVq5Oflec7BhDX1CHc12wtHAjxegZUl9g=; b=C0mbUOgoqoGUpNEBTOx+1RBYD9Q3tPxMjprzaBHH0E9njvYbS+UJeyElc962eZEnBa QPp0KiMDqCIbCI+/DEw2CmHr2bHsgLSPbv/4neKee0jyh4zVDIeWLCGAWEnSQ1oE68RI O+En8wC3qv8y/6/dRIvqKUXYOQygo3vu4HU+8W/VIgFKt0ixBPlOFDfwvcU/ujcvA+ux cWSYCMnSQbLwaYif4AFolT23y5iwBlPdwlNHQc2nHJt1ws9Mp2eSPO0lxfb2XpG08yuG fZPuHSpYgswTkLrslL13GbT0anpCi103gACQgtyeWqSCkkbIgggm40sj2fo7KsBLZpu4 RUyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VDBN3NMYfdiVq5Oflec7BhDX1CHc12wtHAjxegZUl9g=; b=J4h5DwGjaezxnV75znR+k1xasmW6V6Aafwl+RMdlmUjzhDEHTS/XDfDNIeZUD/PW2m 0eH5NwH+KoXF8uH47kREknY7+Q0zvZOKYhf2G6bojh++krYLEGZ4s7yYczBjxnuAOvXf KgqPW+QQcQWKgzTedPyEn1VKJO74h8Lj1Iw//0eeDzNc+yG59j13bUBHlW+BWxP1eg/O g19uPTkO0JYGOL19GvK3TDtHlcnjLZPHrvj/AXOHujvr2MIPkRXFLQCBUZzrhXcBgp7e O/wwEd3/rL75BDVCcocDURRN5gczHmvsMUTRIpXOggiZfeUeE2hN3IzimebiJIpdAnfE EX9A== X-Gm-Message-State: AOAM5302wWe7Q4VUzV4yksLURv5+KdtktZ/WheXsZwiycHiXR6H95KRB 1OHk8NITEKd2XXWwbUcaJeFxpTmp2re9V2Np X-Google-Smtp-Source: ABdhPJywwoK1zTWc52yaUgLoNdhDvw7ewgfQBivi/l/aE10Cf0XMVlL+vdcZx9XYLeVJs7A5N/SHTA== X-Received: by 2002:a5d:4203:: with SMTP id n3mr682358wrq.132.1622735971507; Thu, 03 Jun 2021 08:59:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/45] target/arm: Enable BFloat16 extensions Date: Thu, 3 Jun 2021 16:58:46 +0100 Message-Id: <20210603155904.26021-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Disable BF16 again for !have_neon and !have_vfp during realize. Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-13-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 3 +++ target/arm/cpu64.c | 3 +++ target/arm/cpu_tcg.c | 1 + 3 files changed, 7 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9ad6f5911b6..9cddfd6a442 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1473,6 +1473,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) =20 u =3D cpu->isar.id_isar6; u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 0); + u =3D FIELD_DP32(u, ID_ISAR6, BF16, 0); cpu->isar.id_isar6 =3D u; =20 u =3D cpu->isar.mvfr0; @@ -1513,6 +1514,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); cpu->isar.id_aa64isar1 =3D t; =20 @@ -1528,6 +1530,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) u =3D cpu->isar.id_isar6; u =3D FIELD_DP32(u, ID_ISAR6, DP, 0); u =3D FIELD_DP32(u, ID_ISAR6, FHM, 0); + u =3D FIELD_DP32(u, ID_ISAR6, BF16, 0); u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 0); cpu->isar.id_isar6 =3D u; =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d561dc7accc..1c23187d1a5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -661,6 +661,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); @@ -708,6 +709,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); @@ -731,6 +733,7 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); + u =3D FIELD_DP32(u, ID_ISAR6, BF16, 1); u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 1); cpu->isar.id_isar6 =3D u; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 2e0e508f0e9..d2d97115ea1 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -968,6 +968,7 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); cpu->isar.id_isar6 =3D t; =20 --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=grpJYafjNW+ukFyoPqAiBJXGevYi02tanX+BC8ln2iM=; b=FOOB2ILcray/Zxz9fQPHfQ+w7kGTC8USftSK6RO58oTgZjLhIr8s67H8gp7PhfEhX3 OIQLdRkK9KseK6RzIRwTEIzlkpRitjlzH5tMuQafUofD3JFeV3LjlD/3etMzl2eoEHY6 CS88ENvMkOvQllS+heCNS+heY0nG4pxzZ6zpg7uQaj7Yy9fgrBlgUO4VTeZDAL2L9mGQ m1u6ENXXUNTgUKQxm4TtD/Urq2PuilgAn50TEL8rx/Sdv9q+7V1vgZ05eXiIvvn7DhoZ 6wPwKFc9H1KQWva8s1KxvOn4zKnew6hCHn0A7i9OB5++ZaMRvz5NwUMM/aaDAAFInXfG iBUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=grpJYafjNW+ukFyoPqAiBJXGevYi02tanX+BC8ln2iM=; b=U4P20jQAwpoTtvfb6riuyIgyQFyKmuLF86JBbBAT8dAKhfuKpw2hbH4d8ETUqfP3Hb yJ1EDALyB8wN2I158SZ/XyanHe7NSE850KlgtJZi8QnbYlR6rhGTf9t+BUbHay28jD9V DNR1dVwUNdbUemoBWZXnAisPDkMlbrYsP/GDBPIMocbZ4dBgwzQix/cpaK/DTcRciaKf aMQN3KxZpzm8yvbgdgpBWdYmUwoe9zGMev3/sp92nRx6m7OfzsX06GubqFai9hJ/mU9q R0D/PzBGUYRENqvVy79aaFFjPwwtZWmKUax6FAzSE3RHodjy6OUcW8ABNYCxf/ct4yNU Wj3w== X-Gm-Message-State: AOAM532n4nrW3aBinD2ePGuCOrXMv93O1sB2b1pVOg3zfnldUzvgPq/H +Yb20b0VWBfxNGXkcBs907L3AYYU66ks21Gd X-Google-Smtp-Source: ABdhPJxyxgDXHONcJmI7CYldjJxl70eEQFLsgk5SaambYLYSpev4luMp7mDQJifFv9JjE524Oq5GMQ== X-Received: by 2002:a5d:46cb:: with SMTP id g11mr645972wrs.418.1622735973292; Thu, 03 Jun 2021 08:59:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/45] hvf: Move assert_hvf_ok() into common directory Date: Thu, 3 Jun 2021 16:58:47 +0100 Message-Id: <20210603155904.26021-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alexander Graf Until now, Hypervisor.framework has only been available on x86_64 systems. With Apple Silicon shipping now, it extends its reach to aarch64. To prepare for support for multiple architectures, let's start moving common code out into its own accel directory. This patch moves assert_hvf_ok() and introduces generic build infrastructur= e. Signed-off-by: Alexander Graf Reviewed-by: Sergio Lopez Message-id: 20210519202253.76782-2-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/sysemu/hvf_int.h | 18 +++++++++++++++ accel/hvf/hvf-all.c | 47 ++++++++++++++++++++++++++++++++++++++++ target/i386/hvf/hvf.c | 33 +--------------------------- MAINTAINERS | 8 +++++++ accel/hvf/meson.build | 6 +++++ accel/meson.build | 1 + 6 files changed, 81 insertions(+), 32 deletions(-) create mode 100644 include/sysemu/hvf_int.h create mode 100644 accel/hvf/hvf-all.c create mode 100644 accel/hvf/meson.build diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h new file mode 100644 index 00000000000..3deb4cfacc4 --- /dev/null +++ b/include/sysemu/hvf_int.h @@ -0,0 +1,18 @@ +/* + * QEMU Hypervisor.framework (HVF) support + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +/* header to be included in HVF-specific code */ + +#ifndef HVF_INT_H +#define HVF_INT_H + +#include + +void assert_hvf_ok(hv_return_t ret); + +#endif diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c new file mode 100644 index 00000000000..f185b0830a7 --- /dev/null +++ b/accel/hvf/hvf-all.c @@ -0,0 +1,47 @@ +/* + * QEMU Hypervisor.framework support + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/error-report.h" +#include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" + +void assert_hvf_ok(hv_return_t ret) +{ + if (ret =3D=3D HV_SUCCESS) { + return; + } + + switch (ret) { + case HV_ERROR: + error_report("Error: HV_ERROR"); + break; + case HV_BUSY: + error_report("Error: HV_BUSY"); + break; + case HV_BAD_ARGUMENT: + error_report("Error: HV_BAD_ARGUMENT"); + break; + case HV_NO_RESOURCES: + error_report("Error: HV_NO_RESOURCES"); + break; + case HV_NO_DEVICE: + error_report("Error: HV_NO_DEVICE"); + break; + case HV_UNSUPPORTED: + error_report("Error: HV_UNSUPPORTED"); + break; + default: + error_report("Unknown Error"); + } + + abort(); +} diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index f044181d061..32f42f15924 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -51,6 +51,7 @@ #include "qemu/error-report.h" =20 #include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" #include "sysemu/runstate.h" #include "hvf-i386.h" #include "vmcs.h" @@ -76,38 +77,6 @@ =20 HVFState *hvf_state; =20 -static void assert_hvf_ok(hv_return_t ret) -{ - if (ret =3D=3D HV_SUCCESS) { - return; - } - - switch (ret) { - case HV_ERROR: - error_report("Error: HV_ERROR"); - break; - case HV_BUSY: - error_report("Error: HV_BUSY"); - break; - case HV_BAD_ARGUMENT: - error_report("Error: HV_BAD_ARGUMENT"); - break; - case HV_NO_RESOURCES: - error_report("Error: HV_NO_RESOURCES"); - break; - case HV_NO_DEVICE: - error_report("Error: HV_NO_DEVICE"); - break; - case HV_UNSUPPORTED: - error_report("Error: HV_UNSUPPORTED"); - break; - default: - error_report("Unknown Error"); - } - - abort(); -} - /* Memory slots */ hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t size) { diff --git a/MAINTAINERS b/MAINTAINERS index 96a4eeb5a59..de5426f6724 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -436,7 +436,15 @@ M: Roman Bolshakov W: https://wiki.qemu.org/Features/HVF S: Maintained F: target/i386/hvf/ + +HVF +M: Cameron Esfahani +M: Roman Bolshakov +W: https://wiki.qemu.org/Features/HVF +S: Maintained +F: accel/hvf/ F: include/sysemu/hvf.h +F: include/sysemu/hvf_int.h =20 WHPX CPUs M: Sunil Muthuswamy diff --git a/accel/hvf/meson.build b/accel/hvf/meson.build new file mode 100644 index 00000000000..227b11cd717 --- /dev/null +++ b/accel/hvf/meson.build @@ -0,0 +1,6 @@ +hvf_ss =3D ss.source_set() +hvf_ss.add(files( + 'hvf-all.c', +)) + +specific_ss.add_all(when: 'CONFIG_HVF', if_true: hvf_ss) diff --git a/accel/meson.build b/accel/meson.build index b44ba30c864..dfd808d2c8e 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -2,6 +2,7 @@ specific_ss.add(files('accel-common.c')) softmmu_ss.add(files('accel-softmmu.c')) user_ss.add(files('accel-user.c')) =20 +subdir('hvf') subdir('qtest') subdir('kvm') subdir('tcg') --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1mYBCex9meGBr2ctnrZlReVhFiOSt3U/7dRPAFjy6z0=; b=Y3bAmTtR99BbEWm7edmZ1w12xeUfhZcRkk2iM4jX4k1JyR9f27/ZHe1dqRDGLAFSVV te+zsfLEEdcSzzuSzBjLsXQ3Mo7NQm9ZxpVMfcEufsNg2yVaKp5KOQA59tWX+6FIXYki gpxhMzhcc40qHU105gFVqjkoLMJHhSVxY+BLHmE/kct3pf/bkIIgp+m3U9DtBXkwhM9G 8aT7uxvL/vmQnVm92fiV0if86if3UeRYwPNfrBc5LIs07Tu4Kz24Zkq3efxjEo3QkqVn tomrJ9g3Mu+Qkfe0q5aDTPz8ztCwcPh27BttDvHJuA70BhR3nUUJa2xErMTnQBcfJBey 5/7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1mYBCex9meGBr2ctnrZlReVhFiOSt3U/7dRPAFjy6z0=; b=KKTIhmTWJnNxPDpvx0RIxYNkIyhz+nKfWKrStK3c6KkBpv+0V3m9oh1uv4prUzQU4L paosZNRruCdcFHhntsq6hLvcBvLYhLN/FdeD6+xIY0p2NvfDz2DAg2Rymc/DymtU4nsg HTMiJCmVAqeNAv74SJMVOlh/vqIWSGY856tdbOp3oNz3oKtc/0M6qALMM6MgwI6rH240 ho42M/97u1TtAc61z56B6o/WnOPw1YvALJuxOPkmTlHfnqNdskLU9Yi4Xgor5kRZzyf4 JPK9fnI+0x/vVhCASR0WWRIMavy4G/S480qu2sRxfUZT4bUNuD9nDqyzgQYkYCOLBb5f x5Fg== X-Gm-Message-State: AOAM530JWt5e4qkylznsyGXlt9rQ3hDJzAzSljtColTn1+sUl+hBp1Gr /Bn9MYR7yJErT6YEFphPMVaOqTiyOPAw/Q1J X-Google-Smtp-Source: ABdhPJypdHImMRvVefV3MX1EI5aGn2VNBNmfV95bgBxmA22rRoB+2imdVg2/b36UFOzsJle92XsElQ== X-Received: by 2002:a5d:4b87:: with SMTP id b7mr615342wrt.129.1622735975426; Thu, 03 Jun 2021 08:59:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/45] hvf: Move vcpu thread functions into common directory Date: Thu, 3 Jun 2021 16:58:48 +0100 Message-Id: <20210603155904.26021-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alexander Graf Until now, Hypervisor.framework has only been available on x86_64 systems. With Apple Silicon shipping now, it extends its reach to aarch64. To prepare for support for multiple architectures, let's start moving common code out into its own accel directory. This patch moves the vCPU thread loop over. Signed-off-by: Alexander Graf Reviewed-by: Sergio Lopez Message-id: 20210519202253.76782-3-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- {target/i386 =3D> accel}/hvf/hvf-accel-ops.h | 0 {target/i386 =3D> accel}/hvf/hvf-accel-ops.c | 0 target/i386/hvf/x86hvf.c | 2 +- accel/hvf/meson.build | 1 + target/i386/hvf/meson.build | 1 - 5 files changed, 2 insertions(+), 2 deletions(-) rename {target/i386 =3D> accel}/hvf/hvf-accel-ops.h (100%) rename {target/i386 =3D> accel}/hvf/hvf-accel-ops.c (100%) diff --git a/target/i386/hvf/hvf-accel-ops.h b/accel/hvf/hvf-accel-ops.h similarity index 100% rename from target/i386/hvf/hvf-accel-ops.h rename to accel/hvf/hvf-accel-ops.h diff --git a/target/i386/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c similarity index 100% rename from target/i386/hvf/hvf-accel-ops.c rename to accel/hvf/hvf-accel-ops.c diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index 0d7533742eb..2b99f3eaa2d 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -32,7 +32,7 @@ #include #include =20 -#include "hvf-accel-ops.h" +#include "accel/hvf/hvf-accel-ops.h" =20 void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr) diff --git a/accel/hvf/meson.build b/accel/hvf/meson.build index 227b11cd717..fc52cb78433 100644 --- a/accel/hvf/meson.build +++ b/accel/hvf/meson.build @@ -1,6 +1,7 @@ hvf_ss =3D ss.source_set() hvf_ss.add(files( 'hvf-all.c', + 'hvf-accel-ops.c', )) =20 specific_ss.add_all(when: 'CONFIG_HVF', if_true: hvf_ss) diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build index d253d5fd102..f6d4c394d3e 100644 --- a/target/i386/hvf/meson.build +++ b/target/i386/hvf/meson.build @@ -1,6 +1,5 @@ i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files( 'hvf.c', - 'hvf-accel-ops.c', 'x86.c', 'x86_cpuid.c', 'x86_decode.c', --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737422; cv=none; d=zohomail.com; s=zohoarc; b=KCnAzX8iX46lf710N5SrQlmMRPq8PgMzgrWz2VtQQXgLl6mFIM7FWklPELiyVPZTFmG37DABUUva0BbfQNCfHB9jx39NF+BOEByXJzHxAbKM0aR+sWg7eneqkjMsJNp315HqeG9w2xsLqZdmW4MOlp74tRSyb9LkB56gi4nnmZA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737422; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KTS3TaiYQCpx2ZVWFGEqIbk7tCTbfCHQfmLGknTzTDQ=; b=DQ3+D6EBzMhWGuRMWHV4XW5p0OpoTSlb3zgUUqnuc6pNgNNhHgtdEkjpXwlq/Pb+12OaI7xYvkKvESSgxQjGxCRElhfIxl9grm9m3VND45fPR10b+Gi4wizwoPJkc0LFzicj/bOgUTLLb8Ezh+U2RcQNr00ALQl3HvZ0/CczE6M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737422545972.3297791607929; Thu, 3 Jun 2021 09:23:42 -0700 (PDT) Received: from localhost ([::1]:39574 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loq8D-0003fk-5y for importer2@patchew.org; Thu, 03 Jun 2021 12:23:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopl0-0001Qx-37 for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:42 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:33665) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkx-0007Da-5e for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:41 -0400 Received: by mail-wr1-x430.google.com with SMTP id a20so6436741wrc.0 for ; Thu, 03 Jun 2021 08:59:38 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KTS3TaiYQCpx2ZVWFGEqIbk7tCTbfCHQfmLGknTzTDQ=; b=GlOQiXd+EpJkJhw7/ya//wxvK5JjUlLzFlPDDCAqV3PLzxojqOdg1MEXVxDsKi74vV H9beo6dVsMY/x1IjtA/TTxnlO+VwbhdGruiUxG5CR2apUeo1+E/we9JCIRG3DskEjuSw RE6SBieq7wx4UubcUEsmCon65hia3C8EY0FZbbDzZlcsviaLs48QDuWQ0Mdi9PPipX7Z vTFHECdF5+1Hv9YyYba5bSMZna+ZUJmXQXIgfmYzkjjeQY/YqWQTA/d2dCtHzOjtXiOA /pxFsEf2b4JJdEF9FbRK9Lu43MYkp5bQf49PwMpbaA7tW4APoppQzeah5eSVKJlDsbid OZeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KTS3TaiYQCpx2ZVWFGEqIbk7tCTbfCHQfmLGknTzTDQ=; b=QcPSu2KLO6MQK+CicZjyvoddhNjr5kZEOcoKJz4GoIbcAfuU28loOZJ89Ofb2uUJzt 1n0fOz8dxQUJGV990GCEthcC4VeX8vIONLT+K6fbeD8z9fH0PtF7pEtJLgAhwS/QEwpp rX3E7TORlRgDk24UABk6F0/DYpEhb0DTDyScx7E0Lpmj5c6Y/0YRajQd7yY82yFebnKh YYvAaWYTvbU/FUnHcmxJO1URCCXPKIvjFqhF+/Reg148cwCJKk1lNpnNV+Nmv246YL+x fUL4HNHkwRQAOfbxpon+++AVVtV8DIwj4G0YOcGETtls/OS9fi8xjfOBAK2Rypgo27ak bv5w== X-Gm-Message-State: AOAM530eCoujAX4dO/Yb2dcefwUraiJ4Zj16XgwOjcL5k6TSoONxbZeE gnCpi8NTwoORsOfbVYZv61ZAhPHK2aYHUXSO X-Google-Smtp-Source: ABdhPJx0ffCjztLsQblWSp21raIYJ/XW2sDe8mv+MaqSAFErbeZZovBiJr7V+szR+f7pEkEQpjFGVg== X-Received: by 2002:adf:f382:: with SMTP id m2mr655423wro.394.1622735977833; Thu, 03 Jun 2021 08:59:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/45] hvf: Move cpu functions into common directory Date: Thu, 3 Jun 2021 16:58:49 +0100 Message-Id: <20210603155904.26021-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alexander Graf Until now, Hypervisor.framework has only been available on x86_64 systems. With Apple Silicon shipping now, it extends its reach to aarch64. To prepare for support for multiple architectures, let's start moving common code out into its own accel directory. This patch moves CPU and memory operations over. While at it, make sure the code is consumable on non-i386 systems. Signed-off-by: Alexander Graf Reviewed-by: Sergio Lopez Message-id: 20210519202253.76782-4-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/sysemu/hvf_int.h | 4 + target/i386/hvf/hvf-i386.h | 2 - target/i386/hvf/x86hvf.h | 2 - accel/hvf/hvf-accel-ops.c | 308 ++++++++++++++++++++++++++++++++++++- target/i386/hvf/hvf.c | 302 ------------------------------------ 5 files changed, 311 insertions(+), 307 deletions(-) diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 3deb4cfacc4..4c657b054c1 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -13,6 +13,10 @@ =20 #include =20 +void hvf_set_phys_mem(MemoryRegionSection *, bool); void assert_hvf_ok(hv_return_t ret); +hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); +int hvf_put_registers(CPUState *); +int hvf_get_registers(CPUState *); =20 #endif diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h index 59cfca8875e..94e5c788c48 100644 --- a/target/i386/hvf/hvf-i386.h +++ b/target/i386/hvf/hvf-i386.h @@ -51,9 +51,7 @@ struct HVFState { }; extern HVFState *hvf_state; =20 -void hvf_set_phys_mem(MemoryRegionSection *, bool); void hvf_handle_io(CPUArchState *, uint16_t, void *, int, int, int); -hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); =20 #ifdef NEED_CPU_H /* Functions exported to host specific mode */ diff --git a/target/i386/hvf/x86hvf.h b/target/i386/hvf/x86hvf.h index 635ab0f34e4..99ed8d608dd 100644 --- a/target/i386/hvf/x86hvf.h +++ b/target/i386/hvf/x86hvf.h @@ -21,8 +21,6 @@ #include "x86_descr.h" =20 int hvf_process_events(CPUState *); -int hvf_put_registers(CPUState *); -int hvf_get_registers(CPUState *); bool hvf_inject_interrupts(CPUState *); void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr); diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index cbaad238e0d..c2136dfbb8c 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -50,13 +50,319 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "exec/address-spaces.h" +#include "exec/exec-all.h" +#include "sysemu/cpus.h" #include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" #include "sysemu/runstate.h" -#include "target/i386/cpu.h" #include "qemu/guest-random.h" =20 #include "hvf-accel-ops.h" =20 +HVFState *hvf_state; + +/* Memory slots */ + +hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t size) +{ + hvf_slot *slot; + int x; + for (x =3D 0; x < hvf_state->num_slots; ++x) { + slot =3D &hvf_state->slots[x]; + if (slot->size && start < (slot->start + slot->size) && + (start + size) > slot->start) { + return slot; + } + } + return NULL; +} + +struct mac_slot { + int present; + uint64_t size; + uint64_t gpa_start; + uint64_t gva; +}; + +struct mac_slot mac_slots[32]; + +static int do_hvf_set_memory(hvf_slot *slot, hv_memory_flags_t flags) +{ + struct mac_slot *macslot; + hv_return_t ret; + + macslot =3D &mac_slots[slot->slot_id]; + + if (macslot->present) { + if (macslot->size !=3D slot->size) { + macslot->present =3D 0; + ret =3D hv_vm_unmap(macslot->gpa_start, macslot->size); + assert_hvf_ok(ret); + } + } + + if (!slot->size) { + return 0; + } + + macslot->present =3D 1; + macslot->gpa_start =3D slot->start; + macslot->size =3D slot->size; + ret =3D hv_vm_map((hv_uvaddr_t)slot->mem, slot->start, slot->size, fla= gs); + assert_hvf_ok(ret); + return 0; +} + +void hvf_set_phys_mem(MemoryRegionSection *section, bool add) +{ + hvf_slot *mem; + MemoryRegion *area =3D section->mr; + bool writeable =3D !area->readonly && !area->rom_device; + hv_memory_flags_t flags; + + if (!memory_region_is_ram(area)) { + if (writeable) { + return; + } else if (!memory_region_is_romd(area)) { + /* + * If the memory device is not in romd_mode, then we actually = want + * to remove the hvf memory slot so all accesses will trap. + */ + add =3D false; + } + } + + mem =3D hvf_find_overlap_slot( + section->offset_within_address_space, + int128_get64(section->size)); + + if (mem && add) { + if (mem->size =3D=3D int128_get64(section->size) && + mem->start =3D=3D section->offset_within_address_space && + mem->mem =3D=3D (memory_region_get_ram_ptr(area) + + section->offset_within_region)) { + return; /* Same region was attempted to register, go away. */ + } + } + + /* Region needs to be reset. set the size to 0 and remap it. */ + if (mem) { + mem->size =3D 0; + if (do_hvf_set_memory(mem, 0)) { + error_report("Failed to reset overlapping slot"); + abort(); + } + } + + if (!add) { + return; + } + + if (area->readonly || + (!memory_region_is_ram(area) && memory_region_is_romd(area))) { + flags =3D HV_MEMORY_READ | HV_MEMORY_EXEC; + } else { + flags =3D HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC; + } + + /* Now make a new slot. */ + int x; + + for (x =3D 0; x < hvf_state->num_slots; ++x) { + mem =3D &hvf_state->slots[x]; + if (!mem->size) { + break; + } + } + + if (x =3D=3D hvf_state->num_slots) { + error_report("No free slots"); + abort(); + } + + mem->size =3D int128_get64(section->size); + mem->mem =3D memory_region_get_ram_ptr(area) + section->offset_within_= region; + mem->start =3D section->offset_within_address_space; + mem->region =3D area; + + if (do_hvf_set_memory(mem, flags)) { + error_report("Error registering new memory slot"); + abort(); + } +} + +static void do_hvf_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data ar= g) +{ + if (!cpu->vcpu_dirty) { + hvf_get_registers(cpu); + cpu->vcpu_dirty =3D true; + } +} + +void hvf_cpu_synchronize_state(CPUState *cpu) +{ + if (!cpu->vcpu_dirty) { + run_on_cpu(cpu, do_hvf_cpu_synchronize_state, RUN_ON_CPU_NULL); + } +} + +static void do_hvf_cpu_synchronize_post_reset(CPUState *cpu, + run_on_cpu_data arg) +{ + hvf_put_registers(cpu); + cpu->vcpu_dirty =3D false; +} + +void hvf_cpu_synchronize_post_reset(CPUState *cpu) +{ + run_on_cpu(cpu, do_hvf_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); +} + +static void do_hvf_cpu_synchronize_post_init(CPUState *cpu, + run_on_cpu_data arg) +{ + hvf_put_registers(cpu); + cpu->vcpu_dirty =3D false; +} + +void hvf_cpu_synchronize_post_init(CPUState *cpu) +{ + run_on_cpu(cpu, do_hvf_cpu_synchronize_post_init, RUN_ON_CPU_NULL); +} + +static void do_hvf_cpu_synchronize_pre_loadvm(CPUState *cpu, + run_on_cpu_data arg) +{ + cpu->vcpu_dirty =3D true; +} + +void hvf_cpu_synchronize_pre_loadvm(CPUState *cpu) +{ + run_on_cpu(cpu, do_hvf_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); +} + +static void hvf_set_dirty_tracking(MemoryRegionSection *section, bool on) +{ + hvf_slot *slot; + + slot =3D hvf_find_overlap_slot( + section->offset_within_address_space, + int128_get64(section->size)); + + /* protect region against writes; begin tracking it */ + if (on) { + slot->flags |=3D HVF_SLOT_LOG; + hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size, + HV_MEMORY_READ); + /* stop tracking region*/ + } else { + slot->flags &=3D ~HVF_SLOT_LOG; + hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size, + HV_MEMORY_READ | HV_MEMORY_WRITE); + } +} + +static void hvf_log_start(MemoryListener *listener, + MemoryRegionSection *section, int old, int new) +{ + if (old !=3D 0) { + return; + } + + hvf_set_dirty_tracking(section, 1); +} + +static void hvf_log_stop(MemoryListener *listener, + MemoryRegionSection *section, int old, int new) +{ + if (new !=3D 0) { + return; + } + + hvf_set_dirty_tracking(section, 0); +} + +static void hvf_log_sync(MemoryListener *listener, + MemoryRegionSection *section) +{ + /* + * sync of dirty pages is handled elsewhere; just make sure we keep + * tracking the region. + */ + hvf_set_dirty_tracking(section, 1); +} + +static void hvf_region_add(MemoryListener *listener, + MemoryRegionSection *section) +{ + hvf_set_phys_mem(section, true); +} + +static void hvf_region_del(MemoryListener *listener, + MemoryRegionSection *section) +{ + hvf_set_phys_mem(section, false); +} + +static MemoryListener hvf_memory_listener =3D { + .priority =3D 10, + .region_add =3D hvf_region_add, + .region_del =3D hvf_region_del, + .log_start =3D hvf_log_start, + .log_stop =3D hvf_log_stop, + .log_sync =3D hvf_log_sync, +}; + +static void dummy_signal(int sig) +{ +} + +bool hvf_allowed; + +static int hvf_accel_init(MachineState *ms) +{ + int x; + hv_return_t ret; + HVFState *s; + + ret =3D hv_vm_create(HV_VM_DEFAULT); + assert_hvf_ok(ret); + + s =3D g_new0(HVFState, 1); + + s->num_slots =3D 32; + for (x =3D 0; x < s->num_slots; ++x) { + s->slots[x].size =3D 0; + s->slots[x].slot_id =3D x; + } + + hvf_state =3D s; + memory_listener_register(&hvf_memory_listener, &address_space_memory); + return 0; +} + +static void hvf_accel_class_init(ObjectClass *oc, void *data) +{ + AccelClass *ac =3D ACCEL_CLASS(oc); + ac->name =3D "HVF"; + ac->init_machine =3D hvf_accel_init; + ac->allowed =3D &hvf_allowed; +} + +static const TypeInfo hvf_accel_type =3D { + .name =3D TYPE_HVF_ACCEL, + .parent =3D TYPE_ACCEL, + .class_init =3D hvf_accel_class_init, +}; + +static void hvf_type_init(void) +{ + type_register_static(&hvf_accel_type); +} + +type_init(hvf_type_init); + /* * The HVF-specific vCPU thread function. This one should only run when th= e host * CPU supports the VMX "unrestricted guest" feature. diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 32f42f15924..100ede2a4d7 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -75,137 +75,6 @@ =20 #include "hvf-accel-ops.h" =20 -HVFState *hvf_state; - -/* Memory slots */ -hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t size) -{ - hvf_slot *slot; - int x; - for (x =3D 0; x < hvf_state->num_slots; ++x) { - slot =3D &hvf_state->slots[x]; - if (slot->size && start < (slot->start + slot->size) && - (start + size) > slot->start) { - return slot; - } - } - return NULL; -} - -struct mac_slot { - int present; - uint64_t size; - uint64_t gpa_start; - uint64_t gva; -}; - -struct mac_slot mac_slots[32]; - -static int do_hvf_set_memory(hvf_slot *slot, hv_memory_flags_t flags) -{ - struct mac_slot *macslot; - hv_return_t ret; - - macslot =3D &mac_slots[slot->slot_id]; - - if (macslot->present) { - if (macslot->size !=3D slot->size) { - macslot->present =3D 0; - ret =3D hv_vm_unmap(macslot->gpa_start, macslot->size); - assert_hvf_ok(ret); - } - } - - if (!slot->size) { - return 0; - } - - macslot->present =3D 1; - macslot->gpa_start =3D slot->start; - macslot->size =3D slot->size; - ret =3D hv_vm_map((hv_uvaddr_t)slot->mem, slot->start, slot->size, fla= gs); - assert_hvf_ok(ret); - return 0; -} - -void hvf_set_phys_mem(MemoryRegionSection *section, bool add) -{ - hvf_slot *mem; - MemoryRegion *area =3D section->mr; - bool writeable =3D !area->readonly && !area->rom_device; - hv_memory_flags_t flags; - - if (!memory_region_is_ram(area)) { - if (writeable) { - return; - } else if (!memory_region_is_romd(area)) { - /* - * If the memory device is not in romd_mode, then we actually = want - * to remove the hvf memory slot so all accesses will trap. - */ - add =3D false; - } - } - - mem =3D hvf_find_overlap_slot( - section->offset_within_address_space, - int128_get64(section->size)); - - if (mem && add) { - if (mem->size =3D=3D int128_get64(section->size) && - mem->start =3D=3D section->offset_within_address_space && - mem->mem =3D=3D (memory_region_get_ram_ptr(area) + - section->offset_within_region)) { - return; /* Same region was attempted to register, go away. */ - } - } - - /* Region needs to be reset. set the size to 0 and remap it. */ - if (mem) { - mem->size =3D 0; - if (do_hvf_set_memory(mem, 0)) { - error_report("Failed to reset overlapping slot"); - abort(); - } - } - - if (!add) { - return; - } - - if (area->readonly || - (!memory_region_is_ram(area) && memory_region_is_romd(area))) { - flags =3D HV_MEMORY_READ | HV_MEMORY_EXEC; - } else { - flags =3D HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC; - } - - /* Now make a new slot. */ - int x; - - for (x =3D 0; x < hvf_state->num_slots; ++x) { - mem =3D &hvf_state->slots[x]; - if (!mem->size) { - break; - } - } - - if (x =3D=3D hvf_state->num_slots) { - error_report("No free slots"); - abort(); - } - - mem->size =3D int128_get64(section->size); - mem->mem =3D memory_region_get_ram_ptr(area) + section->offset_within_= region; - mem->start =3D section->offset_within_address_space; - mem->region =3D area; - - if (do_hvf_set_memory(mem, flags)) { - error_report("Error registering new memory slot"); - abort(); - } -} - void vmx_update_tpr(CPUState *cpu) { /* TODO: need integrate APIC handling */ @@ -245,56 +114,6 @@ void hvf_handle_io(CPUArchState *env, uint16_t port, v= oid *buffer, } } =20 -static void do_hvf_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data ar= g) -{ - if (!cpu->vcpu_dirty) { - hvf_get_registers(cpu); - cpu->vcpu_dirty =3D true; - } -} - -void hvf_cpu_synchronize_state(CPUState *cpu) -{ - if (!cpu->vcpu_dirty) { - run_on_cpu(cpu, do_hvf_cpu_synchronize_state, RUN_ON_CPU_NULL); - } -} - -static void do_hvf_cpu_synchronize_post_reset(CPUState *cpu, - run_on_cpu_data arg) -{ - hvf_put_registers(cpu); - cpu->vcpu_dirty =3D false; -} - -void hvf_cpu_synchronize_post_reset(CPUState *cpu) -{ - run_on_cpu(cpu, do_hvf_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); -} - -static void do_hvf_cpu_synchronize_post_init(CPUState *cpu, - run_on_cpu_data arg) -{ - hvf_put_registers(cpu); - cpu->vcpu_dirty =3D false; -} - -void hvf_cpu_synchronize_post_init(CPUState *cpu) -{ - run_on_cpu(cpu, do_hvf_cpu_synchronize_post_init, RUN_ON_CPU_NULL); -} - -static void do_hvf_cpu_synchronize_pre_loadvm(CPUState *cpu, - run_on_cpu_data arg) -{ - cpu->vcpu_dirty =3D true; -} - -void hvf_cpu_synchronize_pre_loadvm(CPUState *cpu) -{ - run_on_cpu(cpu, do_hvf_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); -} - static bool ept_emulation_fault(hvf_slot *slot, uint64_t gpa, uint64_t ept= _qual) { int read, write; @@ -339,78 +158,6 @@ static bool ept_emulation_fault(hvf_slot *slot, uint64= _t gpa, uint64_t ept_qual) return false; } =20 -static void hvf_set_dirty_tracking(MemoryRegionSection *section, bool on) -{ - hvf_slot *slot; - - slot =3D hvf_find_overlap_slot( - section->offset_within_address_space, - int128_get64(section->size)); - - /* protect region against writes; begin tracking it */ - if (on) { - slot->flags |=3D HVF_SLOT_LOG; - hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size, - HV_MEMORY_READ); - /* stop tracking region*/ - } else { - slot->flags &=3D ~HVF_SLOT_LOG; - hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size, - HV_MEMORY_READ | HV_MEMORY_WRITE); - } -} - -static void hvf_log_start(MemoryListener *listener, - MemoryRegionSection *section, int old, int new) -{ - if (old !=3D 0) { - return; - } - - hvf_set_dirty_tracking(section, 1); -} - -static void hvf_log_stop(MemoryListener *listener, - MemoryRegionSection *section, int old, int new) -{ - if (new !=3D 0) { - return; - } - - hvf_set_dirty_tracking(section, 0); -} - -static void hvf_log_sync(MemoryListener *listener, - MemoryRegionSection *section) -{ - /* - * sync of dirty pages is handled elsewhere; just make sure we keep - * tracking the region. - */ - hvf_set_dirty_tracking(section, 1); -} - -static void hvf_region_add(MemoryListener *listener, - MemoryRegionSection *section) -{ - hvf_set_phys_mem(section, true); -} - -static void hvf_region_del(MemoryListener *listener, - MemoryRegionSection *section) -{ - hvf_set_phys_mem(section, false); -} - -static MemoryListener hvf_memory_listener =3D { - .priority =3D 10, - .region_add =3D hvf_region_add, - .region_del =3D hvf_region_del, - .log_start =3D hvf_log_start, - .log_stop =3D hvf_log_stop, - .log_sync =3D hvf_log_sync, -}; - void hvf_vcpu_destroy(CPUState *cpu) { X86CPU *x86_cpu =3D X86_CPU(cpu); @@ -421,10 +168,6 @@ void hvf_vcpu_destroy(CPUState *cpu) assert_hvf_ok(ret); } =20 -static void dummy_signal(int sig) -{ -} - static void init_tsc_freq(CPUX86State *env) { size_t length; @@ -931,48 +674,3 @@ int hvf_vcpu_exec(CPUState *cpu) =20 return ret; } - -bool hvf_allowed; - -static int hvf_accel_init(MachineState *ms) -{ - int x; - hv_return_t ret; - HVFState *s; - - ret =3D hv_vm_create(HV_VM_DEFAULT); - assert_hvf_ok(ret); - - s =3D g_new0(HVFState, 1); -=20 - s->num_slots =3D 32; - for (x =3D 0; x < s->num_slots; ++x) { - s->slots[x].size =3D 0; - s->slots[x].slot_id =3D x; - } - =20 - hvf_state =3D s; - memory_listener_register(&hvf_memory_listener, &address_space_memory); - return 0; -} - -static void hvf_accel_class_init(ObjectClass *oc, void *data) -{ - AccelClass *ac =3D ACCEL_CLASS(oc); - ac->name =3D "HVF"; - ac->init_machine =3D hvf_accel_init; - ac->allowed =3D &hvf_allowed; -} - -static const TypeInfo hvf_accel_type =3D { - .name =3D TYPE_HVF_ACCEL, - .parent =3D TYPE_ACCEL, - .class_init =3D hvf_accel_class_init, -}; - -static void hvf_type_init(void) -{ - type_register_static(&hvf_accel_type); -} - -type_init(hvf_type_init); --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737878; cv=none; d=zohomail.com; s=zohoarc; b=jFLvH/MCJl7RT96PYsLS8h8dr3n/E5+2RJ6oHEwd+2PrLCaujkacZKSfgYKDMZBb90O+J+/l9c4nOeVywZfcJ00bAIfW/L/d1YJiNtaXRmJJm6VCZPdPi4nuAHub7UgAxX7KtBak0lChzE5iVIwDLNnJhv2A4UEPiJ6kz/IsDGY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737878; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=L2jnhOpXcbKctD5AkMO99CRTbMJj/R4Ja+o8LEVjQag=; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=L2jnhOpXcbKctD5AkMO99CRTbMJj/R4Ja+o8LEVjQag=; b=E3wWZNyBtVOgvHeqqSPvK5MXLtYDiuoXr6IEtHVQiJupsjsbL7CFYSRw6P1g+cmQY9 ZkTZnwXXrCrZS2b//9+DPC5DV/2cs8l1Wm6xGVWlh8vcImaDVwpCPEC9dig1LqsrpcR7 k1doRmJV6jyF3wgnHRYjU2XJqgcYg3Tv1UW52NYz2+rFmodwoCdQyLpaOeHf8nMkuyV6 bsAwWsrfkLHrX4C4eZzsTOIKqKtkery6poroPID8sGBoVKKrfF5958gpGQFw3TY7Je89 Yt3N9qH0ehVIEc1b+h4l50GyZguwZVzMhV2HnG2UWmMydfysYmZPcpiRrEupQ12oePHI fo/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L2jnhOpXcbKctD5AkMO99CRTbMJj/R4Ja+o8LEVjQag=; b=MC97ds0Zkb+UGW9sQw0MxbbB4R285WGTAO+fsX4vjhpRD+w7zCkTdx85kDHCaewh46 fCUfmh8/1ecY63zA/mBQJUalPr1+CI9bLDFIyscOmUXEcbMqKAXX27i4QkwzzCoaz4j2 j+49QLWdZv740NehqJ6O2KBBa+DrrRD+n2H6auVRhp9yQ7YVKBqPv6eP/j1vs5SgXgbE WjSuquNVV0leGfChUPBmvd/kd+hHTy5M0P9n/gG9GjRqE+YgIO0xkL7Jlhg2ylK4hcFU /QD8tN4yWmXRAWGXhYR3W7XP3xf+SfTyiW/S7xRj/zU56k/npPwn1nhnXrYeU5HTUDkx tgOg== X-Gm-Message-State: AOAM530F5LCbTMwO+IJogo11HW6p8iuZ0xm/GN0rPDUyMIPzLOl81rHc OjksN35slcR0v5DsPhetwJzqks7tsHxPFQHc X-Google-Smtp-Source: ABdhPJxFBLNIsmlNcYhCAm758FumKuw2d8RUouKGslF47DIuI2YhDfXQvDtdCoLGaQV4AC8QYq7zJA== X-Received: by 2002:adf:dcc3:: with SMTP id x3mr616670wrm.177.1622735979035; Thu, 03 Jun 2021 08:59:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/45] hvf: Move hvf internal definitions into common header Date: Thu, 3 Jun 2021 16:58:50 +0100 Message-Id: <20210603155904.26021-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alexander Graf Until now, Hypervisor.framework has only been available on x86_64 systems. With Apple Silicon shipping now, it extends its reach to aarch64. To prepare for support for multiple architectures, let's start moving common code out into its own accel directory. This patch moves a few internal struct and constant defines over. Signed-off-by: Alexander Graf Reviewed-by: Sergio Lopez Message-id: 20210519202253.76782-5-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/sysemu/hvf_int.h | 30 ++++++++++++++++++++++++++++++ target/i386/hvf/hvf-i386.h | 31 +------------------------------ 2 files changed, 31 insertions(+), 30 deletions(-) diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 4c657b054c1..ef84a24dd96 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -13,6 +13,36 @@ =20 #include =20 +/* hvf_slot flags */ +#define HVF_SLOT_LOG (1 << 0) + +typedef struct hvf_slot { + uint64_t start; + uint64_t size; + uint8_t *mem; + int slot_id; + uint32_t flags; + MemoryRegion *region; +} hvf_slot; + +typedef struct hvf_vcpu_caps { + uint64_t vmx_cap_pinbased; + uint64_t vmx_cap_procbased; + uint64_t vmx_cap_procbased2; + uint64_t vmx_cap_entry; + uint64_t vmx_cap_exit; + uint64_t vmx_cap_preemption_timer; +} hvf_vcpu_caps; + +struct HVFState { + AccelState parent; + hvf_slot slots[32]; + int num_slots; + + hvf_vcpu_caps *hvf_caps; +}; +extern HVFState *hvf_state; + void hvf_set_phys_mem(MemoryRegionSection *, bool); void assert_hvf_ok(hv_return_t ret); hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h index 94e5c788c48..76e9235524c 100644 --- a/target/i386/hvf/hvf-i386.h +++ b/target/i386/hvf/hvf-i386.h @@ -18,39 +18,10 @@ =20 #include "qemu/accel.h" #include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" #include "cpu.h" #include "x86.h" =20 -/* hvf_slot flags */ -#define HVF_SLOT_LOG (1 << 0) - -typedef struct hvf_slot { - uint64_t start; - uint64_t size; - uint8_t *mem; - int slot_id; - uint32_t flags; - MemoryRegion *region; -} hvf_slot; - -typedef struct hvf_vcpu_caps { - uint64_t vmx_cap_pinbased; - uint64_t vmx_cap_procbased; - uint64_t vmx_cap_procbased2; - uint64_t vmx_cap_entry; - uint64_t vmx_cap_exit; - uint64_t vmx_cap_preemption_timer; -} hvf_vcpu_caps; - -struct HVFState { - AccelState parent; - hvf_slot slots[32]; - int num_slots; - - hvf_vcpu_caps *hvf_caps; -}; -extern HVFState *hvf_state; - void hvf_handle_io(CPUArchState *, uint16_t, void *, int, int, int); =20 #ifdef NEED_CPU_H --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737064; cv=none; d=zohomail.com; s=zohoarc; b=eQLHd4MVWODPyX/WcxnK3NbJf+GehgTniLqUCdZJJJ2X5LKfoxSCcozxHarmxn41o7JxSkK8DUmjJ5Q6iInVTzQXu3x1S9TWsJNNGUtbFbrnJzBWDgejtuwXCfJLWhetoTtlBTP6kTWGG3qBLlrzg0AOeMUYXMzekAz5p/5We/o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737064; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TysIKDrUi/AEFUKTDKtgxqlH2Ug1XczQwdL8ralDjLo=; b=Mf8oLhGpRbGFXVrVcCxOuj96lXPZ4CevaO6UwDOAUNhb6RbKDBUlLRYCgUIvIOSRK1wSztt+F5M7uKy6IMp4P/IVwXCDBrw+jwKwamB9EyIe3pyu8i4E7aPigGD83wcC2FEXxzLhHwxbHw4B4EOp0VabEXvfv4Yu62wWDKKV0PE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162273706472549.003820760924896; Thu, 3 Jun 2021 09:17:44 -0700 (PDT) Received: from localhost ([::1]:48024 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loq2R-00050R-Nr for importer2@patchew.org; Thu, 03 Jun 2021 12:17:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35964) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopl2-0001aA-7T for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:44 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:39708) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkz-0007EZ-5o for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:43 -0400 Received: by mail-wr1-x434.google.com with SMTP id l2so6391646wrw.6 for ; Thu, 03 Jun 2021 08:59:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TysIKDrUi/AEFUKTDKtgxqlH2Ug1XczQwdL8ralDjLo=; b=RKNokuZ5Zku/gdK4hPmziUp6vqi+glwRx2f3pvAImtgVh2Ht9ykOb3NzrNTkXGUc5P kiDqI/NieVpGGisaBK36BzvZxgNgcL/X9eBuJo7A/KY6TZ+cRvahXNDt0m5ftDbZoNB8 0MUVrT1u3HycAQmY5c1IveUutwAdTm1dvbQHgOazUUqfrBO0IFCx5rq1LSBvDOIwnCHh K5dBaNxxMcGHLBR3gnBPJ/B8nL9jjxfegrnV93WbHghL4jUa/EYlC5bJV9CO8TAlEcU8 HqQCCKJNreXLtsbTVHtKJzpwmmBmbd/F1yKKMBAQyQNkFZ2TbN1WTUzKbL9rixQ1Xq15 3rgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TysIKDrUi/AEFUKTDKtgxqlH2Ug1XczQwdL8ralDjLo=; b=J3/H/lmFPYDhB8DxRyhF9BqCcPyJ+VikYVyE3uaVi1WtLI+TeWc35r1PNk6zmGms8W lZ1d3qYXQX/6K0r8zMekOGXwpVf0+J8cHg6WygNURfdi06YZhgQ3fbhkUKTFQVC5eaSi jLh56vjYZ4UDZlWcpyINYEduGd9Z+eAXYrc1t652z7AvKN7Zxo7YpJ1fPcx/5PzW2wRE gLiR+o3h8+IfDI8GrDyXJEJiirnIj/W4pWUlk1m7zI2tOgNshjRIhYKd+gxPp4LjS+Gd p5Xgfdju9BYkFXs2P3NgvOYklA3KnRL5WdzNdAeZiswVR27ukyJ5CPA2b+9JwjQumwf+ DL6A== X-Gm-Message-State: AOAM5306LBAut+Bq7YgpsIatJoTePbmP5l5l8+Heuw02bTWLD5Lp87KX nHwcg0jpcqF4E4xtaIi6qC+9Kad8D6pWkxaC X-Google-Smtp-Source: ABdhPJyCRfb3xNuoez14ikCFHjafJ5iPl0neWtJTn41hnNtCa3klpl8mNwdgj/90/A8bJs126dKeaA== X-Received: by 2002:a5d:6546:: with SMTP id z6mr684252wrv.100.1622735979832; Thu, 03 Jun 2021 08:59:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/45] hvf: Make hvf_set_phys_mem() static Date: Thu, 3 Jun 2021 16:58:51 +0100 Message-Id: <20210603155904.26021-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alexander Graf The hvf_set_phys_mem() function is only called within the same file. Make it static. Signed-off-by: Alexander Graf Reviewed-by: Sergio Lopez Message-id: 20210519202253.76782-6-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/sysemu/hvf_int.h | 1 - accel/hvf/hvf-accel-ops.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index ef84a24dd96..d15fa3302a9 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -43,7 +43,6 @@ struct HVFState { }; extern HVFState *hvf_state; =20 -void hvf_set_phys_mem(MemoryRegionSection *, bool); void assert_hvf_ok(hv_return_t ret); hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); int hvf_put_registers(CPUState *); diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index c2136dfbb8c..5bec7b4d6dc 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -114,7 +114,7 @@ static int do_hvf_set_memory(hvf_slot *slot, hv_memory_= flags_t flags) return 0; } =20 -void hvf_set_phys_mem(MemoryRegionSection *section, bool add) +static void hvf_set_phys_mem(MemoryRegionSection *section, bool add) { hvf_slot *mem; MemoryRegion *area =3D section->mr; --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737977; cv=none; d=zohomail.com; s=zohoarc; b=n32Jp7+rKBNCWgcjRtbkB7PSxxlEFx10arZ4PuSU0eXT5soLbl+eSC1lNV645YU938acxQyKhPBwZUDGKdsSlTrnutbfl/t8hOedUE3rBeLj2myae/dv95K3xqzeKEP5m3M2LvLmjWqp3r07UfsffEftnleXq1UdO43ge9KPAiA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737977; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/Ll9YC3gq0ZRPtZyXFyJvlXQyvVNNe2QT4j+IfKDeno=; b=ZgbhYaztDOL+6eyNWJ/Dv6vRkIWE0DJ8QSbXNE+1rw1edWXNI/4PhdJEY+doNqWW50PCnBxHHtw7nUxmZE7Rb5ojn12QbJVkcU4sxr3ilQ5u01303lHLahrZuZud1BONHucoGtcnp89ponTtiNlQEpixUzfh8LHt/YtquMEkze4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737977234659.0146780863824; Thu, 3 Jun 2021 09:32:57 -0700 (PDT) Received: from localhost ([::1]:46294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loqHA-0002XA-3P for importer2@patchew.org; Thu, 03 Jun 2021 12:32:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopl1-0001Xr-Ok for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:43 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:41502) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopkz-0007FE-OL for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:43 -0400 Received: by mail-wr1-x42a.google.com with SMTP id h8so6356006wrz.8 for ; Thu, 03 Jun 2021 08:59:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/Ll9YC3gq0ZRPtZyXFyJvlXQyvVNNe2QT4j+IfKDeno=; b=j78OhndX4+41/3JlpnQNd4vKrvQwd9EcIHh18l4a8lwch0adzhe2rp9QG5b+65gPC9 zB4QcqNrF+uwGix7EikcxNi3S4mcFMtVOeQQSGDHSsPzYjFJ3bjDaJjS/w9FpllxQHaa SdSrwUvxrCsbaDfinG1leWtZlKwuXVoWRwRn88Y8cLnCChN/O7/6m0sR+NCKPNJUAzS9 YHSE8v/T6RXBJpqaSSSTmVvOq8P9HYVxIdluvwHzFucKANNDi1djtFaRh78LJix/vc1O UtnLl26dRjBN+9aJWYluKsQJ+z05WBtbRknoIPuAA+fPcGV/TNJWJnwoPl3KT6uHCr1g q13A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Ll9YC3gq0ZRPtZyXFyJvlXQyvVNNe2QT4j+IfKDeno=; b=YZhIoSu8p8vS8bWgDg5Ot5l+3xSHlujQP4kChXV1xZCM/Fd2mvL+zA50MEAz+7gFAc 24BbK0rS8KWTzbyMOxIi9tahRe/Clp6bYfTyo4KVpNbr/Dg9bnE7mfTuAI0lq+8d8Te+ f6hkChXxFWuSi79wbDz3P0Eg1kKGuzDyyG+Mcr7hIRRQHXCaAoGvkbfnx0RhoInDwfnr eBE+f59sQdkWqUmOTYMJmgou190rvUbhn/oZ7uA26XHH4jX0d1Lzf1bB4mrpQWoFT4Bf /XFcmBOn4NZqCQEU/dNe6sd0AG8WTyxOuG2NH+h4B5KUwkv52Mv2u3ko1JYwFCeJ5iTG W/VQ== X-Gm-Message-State: AOAM530rMsChDcEOnZRe8KMyQTcCBChXvmRuncy9uwR2jOKFYOXXmc9M btRYO77zDH6xUE592oAPHNAIenFGRh2fW6Qw X-Google-Smtp-Source: ABdhPJwUd67m+EoAHM7iH3S+u8TN+tEuxduhq+Uo/11Pk+iMoJ6T4TqM9rdddMLF+1RMJyTFIJ+fPQ== X-Received: by 2002:adf:f346:: with SMTP id e6mr624224wrp.179.1622735980410; Thu, 03 Jun 2021 08:59:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/45] hvf: Remove use of hv_uvaddr_t and hv_gpaddr_t Date: Thu, 3 Jun 2021 16:58:52 +0100 Message-Id: <20210603155904.26021-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alexander Graf The ARM version of Hypervisor.framework no longer defines these two types, so let's just revert to standard ones. Signed-off-by: Alexander Graf Reviewed-by: Sergio Lopez Message-id: 20210519202253.76782-7-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- accel/hvf/hvf-accel-ops.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 5bec7b4d6dc..7370fcfba09 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -109,7 +109,7 @@ static int do_hvf_set_memory(hvf_slot *slot, hv_memory_= flags_t flags) macslot->present =3D 1; macslot->gpa_start =3D slot->start; macslot->size =3D slot->size; - ret =3D hv_vm_map((hv_uvaddr_t)slot->mem, slot->start, slot->size, fla= gs); + ret =3D hv_vm_map(slot->mem, slot->start, slot->size, flags); assert_hvf_ok(ret); return 0; } @@ -253,12 +253,12 @@ static void hvf_set_dirty_tracking(MemoryRegionSectio= n *section, bool on) /* protect region against writes; begin tracking it */ if (on) { slot->flags |=3D HVF_SLOT_LOG; - hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size, + hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size, HV_MEMORY_READ); /* stop tracking region*/ } else { slot->flags &=3D ~HVF_SLOT_LOG; - hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size, + hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size, HV_MEMORY_READ | HV_MEMORY_WRITE); } } --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737559; cv=none; d=zohomail.com; s=zohoarc; b=Yef8NymBiEjiHL6WGtvR9q0F51Pv0UKtrjvJGo/MAhnfB7NQTKu5AcrU1i5FiOlQGA2HzDuFp/nne+bQ+SDyQW1JoDQXIjpYKDJ5s8nVcZMR6XIfj1k2VXM0HzJb4RAhOfsLS+nPoOufrQBsfOUU/K2hTIMaXDzulpzuwR0GXek= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737559; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=39zWw02n/PyDZkX7vmHiaIpTKhdewTRKIwY8LP7j41w=; b=XUFi8sWgrx2xjSJWsI42Y034QmaFtm7aVIErW0pRFuQu7S1WnlsOVuiA5uYMmh7gfYe3dKD9N/t8hzova1U1YmF+YOlpK0JHCnF9veI36s3l0lzK4NITRF/c7lrvvIyQ8v1hCSAZetJiQI5NoaHrqDJGneTQLuONL8hY0pAk8Fc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737559658331.3697154568962; Thu, 3 Jun 2021 09:25:59 -0700 (PDT) Received: from localhost ([::1]:48382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loqAQ-0001Em-IQ for importer2@patchew.org; Thu, 03 Jun 2021 12:25:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopl2-0001bw-Jl for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:44 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:39700) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopl0-0007G5-H6 for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:44 -0400 Received: by mail-wr1-x42b.google.com with SMTP id l2so6391727wrw.6 for ; Thu, 03 Jun 2021 08:59:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=39zWw02n/PyDZkX7vmHiaIpTKhdewTRKIwY8LP7j41w=; b=zsDXGUqLMe9N0zzE507fKKk/RxkaLykvjHtf7y1BpzZnXR5sIzValqIy3aILoklbhh PBHTJ+Xj21lAizTevfpOo/Y0131VuHnQEcuwCz+N8NefemY+pcna7OvQQmTqEqdrEvzZ YmvU/3SDh0eAc79cZImOPvko99FkJ+RhMQZbh9COyT8oM7cJR2lDX41i2hZ3EFuG16nm wtyYDEHl4r2/528Rvvivwza2mlkxUtEZmq70vipjCikyU7nX1eL7RkdJjBmFvQXuAV9G w/uBmD+q+CqAWbhev05Fsy7FGDK/DiF0Wvt7/Xy5SYAtAMwXqLfAJyayZ+QKHuGmR60a 71JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=39zWw02n/PyDZkX7vmHiaIpTKhdewTRKIwY8LP7j41w=; b=GBUGfn7GHnyDslg3iprBaa0XgXRQhobg3T77Qe5j1Nb2RNwws45UU2guhZjinIfrPI uQR1slZrs2Z1IjY5jiCJ7UwEUV0thUoLw3VkXS1doF0g7bgycNWhQOdlBnF2C8RHbVDJ j8SiL4ghNIiss/u4ee1xQBExtHPWQXd7Js53c9aq84e7rcw5w78CbroJ2uJ77tEgKacR eL9XqgwS7ZvVKzrBryAITktv22LEX33WM/vAqstBMmZRAjKVF4f4t+2CaF3JA6vF2iUf AGMralEaR1F4/SEHWIQ/E8MnBjaBYDknLp+3kf9YVGF+m+W3k1AghabRCxKRNq5GI2JR RkKQ== X-Gm-Message-State: AOAM530S/NCfXS3l3/NJI7HrVZriWb7CUrOLBJm44ATVc6MD9cSuqnHo 9mkSZsejyfD4GYm2iCyH/nJjDalu755d0bYn X-Google-Smtp-Source: ABdhPJzta6AcObu/vNH/xNMCCHhltlnF3UXlMxYqWDP4FD3zrNu6iIpfpVNj3wH6mLM6MjbjiwZEBw== X-Received: by 2002:adf:e109:: with SMTP id t9mr651201wrz.372.1622735981306; Thu, 03 Jun 2021 08:59:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/45] hvf: Split out common code on vcpu init and destroy Date: Thu, 3 Jun 2021 16:58:53 +0100 Message-Id: <20210603155904.26021-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alexander Graf Until now, Hypervisor.framework has only been available on x86_64 systems. With Apple Silicon shipping now, it extends its reach to aarch64. To prepare for support for multiple architectures, let's start moving common code out into its own accel directory. This patch splits the vcpu init and destroy functions into a generic and an architecture specific portion. This also allows us to move the generic functions into the generic hvf code, removing exported functions. Signed-off-by: Alexander Graf Reviewed-by: Sergio Lopez Message-id: 20210519202253.76782-8-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- accel/hvf/hvf-accel-ops.h | 2 -- include/sysemu/hvf_int.h | 2 ++ accel/hvf/hvf-accel-ops.c | 30 ++++++++++++++++++++++++++++++ target/i386/hvf/hvf.c | 23 ++--------------------- 4 files changed, 34 insertions(+), 23 deletions(-) diff --git a/accel/hvf/hvf-accel-ops.h b/accel/hvf/hvf-accel-ops.h index 8f992da1686..09fcf220676 100644 --- a/accel/hvf/hvf-accel-ops.h +++ b/accel/hvf/hvf-accel-ops.h @@ -12,12 +12,10 @@ =20 #include "sysemu/cpus.h" =20 -int hvf_init_vcpu(CPUState *); int hvf_vcpu_exec(CPUState *); void hvf_cpu_synchronize_state(CPUState *); void hvf_cpu_synchronize_post_reset(CPUState *); void hvf_cpu_synchronize_post_init(CPUState *); void hvf_cpu_synchronize_pre_loadvm(CPUState *); -void hvf_vcpu_destroy(CPUState *); =20 #endif /* HVF_CPUS_H */ diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index d15fa3302a9..80c1a8f9466 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -44,6 +44,8 @@ struct HVFState { extern HVFState *hvf_state; =20 void assert_hvf_ok(hv_return_t ret); +int hvf_arch_init_vcpu(CPUState *cpu); +void hvf_arch_vcpu_destroy(CPUState *cpu); hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); int hvf_put_registers(CPUState *); int hvf_get_registers(CPUState *); diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 7370fcfba09..b262efd8b6c 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -363,6 +363,36 @@ static void hvf_type_init(void) =20 type_init(hvf_type_init); =20 +static void hvf_vcpu_destroy(CPUState *cpu) +{ + hv_return_t ret =3D hv_vcpu_destroy(cpu->hvf_fd); + assert_hvf_ok(ret); + + hvf_arch_vcpu_destroy(cpu); +} + +static int hvf_init_vcpu(CPUState *cpu) +{ + int r; + + /* init cpu signals */ + sigset_t set; + struct sigaction sigact; + + memset(&sigact, 0, sizeof(sigact)); + sigact.sa_handler =3D dummy_signal; + sigaction(SIG_IPI, &sigact, NULL); + + pthread_sigmask(SIG_BLOCK, NULL, &set); + sigdelset(&set, SIG_IPI); + + r =3D hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT); + cpu->vcpu_dirty =3D 1; + assert_hvf_ok(r); + + return hvf_arch_init_vcpu(cpu); +} + /* * The HVF-specific vCPU thread function. This one should only run when th= e host * CPU supports the VMX "unrestricted guest" feature. diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 100ede2a4d7..c7132ee370c 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -158,14 +158,12 @@ static bool ept_emulation_fault(hvf_slot *slot, uint6= 4_t gpa, uint64_t ept_qual) return false; } =20 -void hvf_vcpu_destroy(CPUState *cpu) +void hvf_arch_vcpu_destroy(CPUState *cpu) { X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; =20 - hv_return_t ret =3D hv_vcpu_destroy((hv_vcpuid_t)cpu->hvf_fd); g_free(env->hvf_mmio_buf); - assert_hvf_ok(ret); } =20 static void init_tsc_freq(CPUX86State *env) @@ -210,23 +208,10 @@ static inline bool apic_bus_freq_is_known(CPUX86State= *env) return env->apic_bus_freq !=3D 0; } =20 -int hvf_init_vcpu(CPUState *cpu) +int hvf_arch_init_vcpu(CPUState *cpu) { - X86CPU *x86cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86cpu->env; - int r; - - /* init cpu signals */ - sigset_t set; - struct sigaction sigact; - - memset(&sigact, 0, sizeof(sigact)); - sigact.sa_handler =3D dummy_signal; - sigaction(SIG_IPI, &sigact, NULL); - - pthread_sigmask(SIG_BLOCK, NULL, &set); - sigdelset(&set, SIG_IPI); =20 init_emu(); init_decoder(); @@ -243,10 +228,6 @@ int hvf_init_vcpu(CPUState *cpu) } } =20 - r =3D hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT); - cpu->vcpu_dirty =3D 1; - assert_hvf_ok(r); - if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &hvf_state->hvf_caps->vmx_cap_pinbased)) { abort(); --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622736918; cv=none; d=zohomail.com; s=zohoarc; b=EOV0fzI3eXf3reB2p2zIkNaveI8ZqapzjmxWPUJquw5D0DZOyUJCzPcJ1+hLLtgqg/w13+FmaaqqpGxvqVBUC2qbuvxeDNmKNjg437FeptLo14cBJCTDSMYtIp70FAbeaoYsprgLbheny0hnXQJ0RZjK+ZBCMxmtHxeQXyL+4rw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622736918; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kjTsF2ypUW0HZAIutISGi0AwlU/2vgJVMA90PMqCH8M=; b=JK+BS2nzGdonQnxxVxkqY233aY8B/HcpwjhwMI2pgX7guacT0yjTlDNWamSLVcWUd4ccU6rr69xgvtAyL19SyAKmNOOPqJ3qi/0rSiVM61NTaAloQZWv58P90Jc+r4DB59Ona1PjcRLa4ah52mirMFqamvIIfrBY5xOUUMNzvFI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622736918891392.6923675776625; Thu, 3 Jun 2021 09:15:18 -0700 (PDT) Received: from localhost ([::1]:40388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loq05-0007mC-Op for importer2@patchew.org; Thu, 03 Jun 2021 12:15:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35988) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopl3-0001e3-42 for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:45 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:43599) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopl1-0007GK-8H for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:44 -0400 Received: by mail-wr1-x429.google.com with SMTP id u7so939724wrs.10 for ; Thu, 03 Jun 2021 08:59:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kjTsF2ypUW0HZAIutISGi0AwlU/2vgJVMA90PMqCH8M=; b=etxw9GArWuanxZ9gkNfuUJuhHJoXKiL3UR8zf2bHfnWlnZmpeMQmmAFkku8GlFHY9J A6bCtbfYHG5qvFgT7RE+wDkevSmv/Ht7v35pRsOZWLbUasI0h7yVOwFMe8lM3Dt8WiMY Jl0R2tlIb6H5PSfUMFe3W929AU7H/2XxUuh9Dy+g5Wg8sHdVZD7G+TM25/ZpO+EOgbEV o9fI765EYhvkI3KeBa8VHeEoldGjTYgL7il3cX7F7BC93T33yn/xtSm5UrN/UsaabRux yPP5bDinBfAoTEUllp8iEX/YdZ1fhnQUhf9P0UHhYMKNKl0+ytIxRN0R4ZH57cyWop4c WkWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kjTsF2ypUW0HZAIutISGi0AwlU/2vgJVMA90PMqCH8M=; b=S27ro/wjEOhmrB4u/F7q2R6T3gVOqTpJecIx1Xx0gHX4Yr8V6E6s513R2g1bCUBEbn 6pkeHDN3JqB5vyxR8MAW7H2A8wuUjpeOd09pFj7g5aBBR/E0sQbUJ+eY6KwhZv7l8BRl rVOb5Gd5pSOTTvls+Ho6Ff+XZWnjyaonbUJgTevOt7EQTpxO1QR7RkJPfZmopkmM5IkT njOLfkq2aibZiBDHKov3Cc+PqSYhd/j/jDlKjHsmxVyQl9QMbp7HgWllfMi+D+VBiJyG HE7kzStCmjgEiHsxKfMEL2ndXooef51wW5S9So7b9ptHMqVJzzyuSLq+Rnqzx0x991/t gHrg== X-Gm-Message-State: AOAM530UpfQr9FyaLD69Tecd59E3MlhXU+JJRV91+YYdMBdBHuK85o5p +w0xWccl6XpbV/qJ2BCUu7m27Y7fn4rc8+63 X-Google-Smtp-Source: ABdhPJwKuSFpoHG6nxNbdPk6OU+pQYMnelvEtQGYp9+0OhRXrHRvg1t9gJPL2O27+p6A7ThSICibiQ== X-Received: by 2002:adf:e401:: with SMTP id g1mr600272wrm.415.1622735981892; Thu, 03 Jun 2021 08:59:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/45] hvf: Use cpu_synchronize_state() Date: Thu, 3 Jun 2021 16:58:54 +0100 Message-Id: <20210603155904.26021-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alexander Graf There is no reason to call the hvf specific hvf_cpu_synchronize_state() when we can just use the generic cpu_synchronize_state() instead. This allows us to have less dependency on internal function definitions and allows us to make hvf_cpu_synchronize_state() static. Signed-off-by: Alexander Graf Reviewed-by: Sergio Lopez Message-id: 20210519202253.76782-9-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- accel/hvf/hvf-accel-ops.h | 1 - accel/hvf/hvf-accel-ops.c | 2 +- target/i386/hvf/x86hvf.c | 9 ++++----- 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/accel/hvf/hvf-accel-ops.h b/accel/hvf/hvf-accel-ops.h index 09fcf220676..f6192b56f0c 100644 --- a/accel/hvf/hvf-accel-ops.h +++ b/accel/hvf/hvf-accel-ops.h @@ -13,7 +13,6 @@ #include "sysemu/cpus.h" =20 int hvf_vcpu_exec(CPUState *); -void hvf_cpu_synchronize_state(CPUState *); void hvf_cpu_synchronize_post_reset(CPUState *); void hvf_cpu_synchronize_post_init(CPUState *); void hvf_cpu_synchronize_pre_loadvm(CPUState *); diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index b262efd8b6c..3b599ac57ce 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -200,7 +200,7 @@ static void do_hvf_cpu_synchronize_state(CPUState *cpu,= run_on_cpu_data arg) } } =20 -void hvf_cpu_synchronize_state(CPUState *cpu) +static void hvf_cpu_synchronize_state(CPUState *cpu) { if (!cpu->vcpu_dirty) { run_on_cpu(cpu, do_hvf_cpu_synchronize_state, RUN_ON_CPU_NULL); diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index 2b99f3eaa2d..cc381307ab9 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -26,14 +26,13 @@ #include "cpu.h" #include "x86_descr.h" #include "x86_decode.h" +#include "sysemu/hw_accel.h" =20 #include "hw/i386/apic_internal.h" =20 #include #include =20 -#include "accel/hvf/hvf-accel-ops.h" - void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr) { @@ -437,7 +436,7 @@ int hvf_process_events(CPUState *cpu_state) env->eflags =3D rreg(cpu_state->hvf_fd, HV_X86_RFLAGS); =20 if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) { - hvf_cpu_synchronize_state(cpu_state); + cpu_synchronize_state(cpu_state); do_cpu_init(cpu); } =20 @@ -451,12 +450,12 @@ int hvf_process_events(CPUState *cpu_state) cpu_state->halted =3D 0; } if (cpu_state->interrupt_request & CPU_INTERRUPT_SIPI) { - hvf_cpu_synchronize_state(cpu_state); + cpu_synchronize_state(cpu_state); do_cpu_sipi(cpu); } if (cpu_state->interrupt_request & CPU_INTERRUPT_TPR) { cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_TPR; - hvf_cpu_synchronize_state(cpu_state); + cpu_synchronize_state(cpu_state); apic_handle_tpr_access_report(cpu->apic_state, env->eip, env->tpr_access_type); } --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622738187; cv=none; d=zohomail.com; s=zohoarc; b=nXMcgH2krrPPtp4RoJgJYW7tRWq1JWYJinmKTlFA6LSUjs1tsgjRZ2Hac+VJlKkfEMNi2leNRa8Oh3QbFr6ofjGO0ZWeE3QRyETP3lUDJcYAy+QMcVsrY62Q1/SHX+peuGJAExKcnkzZkr4Z5g7rawQUr1/I147kMTolEip6+YE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622738187; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3PfyOcvq1w6hCVD63GrC8BHoocc1N1VvGMbNNUzkllA=; b=FHJPq9/dLybnc1vhqbdwoIok+zWl+U9knvXJYIVwk01BUp+dE2bF33egBoAnBABl2jCxYKsq+2k8bbkhYe3r0YwPfsh2GC6LSI9a5ew4PipUUGsoqBWEe68JXWaLAS29tpXYWrta2vSS5dyYVlccL5Nrlibb3fhHJD5NzL1hMFo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162273818794478.6824002459158; Thu, 3 Jun 2021 09:36:27 -0700 (PDT) Received: from localhost ([::1]:57660 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loqKY-00024K-OH for importer2@patchew.org; Thu, 03 Jun 2021 12:36:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36002) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopl4-0001k1-KE for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:46 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:39703) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopl1-0007Gt-TN for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:46 -0400 Received: by mail-wr1-x42e.google.com with SMTP id l2so6391798wrw.6 for ; Thu, 03 Jun 2021 08:59:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3PfyOcvq1w6hCVD63GrC8BHoocc1N1VvGMbNNUzkllA=; b=aDzczgryLDAFLWmtR9g4liN5IGG3wWLeRpfhX+wdK3WQNU8oaSSDDwX66KcOFbrUCh DWk57Lxt5vJAEQjSIoiwWwUSGenL6zqHz8o1CN4fCTAKZMeYJ1CtPnZtJn+TWVivtyzU 2/wEPRDfmzbybeBZJXCxL9T9EbgiPtmqCoTezD9vYwvFdWkLzsA/28gRQ+q23LQWWobN AzzoaAkEvpk1yYO7vfZ2JPw+v9jZx2rfDgU7V195tCn2youRIdXs+3KU2lyCXa+xKU+R 9B9DCbF0iRxjPEsTi8lKp1D5y8Nx5SDav4gdK3hH47vxqeEZYDN0GfEnmmhrOHNjuDs/ gtgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3PfyOcvq1w6hCVD63GrC8BHoocc1N1VvGMbNNUzkllA=; b=tpgb1J6NEvu+8taMeQlZ5p+k/X6oRO8fO2hyzROe+QQNh9Py0tNYVBCl5lRrbuclrl 8UvOxodB0cnnIQ8gd1y7oBGqOqattnSIpGVS3JZ8C5V9aS6uSPtC3wsMI6VuYubC6AzR H9oTzTSlfMrtO3Lr/SSIellebnQkIEW8k7yYR6wGPTOPox/USO2jf41k5u2si8pCDmrr 4PsCQW5qModCsKs5r2Qlvy+LPrqdxAhKWxe5K/pEIoyZij/x7NpQYiwSrqK+VtcPtsBA vCwN4oIGNFU34wMrnp+VQuN4PePLlGuZ91qzyA4Pdw9smA3w5nzWFpd/iOQkXQpZ8udo u3vg== X-Gm-Message-State: AOAM533yexIbYpbeGyK+gHhIDnHxyDX1rC3hnlxcKq9/2KlTVJfqmY6j nZIYaoLqBGrKR36jnAwIY/MsrbrMsmQ35nkV X-Google-Smtp-Source: ABdhPJzu/PbNwKZqbtmJOYAotRd5dWftFE4MX8S+umF1STtZdzUb8qAJVRd6iihEqPMGA2/VFYE7aA== X-Received: by 2002:a5d:46cb:: with SMTP id g11mr646531wrs.418.1622735982639; Thu, 03 Jun 2021 08:59:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/45] hvf: Make synchronize functions static Date: Thu, 3 Jun 2021 16:58:55 +0100 Message-Id: <20210603155904.26021-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alexander Graf The hvf accel synchronize functions are only used as input for local callback functions, so we can make them static. Signed-off-by: Alexander Graf Reviewed-by: Sergio Lopez Message-id: 20210519202253.76782-10-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- accel/hvf/hvf-accel-ops.h | 3 --- accel/hvf/hvf-accel-ops.c | 6 +++--- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/accel/hvf/hvf-accel-ops.h b/accel/hvf/hvf-accel-ops.h index f6192b56f0c..018a4e22f6d 100644 --- a/accel/hvf/hvf-accel-ops.h +++ b/accel/hvf/hvf-accel-ops.h @@ -13,8 +13,5 @@ #include "sysemu/cpus.h" =20 int hvf_vcpu_exec(CPUState *); -void hvf_cpu_synchronize_post_reset(CPUState *); -void hvf_cpu_synchronize_post_init(CPUState *); -void hvf_cpu_synchronize_pre_loadvm(CPUState *); =20 #endif /* HVF_CPUS_H */ diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 3b599ac57ce..69741ce7081 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -214,7 +214,7 @@ static void do_hvf_cpu_synchronize_post_reset(CPUState = *cpu, cpu->vcpu_dirty =3D false; } =20 -void hvf_cpu_synchronize_post_reset(CPUState *cpu) +static void hvf_cpu_synchronize_post_reset(CPUState *cpu) { run_on_cpu(cpu, do_hvf_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); } @@ -226,7 +226,7 @@ static void do_hvf_cpu_synchronize_post_init(CPUState *= cpu, cpu->vcpu_dirty =3D false; } =20 -void hvf_cpu_synchronize_post_init(CPUState *cpu) +static void hvf_cpu_synchronize_post_init(CPUState *cpu) { run_on_cpu(cpu, do_hvf_cpu_synchronize_post_init, RUN_ON_CPU_NULL); } @@ -237,7 +237,7 @@ static void do_hvf_cpu_synchronize_pre_loadvm(CPUState = *cpu, cpu->vcpu_dirty =3D true; } =20 -void hvf_cpu_synchronize_pre_loadvm(CPUState *cpu) +static void hvf_cpu_synchronize_pre_loadvm(CPUState *cpu) { run_on_cpu(cpu, do_hvf_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); } --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622738067; cv=none; d=zohomail.com; s=zohoarc; b=JyuFV33a4dz8bHvUG5cBEjHDl263LqoEB+yjZisMlWv6l/fDDT2P4Ap3YElV45hGKumILgZMPw/n9YJQ29vWOyCqi5nTKjcdN7k8M1/z0wflwt1QgZzEDDPIA82GpNWqf8DiHT+ilwJ4tuRbz7ZglgdzqtC199z0Dk/PtmsGO8w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622738067; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WjYQQ5KbIebYt2UlSAav3EDFRgbRHxYYXAO/kzuH6OE=; b=H+rh7NeDMPcUDLbA2WCGRpiSHw9qnluK3XEWNAUldQjsuzbR/Ro+sCzzzO1HYx06brbx/8nxCmRLTfDMB0Sxx/JSr21+7fj3L9j4xAvgrCkJ9TfiLxbjd4M4u7DtfSSIrDnYTsg5vfMp44OSvVUPj2iBPXVJAdSM3w/kaDkEeQE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622738067283843.9537437511758; Thu, 3 Jun 2021 09:34:27 -0700 (PDT) Received: from localhost ([::1]:51616 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loqIc-0006EJ-97 for importer2@patchew.org; Thu, 03 Jun 2021 12:34:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35996) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopl4-0001iC-6w for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:46 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:35643) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopl2-0007HP-HP for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:45 -0400 Received: by mail-wr1-x429.google.com with SMTP id m18so6401717wrv.2 for ; Thu, 03 Jun 2021 08:59:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WjYQQ5KbIebYt2UlSAav3EDFRgbRHxYYXAO/kzuH6OE=; b=wQM5FJWQbFDNMYx/N16t3/fkg4Kj6Q/017fDRAeGCbc1bqNJbX3j/qle7zWIgIZLR1 k+o4xXCJO118NKdLtYxqyzA4syVcpgd7h9AZ4Q8H3ms0rcjmYy8iHzfjqA2tcS5ZI9Z3 0baL1FDipdZUoZh+szYJxmE91z1itbKgPiG2ieBp516F51q7e/kAvtpgRIVMEWWmI85U jLzF3bJzcCigyxLNeqlrjEBwqhyQF6MeOuOmcTzWXos6kQHPeqR1OH9Y45BqGurocp// 801HEBel0yBRQn0iaO/F1OTWWT+7Uqez2qmNJJ7Uo8CQXy/CLDjgPR9ly07imgWSclVq LmRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WjYQQ5KbIebYt2UlSAav3EDFRgbRHxYYXAO/kzuH6OE=; b=kxqkSONYwgFce7jZZA4V0qGLcLHNAC+R78Fdm2Iu9iiA8ME5mjmWUK1uOFGhx7txov XZ8tJWJ1NAlSn36sEQCN7Sno3HqaJmLGxshNj/wgIAPsmpUxLPbsOVBw1wbtAOl8mszo wOOfaKCE2inj3Pxbh0BNV8NcPZE15sU/qJ/sJFZl/clvESA26/s07XAbyfHvmrMmCCBv 68X5aES7oGp7rabjHBpU0v9hScnUkAgCLMDow21Lk8o6jytVvzwVYYeBy+qbw2+TZZ3p Ev4QrOeLdM7mo1yISivWmDQXrF6vS+fjO/AuDbJvStZQH6vrGOiVwassZ/hdtD6rcP+r SmZA== X-Gm-Message-State: AOAM531lP+JjlchitesPBBd6Jh0TKma/0/58Z8P65Hp7NuMiXCIVxlVC vhrM6YsNIl04Vztx5H7LrkCwqfsTcPNPD9ss X-Google-Smtp-Source: ABdhPJwL/dVVvYXBT3dKj/PI8YI7h5hqXgIzz5ErvMGpcDz/Dh9fHYScf+tcYgcow5gEtBH11vMhRw== X-Received: by 2002:adf:ed8d:: with SMTP id c13mr683534wro.164.1622735983278; Thu, 03 Jun 2021 08:59:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/45] hvf: Remove hvf-accel-ops.h Date: Thu, 3 Jun 2021 16:58:56 +0100 Message-Id: <20210603155904.26021-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alexander Graf We can move the definition of hvf_vcpu_exec() into our internal hvf header, obsoleting the need for hvf-accel-ops.h. Signed-off-by: Alexander Graf Reviewed-by: Sergio Lopez Message-id: 20210519202253.76782-11-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- accel/hvf/hvf-accel-ops.h | 17 ----------------- include/sysemu/hvf_int.h | 1 + accel/hvf/hvf-accel-ops.c | 2 -- target/i386/hvf/hvf.c | 2 -- 4 files changed, 1 insertion(+), 21 deletions(-) delete mode 100644 accel/hvf/hvf-accel-ops.h diff --git a/accel/hvf/hvf-accel-ops.h b/accel/hvf/hvf-accel-ops.h deleted file mode 100644 index 018a4e22f6d..00000000000 --- a/accel/hvf/hvf-accel-ops.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Accelerator CPUS Interface - * - * Copyright 2020 SUSE LLC - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef HVF_CPUS_H -#define HVF_CPUS_H - -#include "sysemu/cpus.h" - -int hvf_vcpu_exec(CPUState *); - -#endif /* HVF_CPUS_H */ diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 80c1a8f9466..fd1dcaf26e0 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -46,6 +46,7 @@ extern HVFState *hvf_state; void assert_hvf_ok(hv_return_t ret); int hvf_arch_init_vcpu(CPUState *cpu); void hvf_arch_vcpu_destroy(CPUState *cpu); +int hvf_vcpu_exec(CPUState *); hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); int hvf_put_registers(CPUState *); int hvf_get_registers(CPUState *); diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 69741ce7081..14fc49791e3 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -58,8 +58,6 @@ #include "sysemu/runstate.h" #include "qemu/guest-random.h" =20 -#include "hvf-accel-ops.h" - HVFState *hvf_state; =20 /* Memory slots */ diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index c7132ee370c..02f7be6cfd6 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -73,8 +73,6 @@ #include "qemu/accel.h" #include "target/i386/cpu.h" =20 -#include "hvf-accel-ops.h" - void vmx_update_tpr(CPUState *cpu) { /* TODO: need integrate APIC handling */ --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737104; cv=none; d=zohomail.com; s=zohoarc; b=dhuYdryfNspuWoXh/B4E5BRYmvICpdoO2x5i7wxek2S9f0zPuP03SCO+asEUSzc5YblwKfm+iFvnCy50c2ymZjqXDIPr6Tf6dLM9sDM6pi8uTDR9Hh5ycHt1KrQFLSpizsox11+tvIcmkgr0Oj14LN+Dv0Gztyx/gYeTY2Or1AY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737104; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/kSuguXcs0FrY2UhvfAmnKBB6dWHJBBgHObcHLtul7A=; b=HKe4U1IJZbtRG+KThCbbi1aP41O0z0ezRI9XkhvH+S9ZQz6hnzwQsHl71SZgi7PZzv75k0f3bEDNva8jrOCupNAqga5OEAhwYlLt5h26HB3OOdlegFEA4qXHi7bO6MgIB3JFR4fry2VW47UNNDYFw4UThO8edubHV7WDdzexo6g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737104131363.30587116106676; Thu, 3 Jun 2021 09:18:24 -0700 (PDT) Received: from localhost ([::1]:49336 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loq34-0006Gy-IJ for importer2@patchew.org; Thu, 03 Jun 2021 12:18:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36086) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopl8-000222-Sh for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:50 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:52825) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopl4-0007I8-74 for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:50 -0400 Received: by mail-wm1-x32c.google.com with SMTP id f17so3716848wmf.2 for ; Thu, 03 Jun 2021 08:59:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/kSuguXcs0FrY2UhvfAmnKBB6dWHJBBgHObcHLtul7A=; b=M0X5VFYQujFkoY2NTzzZtFEBeSCJtrnKJsYTzjkWp63jTA14KaqJ9rQCNPx9kNNQLm ztKhqmsRNAPN6TVnra6htv7togiQM0mdOWm+oNS5XeM47JlbHSYYw5LaQH2PhSp6yh0Y RhVgrLzbGOrh+aBrC0+5g8D11hps1qIe7pikWcVFwQP4PGknf0/h0GGbwutJRD2Hs7zA 1BR7YVZ2pOahwFNviMRaQ3F8tYE6mHPs1GvPEUujzMjrez2PJ3kUFW3Kyia08elR1Lp5 Hkxg001nXWII5kiea9KawdNuxj+V9/9BUqgxd7BcqK0egCo7tnykTj4lQHurrSkUDE/4 Rkfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/kSuguXcs0FrY2UhvfAmnKBB6dWHJBBgHObcHLtul7A=; b=NfD77bk/x+YC28Ny1FOQjMC8uidiX1tfWozOyKoR37pPtthAFvAmm+4xaEFT4YyJY4 eZcb1+aXwUWuiJEfvfGEydVLm4dnCllezKsZ0aIzMhoYfqBtvk3B/dedNjnHiQq0f5zw pjFkQa1KzKWsYVc1xQ0depC/pGHxLOlVBgZec7FJmEcVHytIWLH3/JJbd2BBBAhECAly grScm+GCSrVez7Uv5YCfQOHYw2ZPHL2J23RqZiDBZd4xh1m8IguC9aexN/84Ylrtcv4U dtZdmm6hvC3FQetvGKS6/f2AhOKVRi9gVsn7rTD2xzXA8xAYavsGMRQZDJNwcPCA9WVc MtIg== X-Gm-Message-State: AOAM532xc6ODhjnKTPBcDv1khJZv8TUlrnPZo3F1NgUndAEsZh5CHYEE P/jC+nnAmA61OAwvSHRzXFcvChGrHozt2rV7 X-Google-Smtp-Source: ABdhPJwPq0dU34XNsbYwpqCj45Cgj3dDSiRz4q8duP6pmzgXAiEzyu1hlUTKh3aRbCZLdl8ursN6kw== X-Received: by 2002:a1c:ddc3:: with SMTP id u186mr10843686wmg.44.1622735984659; Thu, 03 Jun 2021 08:59:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/45] hvf: Introduce hvf vcpu struct Date: Thu, 3 Jun 2021 16:58:57 +0100 Message-Id: <20210603155904.26021-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Alexander Graf We will need more than a single field for hvf going forward. To keep the global vcpu struct uncluttered, let's allocate a special hvf vcpu struct, similar to how hax does it. Signed-off-by: Alexander Graf Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Sergio Lopez Message-id: 20210519202253.76782-12-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/core/cpu.h | 3 +- include/sysemu/hvf_int.h | 4 + target/i386/hvf/vmx.h | 24 +++-- accel/hvf/hvf-accel-ops.c | 8 +- target/i386/hvf/hvf.c | 104 +++++++++--------- target/i386/hvf/x86.c | 28 ++--- target/i386/hvf/x86_descr.c | 26 ++--- target/i386/hvf/x86_emu.c | 62 +++++------ target/i386/hvf/x86_mmu.c | 4 +- target/i386/hvf/x86_task.c | 12 +-- target/i386/hvf/x86hvf.c | 210 ++++++++++++++++++------------------ 11 files changed, 248 insertions(+), 237 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6b3bd3a1d4e..4e0ea68efcf 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -214,6 +214,7 @@ struct KVMState; struct kvm_run; =20 struct hax_vcpu_state; +struct hvf_vcpu_state; =20 #define TB_JMP_CACHE_BITS 12 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) @@ -406,7 +407,7 @@ struct CPUState { =20 struct hax_vcpu_state *hax_vcpu; =20 - int hvf_fd; + struct hvf_vcpu_state *hvf; =20 /* track IOMMUs whose translations we've cached in the TCG TLB */ GArray *iommu_notifiers; diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index fd1dcaf26e0..8b66a4e7d0d 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -43,6 +43,10 @@ struct HVFState { }; extern HVFState *hvf_state; =20 +struct hvf_vcpu_state { + int fd; +}; + void assert_hvf_ok(hv_return_t ret); int hvf_arch_init_vcpu(CPUState *cpu); void hvf_arch_vcpu_destroy(CPUState *cpu); diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index 24c4cdf0be0..6df87116f62 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -30,6 +30,8 @@ #include "vmcs.h" #include "cpu.h" #include "x86.h" +#include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" =20 #include "exec/address-spaces.h" =20 @@ -179,15 +181,15 @@ static inline void macvm_set_rip(CPUState *cpu, uint6= 4_t rip) uint64_t val; =20 /* BUG, should take considering overlap.. */ - wreg(cpu->hvf_fd, HV_X86_RIP, rip); + wreg(cpu->hvf->fd, HV_X86_RIP, rip); env->eip =3D rip; =20 /* after moving forward in rip, we need to clean INTERRUPTABILITY */ - val =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY); + val =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY); if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { env->hflags &=3D ~HF_INHIBIT_IRQ_MASK; - wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, + wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)); } @@ -199,9 +201,9 @@ static inline void vmx_clear_nmi_blocking(CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; =20 env->hflags2 &=3D ~HF2_NMI_MASK; - uint32_t gi =3D (uint32_t) rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBIL= ITY); + uint32_t gi =3D (uint32_t) rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBI= LITY); gi &=3D ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING; - wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi); + wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); } =20 static inline void vmx_set_nmi_blocking(CPUState *cpu) @@ -210,16 +212,16 @@ static inline void vmx_set_nmi_blocking(CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; =20 env->hflags2 |=3D HF2_NMI_MASK; - uint32_t gi =3D (uint32_t)rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILI= TY); + uint32_t gi =3D (uint32_t)rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBIL= ITY); gi |=3D VMCS_INTERRUPTIBILITY_NMI_BLOCKING; - wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi); + wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); } =20 static inline void vmx_set_nmi_window_exiting(CPUState *cpu) { uint64_t val; - val =3D rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | + val =3D rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); =20 } @@ -228,8 +230,8 @@ static inline void vmx_clear_nmi_window_exiting(CPUStat= e *cpu) { =20 uint64_t val; - val =3D rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & + val =3D rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); } =20 diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 14fc49791e3..ded918c443d 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -363,16 +363,20 @@ type_init(hvf_type_init); =20 static void hvf_vcpu_destroy(CPUState *cpu) { - hv_return_t ret =3D hv_vcpu_destroy(cpu->hvf_fd); + hv_return_t ret =3D hv_vcpu_destroy(cpu->hvf->fd); assert_hvf_ok(ret); =20 hvf_arch_vcpu_destroy(cpu); + g_free(cpu->hvf); + cpu->hvf =3D NULL; } =20 static int hvf_init_vcpu(CPUState *cpu) { int r; =20 + cpu->hvf =3D g_malloc0(sizeof(*cpu->hvf)); + /* init cpu signals */ sigset_t set; struct sigaction sigact; @@ -384,7 +388,7 @@ static int hvf_init_vcpu(CPUState *cpu) pthread_sigmask(SIG_BLOCK, NULL, &set); sigdelset(&set, SIG_IPI); =20 - r =3D hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT); + r =3D hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT); cpu->vcpu_dirty =3D 1; assert_hvf_ok(r); =20 diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 02f7be6cfd6..346dbcc26f4 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -80,11 +80,11 @@ void vmx_update_tpr(CPUState *cpu) int tpr =3D cpu_get_apic_tpr(x86_cpu->apic_state) << 4; int irr =3D apic_get_highest_priority_irr(x86_cpu->apic_state); =20 - wreg(cpu->hvf_fd, HV_X86_TPR, tpr); + wreg(cpu->hvf->fd, HV_X86_TPR, tpr); if (irr =3D=3D -1) { - wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0); + wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0); } else { - wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : + wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : irr >> 4); } } @@ -92,7 +92,7 @@ void vmx_update_tpr(CPUState *cpu) static void update_apic_tpr(CPUState *cpu) { X86CPU *x86_cpu =3D X86_CPU(cpu); - int tpr =3D rreg(cpu->hvf_fd, HV_X86_TPR) >> 4; + int tpr =3D rreg(cpu->hvf->fd, HV_X86_TPR) >> 4; cpu_set_apic_tpr(x86_cpu->apic_state, tpr); } =20 @@ -244,43 +244,43 @@ int hvf_arch_init_vcpu(CPUState *cpu) } =20 /* set VMCS control fields */ - wvmcs(cpu->hvf_fd, VMCS_PIN_BASED_CTLS, + wvmcs(cpu->hvf->fd, VMCS_PIN_BASED_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased, VMCS_PIN_BASED_CTLS_EXTINT | VMCS_PIN_BASED_CTLS_NMI | VMCS_PIN_BASED_CTLS_VNMI)); - wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, + wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased, VMCS_PRI_PROC_BASED_CTLS_HLT | VMCS_PRI_PROC_BASED_CTLS_MWAIT | VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET | VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) | VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL); - wvmcs(cpu->hvf_fd, VMCS_SEC_PROC_BASED_CTLS, + wvmcs(cpu->hvf->fd, VMCS_SEC_PROC_BASED_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES)); =20 - wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_= cap_entry, + wvmcs(cpu->hvf->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx= _cap_entry, 0)); - wvmcs(cpu->hvf_fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ + wvmcs(cpu->hvf->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ =20 - wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0); + wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0); =20 x86cpu =3D X86_CPU(cpu); x86cpu->env.xsave_buf =3D qemu_memalign(4096, 4096); =20 - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_STAR, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_LSTAR, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_CSTAR, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FMASK, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FSBASE, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_GSBASE, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_KERNELGSBASE, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_TSC_AUX, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_CS, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_EIP, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_ESP, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_STAR, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_LSTAR, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_CSTAR, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FMASK, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FSBASE, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_GSBASE, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_KERNELGSBASE, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_TSC_AUX, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_TSC, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, 1); =20 return 0; } @@ -321,16 +321,16 @@ static void hvf_store_events(CPUState *cpu, uint32_t = ins_len, uint64_t idtvec_in } if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { env->has_error_code =3D true; - env->error_code =3D rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_ERRO= R); + env->error_code =3D rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_ERR= OR); } } - if ((rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & + if ((rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) & VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) { env->hflags2 |=3D HF2_NMI_MASK; } else { env->hflags2 &=3D ~HF2_NMI_MASK; } - if (rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & + if (rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { env->hflags |=3D HF_INHIBIT_IRQ_MASK; @@ -409,20 +409,20 @@ int hvf_vcpu_exec(CPUState *cpu) return EXCP_HLT; } =20 - hv_return_t r =3D hv_vcpu_run(cpu->hvf_fd); + hv_return_t r =3D hv_vcpu_run(cpu->hvf->fd); assert_hvf_ok(r); =20 /* handle VMEXIT */ - uint64_t exit_reason =3D rvmcs(cpu->hvf_fd, VMCS_EXIT_REASON); - uint64_t exit_qual =3D rvmcs(cpu->hvf_fd, VMCS_EXIT_QUALIFICATION); - uint32_t ins_len =3D (uint32_t)rvmcs(cpu->hvf_fd, + uint64_t exit_reason =3D rvmcs(cpu->hvf->fd, VMCS_EXIT_REASON); + uint64_t exit_qual =3D rvmcs(cpu->hvf->fd, VMCS_EXIT_QUALIFICATION= ); + uint32_t ins_len =3D (uint32_t)rvmcs(cpu->hvf->fd, VMCS_EXIT_INSTRUCTION_LENGTH); =20 - uint64_t idtvec_info =3D rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INF= O); + uint64_t idtvec_info =3D rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_IN= FO); =20 hvf_store_events(cpu, ins_len, idtvec_info); - rip =3D rreg(cpu->hvf_fd, HV_X86_RIP); - env->eflags =3D rreg(cpu->hvf_fd, HV_X86_RFLAGS); + rip =3D rreg(cpu->hvf->fd, HV_X86_RIP); + env->eflags =3D rreg(cpu->hvf->fd, HV_X86_RFLAGS); =20 qemu_mutex_lock_iothread(); =20 @@ -452,7 +452,7 @@ int hvf_vcpu_exec(CPUState *cpu) case EXIT_REASON_EPT_FAULT: { hvf_slot *slot; - uint64_t gpa =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRES= S); + uint64_t gpa =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_PHYSICAL_ADDRE= SS); =20 if (((idtvec_info & VMCS_IDT_VEC_VALID) =3D=3D 0) && ((exit_qual & EXIT_QUAL_NMIUDTI) !=3D 0)) { @@ -497,7 +497,7 @@ int hvf_vcpu_exec(CPUState *cpu) store_regs(cpu); break; } else if (!string && !in) { - RAX(env) =3D rreg(cpu->hvf_fd, HV_X86_RAX); + RAX(env) =3D rreg(cpu->hvf->fd, HV_X86_RAX); hvf_handle_io(env, port, &RAX(env), 1, size, 1); macvm_set_rip(cpu, rip + ins_len); break; @@ -513,21 +513,21 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_CPUID: { - uint32_t rax =3D (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX); - uint32_t rbx =3D (uint32_t)rreg(cpu->hvf_fd, HV_X86_RBX); - uint32_t rcx =3D (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX); - uint32_t rdx =3D (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX); + uint32_t rax =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX); + uint32_t rbx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RBX); + uint32_t rcx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX); + uint32_t rdx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX); =20 if (rax =3D=3D 1) { /* CPUID1.ecx.OSXSAVE needs to know CR4 */ - env->cr[4] =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_CR4); + env->cr[4] =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4); } hvf_cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx); =20 - wreg(cpu->hvf_fd, HV_X86_RAX, rax); - wreg(cpu->hvf_fd, HV_X86_RBX, rbx); - wreg(cpu->hvf_fd, HV_X86_RCX, rcx); - wreg(cpu->hvf_fd, HV_X86_RDX, rdx); + wreg(cpu->hvf->fd, HV_X86_RAX, rax); + wreg(cpu->hvf->fd, HV_X86_RBX, rbx); + wreg(cpu->hvf->fd, HV_X86_RCX, rcx); + wreg(cpu->hvf->fd, HV_X86_RDX, rdx); =20 macvm_set_rip(cpu, rip + ins_len); break; @@ -535,16 +535,16 @@ int hvf_vcpu_exec(CPUState *cpu) case EXIT_REASON_XSETBV: { X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; - uint32_t eax =3D (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX); - uint32_t ecx =3D (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX); - uint32_t edx =3D (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX); + uint32_t eax =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX); + uint32_t ecx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX); + uint32_t edx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX); =20 if (ecx) { macvm_set_rip(cpu, rip + ins_len); break; } env->xcr0 =3D ((uint64_t)edx << 32) | eax; - wreg(cpu->hvf_fd, HV_X86_XCR0, env->xcr0 | 1); + wreg(cpu->hvf->fd, HV_X86_XCR0, env->xcr0 | 1); macvm_set_rip(cpu, rip + ins_len); break; } @@ -583,11 +583,11 @@ int hvf_vcpu_exec(CPUState *cpu) =20 switch (cr) { case 0x0: { - macvm_set_cr0(cpu->hvf_fd, RRX(env, reg)); + macvm_set_cr0(cpu->hvf->fd, RRX(env, reg)); break; } case 4: { - macvm_set_cr4(cpu->hvf_fd, RRX(env, reg)); + macvm_set_cr4(cpu->hvf->fd, RRX(env, reg)); break; } case 8: { @@ -623,7 +623,7 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_TASK_SWITCH: { - uint64_t vinfo =3D rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO); + uint64_t vinfo =3D rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO= ); x68_segment_selector sel =3D {.sel =3D exit_qual & 0xffff}; vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3, vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, = vinfo @@ -636,8 +636,8 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_RDPMC: - wreg(cpu->hvf_fd, HV_X86_RAX, 0); - wreg(cpu->hvf_fd, HV_X86_RDX, 0); + wreg(cpu->hvf->fd, HV_X86_RAX, 0); + wreg(cpu->hvf->fd, HV_X86_RDX, 0); macvm_set_rip(cpu, rip + ins_len); break; case VMX_REASON_VMCALL: diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c index cd045183a81..2898bb70a84 100644 --- a/target/i386/hvf/x86.c +++ b/target/i386/hvf/x86.c @@ -62,11 +62,11 @@ bool x86_read_segment_descriptor(struct CPUState *cpu, } =20 if (GDT_SEL =3D=3D sel.ti) { - base =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE); - limit =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT); + base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE); + limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT); } else { - base =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE); - limit =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT); + base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE); + limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT); } =20 if (sel.index * 8 >=3D limit) { @@ -85,11 +85,11 @@ bool x86_write_segment_descriptor(struct CPUState *cpu, uint32_t limit; =20 if (GDT_SEL =3D=3D sel.ti) { - base =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE); - limit =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT); + base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE); + limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT); } else { - base =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE); - limit =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT); + base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE); + limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT); } =20 if (sel.index * 8 >=3D limit) { @@ -103,8 +103,8 @@ bool x86_write_segment_descriptor(struct CPUState *cpu, bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_de= sc, int gate) { - target_ulong base =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_BASE); - uint32_t limit =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_LIMIT); + target_ulong base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_BASE); + uint32_t limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_LIMIT); =20 memset(idt_desc, 0, sizeof(*idt_desc)); if (gate * 8 >=3D limit) { @@ -118,7 +118,7 @@ bool x86_read_call_gate(struct CPUState *cpu, struct x8= 6_call_gate *idt_desc, =20 bool x86_is_protected(struct CPUState *cpu) { - uint64_t cr0 =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0); + uint64_t cr0 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); return cr0 & CR0_PE; } =20 @@ -136,7 +136,7 @@ bool x86_is_v8086(struct CPUState *cpu) =20 bool x86_is_long_mode(struct CPUState *cpu) { - return rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; + return rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; } =20 bool x86_is_long64_mode(struct CPUState *cpu) @@ -149,13 +149,13 @@ bool x86_is_long64_mode(struct CPUState *cpu) =20 bool x86_is_paging_mode(struct CPUState *cpu) { - uint64_t cr0 =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0); + uint64_t cr0 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); return cr0 & CR0_PG; } =20 bool x86_is_pae_enabled(struct CPUState *cpu) { - uint64_t cr4 =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_CR4); + uint64_t cr4 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4); return cr4 & CR4_PAE; } =20 diff --git a/target/i386/hvf/x86_descr.c b/target/i386/hvf/x86_descr.c index 9f539e73f6d..af15c06ac5d 100644 --- a/target/i386/hvf/x86_descr.c +++ b/target/i386/hvf/x86_descr.c @@ -48,47 +48,47 @@ static const struct vmx_segment_field { =20 uint32_t vmx_read_segment_limit(CPUState *cpu, X86Seg seg) { - return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit); + return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit); } =20 uint32_t vmx_read_segment_ar(CPUState *cpu, X86Seg seg) { - return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes); + return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes); } =20 uint64_t vmx_read_segment_base(CPUState *cpu, X86Seg seg) { - return rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base); + return rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base); } =20 x68_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg) { x68_segment_selector sel; - sel.sel =3D rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector); + sel.sel =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector); return sel; } =20 void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector= selector, X86Seg seg) { - wvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector, selector.sel); + wvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector, selector.sel); } =20 void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment = *desc, X86Seg seg) { - desc->sel =3D rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector); - desc->base =3D rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base); - desc->limit =3D rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit); - desc->ar =3D rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes); + desc->sel =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector); + desc->base =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base); + desc->limit =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit); + desc->ar =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes); } =20 void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc,= X86Seg seg) { const struct vmx_segment_field *sf =3D &vmx_segment_fields[seg]; =20 - wvmcs(cpu->hvf_fd, sf->base, desc->base); - wvmcs(cpu->hvf_fd, sf->limit, desc->limit); - wvmcs(cpu->hvf_fd, sf->selector, desc->sel); - wvmcs(cpu->hvf_fd, sf->ar_bytes, desc->ar); + wvmcs(cpu->hvf->fd, sf->base, desc->base); + wvmcs(cpu->hvf->fd, sf->limit, desc->limit); + wvmcs(cpu->hvf->fd, sf->selector, desc->sel); + wvmcs(cpu->hvf->fd, sf->ar_bytes, desc->ar); } =20 void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selec= tor selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_= desc) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index e52c39ddb1f..7c8203b21fb 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -674,7 +674,7 @@ void simulate_rdmsr(struct CPUState *cpu) =20 switch (msr) { case MSR_IA32_TSC: - val =3D rdtscp() + rvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET); + val =3D rdtscp() + rvmcs(cpu->hvf->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: val =3D cpu_get_apic_base(X86_CPU(cpu)->apic_state); @@ -683,16 +683,16 @@ void simulate_rdmsr(struct CPUState *cpu) val =3D x86_cpu->ucode_rev; break; case MSR_EFER: - val =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER); + val =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER); break; case MSR_FSBASE: - val =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE); + val =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE); break; case MSR_GSBASE: - val =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE); + val =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE); break; case MSR_KERNELGSBASE: - val =3D rvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE); + val =3D rvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE); break; case MSR_STAR: abort(); @@ -780,13 +780,13 @@ void simulate_wrmsr(struct CPUState *cpu) cpu_set_apic_base(X86_CPU(cpu)->apic_state, data); break; case MSR_FSBASE: - wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, data); + wvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE, data); break; case MSR_GSBASE: - wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, data); + wvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE, data); break; case MSR_KERNELGSBASE: - wvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE, data); + wvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE, data); break; case MSR_STAR: abort(); @@ -799,9 +799,9 @@ void simulate_wrmsr(struct CPUState *cpu) break; case MSR_EFER: /*printf("new efer %llx\n", EFER(cpu));*/ - wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, data); + wvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER, data); if (data & MSR_EFER_NXE) { - hv_vcpu_invalidate_tlb(cpu->hvf_fd); + hv_vcpu_invalidate_tlb(cpu->hvf->fd); } break; case MSR_MTRRphysBase(0): @@ -1425,21 +1425,21 @@ void load_regs(struct CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; =20 int i =3D 0; - RRX(env, R_EAX) =3D rreg(cpu->hvf_fd, HV_X86_RAX); - RRX(env, R_EBX) =3D rreg(cpu->hvf_fd, HV_X86_RBX); - RRX(env, R_ECX) =3D rreg(cpu->hvf_fd, HV_X86_RCX); - RRX(env, R_EDX) =3D rreg(cpu->hvf_fd, HV_X86_RDX); - RRX(env, R_ESI) =3D rreg(cpu->hvf_fd, HV_X86_RSI); - RRX(env, R_EDI) =3D rreg(cpu->hvf_fd, HV_X86_RDI); - RRX(env, R_ESP) =3D rreg(cpu->hvf_fd, HV_X86_RSP); - RRX(env, R_EBP) =3D rreg(cpu->hvf_fd, HV_X86_RBP); + RRX(env, R_EAX) =3D rreg(cpu->hvf->fd, HV_X86_RAX); + RRX(env, R_EBX) =3D rreg(cpu->hvf->fd, HV_X86_RBX); + RRX(env, R_ECX) =3D rreg(cpu->hvf->fd, HV_X86_RCX); + RRX(env, R_EDX) =3D rreg(cpu->hvf->fd, HV_X86_RDX); + RRX(env, R_ESI) =3D rreg(cpu->hvf->fd, HV_X86_RSI); + RRX(env, R_EDI) =3D rreg(cpu->hvf->fd, HV_X86_RDI); + RRX(env, R_ESP) =3D rreg(cpu->hvf->fd, HV_X86_RSP); + RRX(env, R_EBP) =3D rreg(cpu->hvf->fd, HV_X86_RBP); for (i =3D 8; i < 16; i++) { - RRX(env, i) =3D rreg(cpu->hvf_fd, HV_X86_RAX + i); + RRX(env, i) =3D rreg(cpu->hvf->fd, HV_X86_RAX + i); } =20 - env->eflags =3D rreg(cpu->hvf_fd, HV_X86_RFLAGS); + env->eflags =3D rreg(cpu->hvf->fd, HV_X86_RFLAGS); rflags_to_lflags(env); - env->eip =3D rreg(cpu->hvf_fd, HV_X86_RIP); + env->eip =3D rreg(cpu->hvf->fd, HV_X86_RIP); } =20 void store_regs(struct CPUState *cpu) @@ -1448,20 +1448,20 @@ void store_regs(struct CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; =20 int i =3D 0; - wreg(cpu->hvf_fd, HV_X86_RAX, RAX(env)); - wreg(cpu->hvf_fd, HV_X86_RBX, RBX(env)); - wreg(cpu->hvf_fd, HV_X86_RCX, RCX(env)); - wreg(cpu->hvf_fd, HV_X86_RDX, RDX(env)); - wreg(cpu->hvf_fd, HV_X86_RSI, RSI(env)); - wreg(cpu->hvf_fd, HV_X86_RDI, RDI(env)); - wreg(cpu->hvf_fd, HV_X86_RBP, RBP(env)); - wreg(cpu->hvf_fd, HV_X86_RSP, RSP(env)); + wreg(cpu->hvf->fd, HV_X86_RAX, RAX(env)); + wreg(cpu->hvf->fd, HV_X86_RBX, RBX(env)); + wreg(cpu->hvf->fd, HV_X86_RCX, RCX(env)); + wreg(cpu->hvf->fd, HV_X86_RDX, RDX(env)); + wreg(cpu->hvf->fd, HV_X86_RSI, RSI(env)); + wreg(cpu->hvf->fd, HV_X86_RDI, RDI(env)); + wreg(cpu->hvf->fd, HV_X86_RBP, RBP(env)); + wreg(cpu->hvf->fd, HV_X86_RSP, RSP(env)); for (i =3D 8; i < 16; i++) { - wreg(cpu->hvf_fd, HV_X86_RAX + i, RRX(env, i)); + wreg(cpu->hvf->fd, HV_X86_RAX + i, RRX(env, i)); } =20 lflags_to_rflags(env); - wreg(cpu->hvf_fd, HV_X86_RFLAGS, env->eflags); + wreg(cpu->hvf->fd, HV_X86_RFLAGS, env->eflags); macvm_set_rip(cpu, env->eip); } =20 diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index 78fff046845..e9ed0f5aa10 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -127,7 +127,7 @@ static bool test_pt_entry(struct CPUState *cpu, struct = gpt_translation *pt, pt->err_code |=3D MMU_PAGE_PT; } =20 - uint32_t cr0 =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0); + uint32_t cr0 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); /* check protection */ if (cr0 & CR0_WP) { if (pt->write_access && !pte_write_access(pte)) { @@ -172,7 +172,7 @@ static bool walk_gpt(struct CPUState *cpu, target_ulong= addr, int err_code, { int top_level, level; bool is_large =3D false; - target_ulong cr3 =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_CR3); + target_ulong cr3 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR3); uint64_t page_mask =3D pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK; =20 memset(pt, 0, sizeof(*pt)); diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index d66dfd76690..422156128b7 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -62,7 +62,7 @@ static void load_state_from_tss32(CPUState *cpu, struct x= 86_tss_segment32 *tss) X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; =20 - wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, tss->cr3); + wvmcs(cpu->hvf->fd, VMCS_GUEST_CR3, tss->cr3); =20 env->eip =3D tss->eip; env->eflags =3D tss->eflags | 2; @@ -111,11 +111,11 @@ static int task_switch_32(CPUState *cpu, x68_segment_= selector tss_sel, x68_segme =20 void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, i= nt reason, bool gate_valid, uint8_t gate, uint64_t gate_type) { - uint64_t rip =3D rreg(cpu->hvf_fd, HV_X86_RIP); + uint64_t rip =3D rreg(cpu->hvf->fd, HV_X86_RIP); if (!gate_valid || (gate_type !=3D VMCS_INTR_T_HWEXCEPTION && gate_type !=3D VMCS_INTR_T_HWINTR && gate_type !=3D VMCS_INTR_T_NMI)) { - int ins_len =3D rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH); + int ins_len =3D rvmcs(cpu->hvf->fd, VMCS_EXIT_INSTRUCTION_LENGTH); macvm_set_rip(cpu, rip + ins_len); return; } @@ -174,12 +174,12 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segmen= t_selector tss_sel, int rea //ret =3D task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, = &next_tss_desc); VM_PANIC("task_switch_16"); =20 - macvm_set_cr0(cpu->hvf_fd, rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS= ); + macvm_set_cr0(cpu->hvf->fd, rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0) | CR0_= TS); x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg); vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR); =20 store_regs(cpu); =20 - hv_vcpu_invalidate_tlb(cpu->hvf_fd); - hv_vcpu_flush(cpu->hvf_fd); + hv_vcpu_invalidate_tlb(cpu->hvf->fd); + hv_vcpu_flush(cpu->hvf->fd); } diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index cc381307ab9..28cfee4f608 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -80,7 +80,7 @@ void hvf_put_xsave(CPUState *cpu_state) =20 x86_cpu_xsave_all_areas(X86_CPU(cpu_state), xsave); =20 - if (hv_vcpu_write_fpstate(cpu_state->hvf_fd, (void*)xsave, 4096)) { + if (hv_vcpu_write_fpstate(cpu_state->hvf->fd, (void*)xsave, 4096)) { abort(); } } @@ -90,19 +90,19 @@ void hvf_put_segments(CPUState *cpu_state) CPUX86State *env =3D &X86_CPU(cpu_state)->env; struct vmx_segment seg; =20 - wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); - wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE, env->idt.base); + wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); + wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); =20 - wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); - wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); + wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); + wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); =20 - /* wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR2, env->cr[2]); */ - wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3, env->cr[3]); + /* wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */ + wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3, env->cr[3]); vmx_update_tpr(cpu_state); - wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER, env->efer); + wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer); =20 - macvm_set_cr4(cpu_state->hvf_fd, env->cr[4]); - macvm_set_cr0(cpu_state->hvf_fd, env->cr[0]); + macvm_set_cr4(cpu_state->hvf->fd, env->cr[4]); + macvm_set_cr0(cpu_state->hvf->fd, env->cr[0]); =20 hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false); vmx_write_segment_descriptor(cpu_state, &seg, R_CS); @@ -128,31 +128,31 @@ void hvf_put_segments(CPUState *cpu_state) hvf_set_segment(cpu_state, &seg, &env->ldt, false); vmx_write_segment_descriptor(cpu_state, &seg, R_LDTR); =20 - hv_vcpu_flush(cpu_state->hvf_fd); + hv_vcpu_flush(cpu_state->hvf->fd); } =20 void hvf_put_msrs(CPUState *cpu_state) { CPUX86State *env =3D &X86_CPU(cpu_state)->env; =20 - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, env->sysenter_cs); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, env->sysenter_esp); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, env->sysenter_eip); =20 - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_STAR, env->star); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_STAR, env->star); =20 #ifdef TARGET_X86_64 - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_CSTAR, env->cstar); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_KERNELGSBASE, env->kernelgsba= se); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FMASK, env->fmask); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_LSTAR, env->lstar); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_CSTAR, env->cstar); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, env->kernelgsb= ase); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FMASK, env->fmask); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_LSTAR, env->lstar); #endif =20 - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_GSBASE, env->segs[R_GS].base); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FSBASE, env->segs[R_FS].base); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_GSBASE, env->segs[R_GS].base= ); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FSBASE, env->segs[R_FS].base= ); } =20 =20 @@ -162,7 +162,7 @@ void hvf_get_xsave(CPUState *cpu_state) =20 xsave =3D X86_CPU(cpu_state)->env.xsave_buf; =20 - if (hv_vcpu_read_fpstate(cpu_state->hvf_fd, (void*)xsave, 4096)) { + if (hv_vcpu_read_fpstate(cpu_state->hvf->fd, (void*)xsave, 4096)) { abort(); } =20 @@ -201,17 +201,17 @@ void hvf_get_segments(CPUState *cpu_state) vmx_read_segment_descriptor(cpu_state, &seg, R_LDTR); hvf_get_segment(&env->ldt, &seg); =20 - env->idt.limit =3D rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT); - env->idt.base =3D rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE); - env->gdt.limit =3D rvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT); - env->gdt.base =3D rvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE); + env->idt.limit =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT); + env->idt.base =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE); + env->gdt.limit =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT); + env->gdt.base =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE); =20 - env->cr[0] =3D rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR0); + env->cr[0] =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR0); env->cr[2] =3D 0; - env->cr[3] =3D rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3); - env->cr[4] =3D rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR4); + env->cr[3] =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3); + env->cr[4] =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR4); =20 - env->efer =3D rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER); + env->efer =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER); } =20 void hvf_get_msrs(CPUState *cpu_state) @@ -219,27 +219,27 @@ void hvf_get_msrs(CPUState *cpu_state) CPUX86State *env =3D &X86_CPU(cpu_state)->env; uint64_t tmp; =20 - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, &tmp); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp); env->sysenter_cs =3D tmp; =20 - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, &tmp); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp); env->sysenter_esp =3D tmp; =20 - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, &tmp); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp); env->sysenter_eip =3D tmp; =20 - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_STAR, &env->star); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_STAR, &env->star); =20 #ifdef TARGET_X86_64 - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_CSTAR, &env->cstar); - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_KERNELGSBASE, &env->kernelgsba= se); - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_FMASK, &env->fmask); - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_LSTAR, &env->lstar); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_CSTAR, &env->cstar); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsb= ase); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_FMASK, &env->fmask); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_LSTAR, &env->lstar); #endif =20 - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_APICBASE, &tmp); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_APICBASE, &tmp); =20 - env->tsc =3D rdtscp() + rvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET); + env->tsc =3D rdtscp() + rvmcs(cpu_state->hvf->fd, VMCS_TSC_OFFSET); } =20 int hvf_put_registers(CPUState *cpu_state) @@ -247,26 +247,26 @@ int hvf_put_registers(CPUState *cpu_state) X86CPU *x86cpu =3D X86_CPU(cpu_state); CPUX86State *env =3D &x86cpu->env; =20 - wreg(cpu_state->hvf_fd, HV_X86_RAX, env->regs[R_EAX]); - wreg(cpu_state->hvf_fd, HV_X86_RBX, env->regs[R_EBX]); - wreg(cpu_state->hvf_fd, HV_X86_RCX, env->regs[R_ECX]); - wreg(cpu_state->hvf_fd, HV_X86_RDX, env->regs[R_EDX]); - wreg(cpu_state->hvf_fd, HV_X86_RBP, env->regs[R_EBP]); - wreg(cpu_state->hvf_fd, HV_X86_RSP, env->regs[R_ESP]); - wreg(cpu_state->hvf_fd, HV_X86_RSI, env->regs[R_ESI]); - wreg(cpu_state->hvf_fd, HV_X86_RDI, env->regs[R_EDI]); - wreg(cpu_state->hvf_fd, HV_X86_R8, env->regs[8]); - wreg(cpu_state->hvf_fd, HV_X86_R9, env->regs[9]); - wreg(cpu_state->hvf_fd, HV_X86_R10, env->regs[10]); - wreg(cpu_state->hvf_fd, HV_X86_R11, env->regs[11]); - wreg(cpu_state->hvf_fd, HV_X86_R12, env->regs[12]); - wreg(cpu_state->hvf_fd, HV_X86_R13, env->regs[13]); - wreg(cpu_state->hvf_fd, HV_X86_R14, env->regs[14]); - wreg(cpu_state->hvf_fd, HV_X86_R15, env->regs[15]); - wreg(cpu_state->hvf_fd, HV_X86_RFLAGS, env->eflags); - wreg(cpu_state->hvf_fd, HV_X86_RIP, env->eip); + wreg(cpu_state->hvf->fd, HV_X86_RAX, env->regs[R_EAX]); + wreg(cpu_state->hvf->fd, HV_X86_RBX, env->regs[R_EBX]); + wreg(cpu_state->hvf->fd, HV_X86_RCX, env->regs[R_ECX]); + wreg(cpu_state->hvf->fd, HV_X86_RDX, env->regs[R_EDX]); + wreg(cpu_state->hvf->fd, HV_X86_RBP, env->regs[R_EBP]); + wreg(cpu_state->hvf->fd, HV_X86_RSP, env->regs[R_ESP]); + wreg(cpu_state->hvf->fd, HV_X86_RSI, env->regs[R_ESI]); + wreg(cpu_state->hvf->fd, HV_X86_RDI, env->regs[R_EDI]); + wreg(cpu_state->hvf->fd, HV_X86_R8, env->regs[8]); + wreg(cpu_state->hvf->fd, HV_X86_R9, env->regs[9]); + wreg(cpu_state->hvf->fd, HV_X86_R10, env->regs[10]); + wreg(cpu_state->hvf->fd, HV_X86_R11, env->regs[11]); + wreg(cpu_state->hvf->fd, HV_X86_R12, env->regs[12]); + wreg(cpu_state->hvf->fd, HV_X86_R13, env->regs[13]); + wreg(cpu_state->hvf->fd, HV_X86_R14, env->regs[14]); + wreg(cpu_state->hvf->fd, HV_X86_R15, env->regs[15]); + wreg(cpu_state->hvf->fd, HV_X86_RFLAGS, env->eflags); + wreg(cpu_state->hvf->fd, HV_X86_RIP, env->eip); =20 - wreg(cpu_state->hvf_fd, HV_X86_XCR0, env->xcr0); + wreg(cpu_state->hvf->fd, HV_X86_XCR0, env->xcr0); =20 hvf_put_xsave(cpu_state); =20 @@ -274,14 +274,14 @@ int hvf_put_registers(CPUState *cpu_state) =20 hvf_put_msrs(cpu_state); =20 - wreg(cpu_state->hvf_fd, HV_X86_DR0, env->dr[0]); - wreg(cpu_state->hvf_fd, HV_X86_DR1, env->dr[1]); - wreg(cpu_state->hvf_fd, HV_X86_DR2, env->dr[2]); - wreg(cpu_state->hvf_fd, HV_X86_DR3, env->dr[3]); - wreg(cpu_state->hvf_fd, HV_X86_DR4, env->dr[4]); - wreg(cpu_state->hvf_fd, HV_X86_DR5, env->dr[5]); - wreg(cpu_state->hvf_fd, HV_X86_DR6, env->dr[6]); - wreg(cpu_state->hvf_fd, HV_X86_DR7, env->dr[7]); + wreg(cpu_state->hvf->fd, HV_X86_DR0, env->dr[0]); + wreg(cpu_state->hvf->fd, HV_X86_DR1, env->dr[1]); + wreg(cpu_state->hvf->fd, HV_X86_DR2, env->dr[2]); + wreg(cpu_state->hvf->fd, HV_X86_DR3, env->dr[3]); + wreg(cpu_state->hvf->fd, HV_X86_DR4, env->dr[4]); + wreg(cpu_state->hvf->fd, HV_X86_DR5, env->dr[5]); + wreg(cpu_state->hvf->fd, HV_X86_DR6, env->dr[6]); + wreg(cpu_state->hvf->fd, HV_X86_DR7, env->dr[7]); =20 return 0; } @@ -291,40 +291,40 @@ int hvf_get_registers(CPUState *cpu_state) X86CPU *x86cpu =3D X86_CPU(cpu_state); CPUX86State *env =3D &x86cpu->env; =20 - env->regs[R_EAX] =3D rreg(cpu_state->hvf_fd, HV_X86_RAX); - env->regs[R_EBX] =3D rreg(cpu_state->hvf_fd, HV_X86_RBX); - env->regs[R_ECX] =3D rreg(cpu_state->hvf_fd, HV_X86_RCX); - env->regs[R_EDX] =3D rreg(cpu_state->hvf_fd, HV_X86_RDX); - env->regs[R_EBP] =3D rreg(cpu_state->hvf_fd, HV_X86_RBP); - env->regs[R_ESP] =3D rreg(cpu_state->hvf_fd, HV_X86_RSP); - env->regs[R_ESI] =3D rreg(cpu_state->hvf_fd, HV_X86_RSI); - env->regs[R_EDI] =3D rreg(cpu_state->hvf_fd, HV_X86_RDI); - env->regs[8] =3D rreg(cpu_state->hvf_fd, HV_X86_R8); - env->regs[9] =3D rreg(cpu_state->hvf_fd, HV_X86_R9); - env->regs[10] =3D rreg(cpu_state->hvf_fd, HV_X86_R10); - env->regs[11] =3D rreg(cpu_state->hvf_fd, HV_X86_R11); - env->regs[12] =3D rreg(cpu_state->hvf_fd, HV_X86_R12); - env->regs[13] =3D rreg(cpu_state->hvf_fd, HV_X86_R13); - env->regs[14] =3D rreg(cpu_state->hvf_fd, HV_X86_R14); - env->regs[15] =3D rreg(cpu_state->hvf_fd, HV_X86_R15); + env->regs[R_EAX] =3D rreg(cpu_state->hvf->fd, HV_X86_RAX); + env->regs[R_EBX] =3D rreg(cpu_state->hvf->fd, HV_X86_RBX); + env->regs[R_ECX] =3D rreg(cpu_state->hvf->fd, HV_X86_RCX); + env->regs[R_EDX] =3D rreg(cpu_state->hvf->fd, HV_X86_RDX); + env->regs[R_EBP] =3D rreg(cpu_state->hvf->fd, HV_X86_RBP); + env->regs[R_ESP] =3D rreg(cpu_state->hvf->fd, HV_X86_RSP); + env->regs[R_ESI] =3D rreg(cpu_state->hvf->fd, HV_X86_RSI); + env->regs[R_EDI] =3D rreg(cpu_state->hvf->fd, HV_X86_RDI); + env->regs[8] =3D rreg(cpu_state->hvf->fd, HV_X86_R8); + env->regs[9] =3D rreg(cpu_state->hvf->fd, HV_X86_R9); + env->regs[10] =3D rreg(cpu_state->hvf->fd, HV_X86_R10); + env->regs[11] =3D rreg(cpu_state->hvf->fd, HV_X86_R11); + env->regs[12] =3D rreg(cpu_state->hvf->fd, HV_X86_R12); + env->regs[13] =3D rreg(cpu_state->hvf->fd, HV_X86_R13); + env->regs[14] =3D rreg(cpu_state->hvf->fd, HV_X86_R14); + env->regs[15] =3D rreg(cpu_state->hvf->fd, HV_X86_R15); =20 - env->eflags =3D rreg(cpu_state->hvf_fd, HV_X86_RFLAGS); - env->eip =3D rreg(cpu_state->hvf_fd, HV_X86_RIP); + env->eflags =3D rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); + env->eip =3D rreg(cpu_state->hvf->fd, HV_X86_RIP); =20 hvf_get_xsave(cpu_state); - env->xcr0 =3D rreg(cpu_state->hvf_fd, HV_X86_XCR0); + env->xcr0 =3D rreg(cpu_state->hvf->fd, HV_X86_XCR0); =20 hvf_get_segments(cpu_state); hvf_get_msrs(cpu_state); =20 - env->dr[0] =3D rreg(cpu_state->hvf_fd, HV_X86_DR0); - env->dr[1] =3D rreg(cpu_state->hvf_fd, HV_X86_DR1); - env->dr[2] =3D rreg(cpu_state->hvf_fd, HV_X86_DR2); - env->dr[3] =3D rreg(cpu_state->hvf_fd, HV_X86_DR3); - env->dr[4] =3D rreg(cpu_state->hvf_fd, HV_X86_DR4); - env->dr[5] =3D rreg(cpu_state->hvf_fd, HV_X86_DR5); - env->dr[6] =3D rreg(cpu_state->hvf_fd, HV_X86_DR6); - env->dr[7] =3D rreg(cpu_state->hvf_fd, HV_X86_DR7); + env->dr[0] =3D rreg(cpu_state->hvf->fd, HV_X86_DR0); + env->dr[1] =3D rreg(cpu_state->hvf->fd, HV_X86_DR1); + env->dr[2] =3D rreg(cpu_state->hvf->fd, HV_X86_DR2); + env->dr[3] =3D rreg(cpu_state->hvf->fd, HV_X86_DR3); + env->dr[4] =3D rreg(cpu_state->hvf->fd, HV_X86_DR4); + env->dr[5] =3D rreg(cpu_state->hvf->fd, HV_X86_DR5); + env->dr[6] =3D rreg(cpu_state->hvf->fd, HV_X86_DR6); + env->dr[7] =3D rreg(cpu_state->hvf->fd, HV_X86_DR7); =20 x86_update_hflags(env); return 0; @@ -333,16 +333,16 @@ int hvf_get_registers(CPUState *cpu_state) static void vmx_set_int_window_exiting(CPUState *cpu) { uint64_t val; - val =3D rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | + val =3D rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); } =20 void vmx_clear_int_window_exiting(CPUState *cpu) { uint64_t val; - val =3D rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & + val =3D rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); } =20 @@ -378,7 +378,7 @@ bool hvf_inject_interrupts(CPUState *cpu_state) uint64_t info =3D 0; if (have_event) { info =3D vector | intr_type | VMCS_INTR_VALID; - uint64_t reason =3D rvmcs(cpu_state->hvf_fd, VMCS_EXIT_REASON); + uint64_t reason =3D rvmcs(cpu_state->hvf->fd, VMCS_EXIT_REASON); if (env->nmi_injected && reason !=3D EXIT_REASON_TASK_SWITCH) { vmx_clear_nmi_blocking(cpu_state); } @@ -387,17 +387,17 @@ bool hvf_inject_interrupts(CPUState *cpu_state) info &=3D ~(1 << 12); /* clear undefined bit */ if (intr_type =3D=3D VMCS_INTR_T_SWINTR || intr_type =3D=3D VMCS_INTR_T_SWEXCEPTION) { - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, env->ins_= len); + wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INST_LENGTH, env->ins= _len); } =20 if (env->has_error_code) { - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR, + wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_EXCEPTION_ERROR, env->error_code); /* Indicate that VMCS_ENTRY_EXCEPTION_ERROR is valid */ info |=3D VMCS_INTR_DEL_ERRCODE; } /*printf("reinject %lx err %d\n", info, err);*/ - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info); + wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info); }; } =20 @@ -405,7 +405,7 @@ bool hvf_inject_interrupts(CPUState *cpu_state) if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) { cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_NMI; info =3D VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI; - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info); + wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info); } else { vmx_set_nmi_window_exiting(cpu_state); } @@ -417,7 +417,7 @@ bool hvf_inject_interrupts(CPUState *cpu_state) int line =3D cpu_get_pic_interrupt(&x86cpu->env); cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_HARD; if (line >=3D 0) { - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, line | + wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, line | VMCS_INTR_VALID | VMCS_INTR_T_HWINTR); } } @@ -433,7 +433,7 @@ int hvf_process_events(CPUState *cpu_state) X86CPU *cpu =3D X86_CPU(cpu_state); CPUX86State *env =3D &cpu->env; =20 - env->eflags =3D rreg(cpu_state->hvf_fd, HV_X86_RFLAGS); + env->eflags =3D rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); =20 if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) { cpu_synchronize_state(cpu_state); --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622738289; cv=none; d=zohomail.com; s=zohoarc; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qtE21tz0j/XuMTe0sitQ70UbPqN5imUOWXQe5LhVK1Q=; b=ZHGerY4o50xyISuWhrJ3KszUJudtYUf2KA3+ncS9sh0C/RMEMqTtgZ/ZsqEIwutNPx 3VrJB+SJlkSeNqwt9ih7jw5htumcCWOxeSDstsq1hvIC4hpxKNRbIQwpXC/0TuEdQFBB wTkOut0QDOWt+9nOyhIO0PExz+K2qJg/ZXA2JU+341seDoiqF4+FlZqwiHk3ydb7IcA6 ouTN/Z6jtktS8oNJS/kQNnsOCP6Y04ggavgcJyIejAJz202T6Q0yKCO32dZAOhu1YfKY d04gMIiM2TRrmiHm+/CT6+XEPMzJC2K4WNgLbUo1tpfimKlZ/EqA0Jj1iGgFMSG7azWa NSdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qtE21tz0j/XuMTe0sitQ70UbPqN5imUOWXQe5LhVK1Q=; b=Fv35mYTt2gukuQquflS6zJn3ElFLIYfjB8X9SOG+PhF0IBCSgB3ia9D2NPPnirvnRf htP3o7lq4asAVaY7xLQYrGyqFqKRPv1voFJZd3Nbvu38USU20dUTTK8BQFv+TZtqlX73 cYrFlstxwU6RdXA0e0Z6s1xUiBDexZU9dpMyJo3G4HZNdSo38jQw0Eo5kCvlckZO+h4Z sTADXyYsCgU1MH00K6aoM5wcYnvwLpnUBSnkBHgrEkyAqHGLTBvogT0ZEk199coj+NyI PMhLZzixGEgxP6u+2lQPgHFJcjS7nmAUXmX/6x3SYRBMngqpmOcnKXnixNqwqzvygTE1 tq0Q== X-Gm-Message-State: AOAM532dGYSXKnIf3UQ/8ptBeN/9e0YJfjr4pn3fBqIrGghzaeG5QfNp oD1NsUCDUfebf4ByqAwazHjpG7pW5PUeLu3R X-Google-Smtp-Source: ABdhPJztqYPIn2V3gU20o4i7QvXWF8Fwka3PmSqTRDtoY/Y8ZmlJ4R/XtV4c7DROQ9gp4iHLDU6crg== X-Received: by 2002:a5d:4dc2:: with SMTP id f2mr682293wru.124.1622735985352; Thu, 03 Jun 2021 08:59:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/45] hvf: Simplify post reset/init/loadvm hooks Date: Thu, 3 Jun 2021 16:58:58 +0100 Message-Id: <20210603155904.26021-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alexander Graf The hooks we have that call us after reset, init and loadvm really all just want to say "The reference of all register state is in the QEMU vcpu struct, please push it". We already have a working pushing mechanism though called cpu->vcpu_dirty, so we can just reuse that for all of the above, syncing state properly the next time we actually execute a vCPU. This fixes PSCI resets on ARM, as they modify CPU state even after the post init call has completed, but before we execute the vCPU again. To also make the scheme work for x86, we have to make sure we don't move stale eflags into our env when the vcpu state is dirty. Signed-off-by: Alexander Graf Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov Reviewed-by: Sergio Lopez Message-id: 20210519202253.76782-13-agraf@csgraf.de Signed-off-by: Peter Maydell --- accel/hvf/hvf-accel-ops.c | 27 +++++++-------------------- target/i386/hvf/x86hvf.c | 5 ++++- 2 files changed, 11 insertions(+), 21 deletions(-) diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index ded918c443d..d1691be9896 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -205,39 +205,26 @@ static void hvf_cpu_synchronize_state(CPUState *cpu) } } =20 -static void do_hvf_cpu_synchronize_post_reset(CPUState *cpu, - run_on_cpu_data arg) +static void do_hvf_cpu_synchronize_set_dirty(CPUState *cpu, + run_on_cpu_data arg) { - hvf_put_registers(cpu); - cpu->vcpu_dirty =3D false; + /* QEMU state is the reference, push it to HVF now and on next entry */ + cpu->vcpu_dirty =3D true; } =20 static void hvf_cpu_synchronize_post_reset(CPUState *cpu) { - run_on_cpu(cpu, do_hvf_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); -} - -static void do_hvf_cpu_synchronize_post_init(CPUState *cpu, - run_on_cpu_data arg) -{ - hvf_put_registers(cpu); - cpu->vcpu_dirty =3D false; + run_on_cpu(cpu, do_hvf_cpu_synchronize_set_dirty, RUN_ON_CPU_NULL); } =20 static void hvf_cpu_synchronize_post_init(CPUState *cpu) { - run_on_cpu(cpu, do_hvf_cpu_synchronize_post_init, RUN_ON_CPU_NULL); -} - -static void do_hvf_cpu_synchronize_pre_loadvm(CPUState *cpu, - run_on_cpu_data arg) -{ - cpu->vcpu_dirty =3D true; + run_on_cpu(cpu, do_hvf_cpu_synchronize_set_dirty, RUN_ON_CPU_NULL); } =20 static void hvf_cpu_synchronize_pre_loadvm(CPUState *cpu) { - run_on_cpu(cpu, do_hvf_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); + run_on_cpu(cpu, do_hvf_cpu_synchronize_set_dirty, RUN_ON_CPU_NULL); } =20 static void hvf_set_dirty_tracking(MemoryRegionSection *section, bool on) diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index 28cfee4f608..2ced2c24784 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -433,7 +433,10 @@ int hvf_process_events(CPUState *cpu_state) X86CPU *cpu =3D X86_CPU(cpu_state); CPUX86State *env =3D &cpu->env; =20 - env->eflags =3D rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); + if (!cpu_state->vcpu_dirty) { + /* light weight sync for CPU_INTERRUPT_HARD and IF_MASK */ + env->eflags =3D rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); + } =20 if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) { cpu_synchronize_state(cpu_state); --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737667; cv=none; d=zohomail.com; s=zohoarc; b=GPsFzXVP0tEQeela4aoEE3mPoiQAYcq+FVr7xgS4XADwBCRqupH7a944D9oon1ssTGWgNjBm6byPH2bHeF5JVYkw88WM9W9pSA1u1fik9kyQVUgL3Uef321zlm3aPk4AIZc2TOaU/JOnEQMVSmrCCs7OTrxdva1SudDSWJ6vqyg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737667; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=umKlYqbHmDGAhLtrJPTkOzCMHctMqp53oORvJhnAQvE=; b=k6i5WQNh+dfzLQbL5UdREBiMAZheBVUO3D+QgGlpRg/Cv48uJfPGiJKrZ2xcFU3jOOHrNWdbmp1+Th1UNHh45jLUX4bP9bnfXEDqG4peNqteVPw5oLRTND/8WErt8wakPS+aeIeXLSqOU5EG8U3zQqRIF8lKpaiTEBG2pdvNFSA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737667031695.7176946407742; Thu, 3 Jun 2021 09:27:47 -0700 (PDT) Received: from localhost ([::1]:57266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loqC9-0007PF-Vx for importer2@patchew.org; Thu, 03 Jun 2021 12:27:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36034) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopl6-0001tw-VD for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:48 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:37675) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopl5-0007JG-8n for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:48 -0400 Received: by mail-wr1-x432.google.com with SMTP id i94so1347433wri.4 for ; Thu, 03 Jun 2021 08:59:46 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=umKlYqbHmDGAhLtrJPTkOzCMHctMqp53oORvJhnAQvE=; b=b+RnnyTY02ccACDmzEG/ArDgV8bq5ySPA4SWnzClpJOcltvl6Paxt2nQ9IT8Ie41SY 5+NWJmHwqTx16eEmHcLtUs2YIPe3meswxn4rmIHoPY+vVG3wYrVbokSLfEk6X3Fr70CF 3oWKxCcN6eVWHMf3jSvt4sNMoC9ef1Pq4fFZ54kZjCF2Xj5I2OrBujTkJG6LWrKpZjV3 Bu6IIawr5nQjq/EoXaL8oCQfKtQtacPJzF1s72DxVg+VKLiYFqfQuRb5CjZxaX+Ya4Wn wYG3ZnmISu4QptrV0ZDwt8TYQDl5nNft+AEB3cBFiJYRsNkzFXvQ+5TE1wRVsU1dCvqg JIjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=umKlYqbHmDGAhLtrJPTkOzCMHctMqp53oORvJhnAQvE=; b=Sixu+jQRRopHW4wukmMU89b1ssjpfpiU02lQaLpgdexkEGQpeZLH9g6ai03/RfivdD 0GhQjio1mVZtJl2qChzNrdL3idoKVMKugZjplI9yOS1yJzaoJxWa1TmvMAT70SKrot7s rG0oet938aJ2atK4J7pEiUgNX7NoiYlUEwfbitetttDsNlCqtiNEQMhB1VTszS+Zt4tU 1WCOH2wR8ZrMh2HlRnEKP8U2snCM2BAhDXShfm0ELmS4v4L6pzgKOyCzYBY8zUv1xo5E Gwr2wjeVcg9hYi8jncd8/uhMd4vpJIT2TYKHfhnxnNPsXq4xSCoiQFc/H/zqryuTGEm0 nHiw== X-Gm-Message-State: AOAM531JyBhYDc2dyLPljkVvcaXO1IOR2Gecq4sjle75Eq678EEZnzb+ DA+1BJ6c7br4/Xt1JTJshjaMTVwfmrnBJ/DJ X-Google-Smtp-Source: ABdhPJyEqxyyrVpgee4JqvtfdzF/GnYthKftmB7ShRWoHZs+grwcN7BxJcrWSz71164S9YZl4hXqKQ== X-Received: by 2002:a5d:6d85:: with SMTP id l5mr660817wrs.22.1622735985936; Thu, 03 Jun 2021 08:59:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/45] tests/qtest/bios-tables-test: Check for dup2() failure Date: Thu, 3 Jun 2021 16:58:59 +0100 Message-Id: <20210603155904.26021-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Coverity notes that we don't check for dup2() failing. Add some assertions so that if it does ever happen we get some indication. (This is similar to how we handle other "don't expect this syscall to fail" checks in this test code.) Fixes: Coverity CID 1432346 Signed-off-by: Peter Maydell Reviewed-by: Stefan Berger Message-id: 20210525134458.6675-2-peter.maydell@linaro.org --- tests/qtest/bios-tables-test.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 156d4174aa3..51d3a4e2390 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -489,10 +489,14 @@ static void test_acpi_asl(test_data *data) exp_sdt->asl_file, sdt->a= sl_file); int out =3D dup(STDOUT_FILENO); int ret G_GNUC_UNUSED; + int dupret; =20 - dup2(STDERR_FILENO, STDOUT_FILENO); + g_assert(out >=3D 0); + dupret =3D dup2(STDERR_FILENO, STDOUT_FILENO); + g_assert(dupret >=3D 0); ret =3D system(diff) ; - dup2(out, STDOUT_FILENO); + dupret =3D dup2(out, STDOUT_FILENO); + g_assert(dupret >=3D 0); close(out); g_free(diff); } --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737243; cv=none; d=zohomail.com; s=zohoarc; b=UzLw1/xwvcuDrm3GRI3ToDiSgfS/JYzhAnKnlsw7zQQ9GtTx7LP0C7pTviessC6QH27isopSJl+OzEBgcmk1roqv2VVSCuVpru69PJ+k4Qwg6vPDPYbdS3GR7ojtE+wPJrLqxRn8b855kvIV1gaD35gwmvsoWbhzGYVh4XlJBYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737243; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ppBM5sB9swc2F+kqmAJujcvoKiiJMssttgA/rEBYgGw=; b=ZBJPmNmrW1F/6+dBaUiQLazKPsrIywgA6bwd+y0cMnxSQYWDme7EQ5iE34mNf4IHrfsnnpYTlNEOPt6t+MVJhOjXsSoOp00tlWMvUzUH/okv1lBfOCH5Ilvn7mXG71oJOAOGCulDOPYNnGkeMW4QLwqBt4/SMr00L9A0QNn6tWc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737243958124.76455500469046; Thu, 3 Jun 2021 09:20:43 -0700 (PDT) Received: from localhost ([::1]:56334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loq5K-0003lT-Rm for importer2@patchew.org; Thu, 03 Jun 2021 12:20:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36070) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopl8-0001z9-5T for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:50 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:34478) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopl6-0007K5-AI for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:49 -0400 Received: by mail-wr1-x429.google.com with SMTP id q5so6407880wrm.1 for ; Thu, 03 Jun 2021 08:59:47 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ppBM5sB9swc2F+kqmAJujcvoKiiJMssttgA/rEBYgGw=; b=CwNIqLZXIQC31giBISFJAPVPjZYJgWg00bwsxWqB5pMhs9qj/0AOD4pDigXdFliqeN lofXGTqGMreH8z11gaN0QL2ubvJZdvKPsw2gRqSun8RgbZl7AzIAz5FKoeJkfdaukUQ2 aCIYOGvPRdUhvKAhZh4WsCai/N5egwAnDsWa0Q9ccCHV+HfvIkKH1ICfIR6cbzZXBVtV Os0ovdad/Xt0tKYQSdkYVa9toDT7xRB4wy/PRn9TCZD6Sr3Jdr9vDUdICPibREjiWkM0 3UfRQXtBqjR9Mpth7tS1IH3phhTHlKGCj5sP2UWTnaEgRQIcG/dTQ0SHIMjT1IvjvsJF eBBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ppBM5sB9swc2F+kqmAJujcvoKiiJMssttgA/rEBYgGw=; b=QdiruyQYh4+beAyQt6k4v2Xfn1vdBaaBc6+DVV5OJdHZ68o7Lxw0lgG6K8soWBDDxH Qq1LR5wPCtkDmUR4vHyvPEF9AJuKIKEzCcNGXq8jpgIacgnHfE2W0VUWK8vwXRzzDbm0 CxjQbLUVImmkXCBB90MhpcdjCMUwEA51XMewe8RkFnCjk+xukshntcdXyJHoBtwbYTMg 5H7OFRmNYVKN6vxij8kBCRHK/A0I8y7rUjZW1EYfyxlKwduEGOE6lP44KeQsomx4iBFm VcyHOkUMp46qaU+EzCb8vacLGK8PKsY+QeoQXJFEfbcSAAFi531Wv00LTICIXungQZCD Ngxw== X-Gm-Message-State: AOAM530nTRZtvtYzoBgSUpIeq2U4F9LLiPGHD9VUxeeMrutKdbMnIcm4 x4hKegwYkuJKxdCpTS9tojdi7uwKziRkYvmK X-Google-Smtp-Source: ABdhPJyg1V+g/rkvxFFlNSww61TGh8ArJRyiSL87s479QaBBd6k878ETSWu8RfbJk4igc41/+Lqllw== X-Received: by 2002:adf:f90c:: with SMTP id b12mr647307wrr.409.1622735987065; Thu, 03 Jun 2021 08:59:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/45] tests/qtest/e1000e-test: Check qemu_recv() succeeded Date: Thu, 3 Jun 2021 16:59:00 +0100 Message-Id: <20210603155904.26021-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The e1000e_send_verify() test calls qemu_recv() but doesn't check that the call succeeded, which annoys Coverity. Add an explicit test check for the length of the data. (This is a test check, not a "we assume this syscall always succeeds", so we use g_assert_cmpint() rather than g_assert().) Fixes: Coverity CID 1432324 Signed-off-by: Peter Maydell Reviewed-by: Stefan Berger Message-id: 20210525134458.6675-3-peter.maydell@linaro.org --- tests/qtest/e1000e-test.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/e1000e-test.c index fc226fdfeb5..0273fe4c156 100644 --- a/tests/qtest/e1000e-test.c +++ b/tests/qtest/e1000e-test.c @@ -93,7 +93,8 @@ static void e1000e_send_verify(QE1000E *d, int *test_sock= ets, QGuestAllocator *a /* Check data sent to the backend */ ret =3D qemu_recv(test_sockets[0], &recv_len, sizeof(recv_len), 0); g_assert_cmpint(ret, =3D=3D , sizeof(recv_len)); - qemu_recv(test_sockets[0], buffer, 64, 0); + ret =3D qemu_recv(test_sockets[0], buffer, 64, 0); + g_assert_cmpint(ret, >=3D, 5); g_assert_cmpstr(buffer, =3D=3D , "TEST"); =20 /* Free test data buffer */ --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737379; cv=none; d=zohomail.com; s=zohoarc; b=LSVjzusPwQSaDmMI+aQvmdKUXJTpvhcHBMnrsMxevGOlZQ7/xhnr9mHITph1Z8g19ErsgNAl+/kXtPb8ebPiwITGxzgWlnHBpKWyCOB5jpHTqEp2nmDwRpwMMTy+HYvs0/HgKuaqVtlY87AQham6iY/0KBPhALypAfZtLIz3AXg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737379; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Cds5GGFqPsxZEQ8A/Oi3ANjhdDr2P17DFeabFdjzF8U=; b=PdV2ebTxg4ezAPVkWqvVlgtFCGTdn27Oep+afEwO7buYnaeTzTMlxs00igRXg+Zg1mIloJT98ZXKE49QVfBYw7ZoskzTQa/kXTZj8AFJqHoPNJIVvm/JEQ0rD2f15wr6C9EkM1AzkVS9dZP3vUPihaI0qNt+NaF9vNlOzhuvY4M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737379279160.06302688179994; Thu, 3 Jun 2021 09:22:59 -0700 (PDT) Received: from localhost ([::1]:36720 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loq7W-0001cW-8M for importer2@patchew.org; Thu, 03 Jun 2021 12:22:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36102) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopl9-00024X-JB for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:51 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:39703) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopl6-0007KS-VL for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:51 -0400 Received: by mail-wr1-x42d.google.com with SMTP id l2so6392064wrw.6 for ; Thu, 03 Jun 2021 08:59:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Cds5GGFqPsxZEQ8A/Oi3ANjhdDr2P17DFeabFdjzF8U=; b=uiIkQukl2KEQBueWUw4rXpRwFeNgRLPaa1AcADpNGq0WHim2TPVfWsq8On4RpuEJsc Pui+qyTZapmEmfwSqezn8qxtWzQsmWw6c8TQuLo6wxvxfWjWhHXMjxvbpGzNnO0kcw25 Bm/YLh7eQQU+J9XHZg1VqusSYaVrghbEl1AEF60hw6zjX8nUNsNNL6gcVUyjVX/rDsbE 7+HsCYwaGhdM7O+4er3aQ/oZ11TeJU7vUh0LBMhF4rD3zHDckPOg/H4pPPNzzGSkkk6L H2wYO21sQOEg8GT0ZIAXBWInb5VyWN+nWZghmx6ZItK/ycJRW8ctLTg0hTBIkmgt2v5Q FxOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cds5GGFqPsxZEQ8A/Oi3ANjhdDr2P17DFeabFdjzF8U=; b=LkvAjU0b5KIxAsrmEK9FcXREPM8Q6o5/BH/5o/CRJ7TLG3+puDQFPz/F1YdALM8Tyz XruX+XSSp7y4FK38wzJ0wrchDhL0mBEScV8YuqNO2DHQ1lWME1RlFJkwoZpsXJJQAXgP KnuqVSyiQSy9SpnYJU6QXKcmwyRJ1p7v40CmTNvaLM4hCMJQgkjsSrE3jjv6AWtsM2s2 v+dfo/fcEN7Dtgj6isKpbOt3Hv4JQTJDwpFlISQcpWZxFlqkYCeh+5VYGHGbcXsnrNqx ws3ASZd+zhPFIPgng9UTQ9rnMEHtZI+u9hl7m3RlN+wCJ5768IYKK5ETJ9sElgNzRQff WNpg== X-Gm-Message-State: AOAM530YRwgfQE9CqTQu6g5c70tDXaU3zFvGiEQFWJnDUNk9/1hSaAGf faN9mSLXgAH+8ApKiEqPWcECXLTCHr2x+bBN X-Google-Smtp-Source: ABdhPJzawrOlK5DqRuxYPHQUfBufIGIk0aqbdTM8/8BPR2fWoeVocJjtfXJSJPhB+x0vjQ+3XlXN5w== X-Received: by 2002:adf:f54a:: with SMTP id j10mr612427wrp.383.1622735987690; Thu, 03 Jun 2021 08:59:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/45] tests/qtest/hd-geo-test: Fix checks on mkstemp() return value Date: Thu, 3 Jun 2021 16:59:01 +0100 Message-Id: <20210603155904.26021-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Coverity notices that the checks against mkstemp() failing in create_qcow2_with_mbr() are wrong: mkstemp returns -1 on failure but the check is just "g_assert(fd)". Fix to use "g_assert(fd >=3D 0)", matching the correct check in create_test_img(). Fixes: Coverity CID 1432274 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Stefan Berger Message-id: 20210525134458.6675-4-peter.maydell@linaro.org --- tests/qtest/hd-geo-test.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/qtest/hd-geo-test.c b/tests/qtest/hd-geo-test.c index f7b7cfbc2d1..113126ae06c 100644 --- a/tests/qtest/hd-geo-test.c +++ b/tests/qtest/hd-geo-test.c @@ -464,7 +464,7 @@ static char *create_qcow2_with_mbr(MBRpartitions mbr, u= int64_t sectors) } =20 fd =3D mkstemp(raw_path); - g_assert(fd); + g_assert(fd >=3D 0); close(fd); =20 fd =3D open(raw_path, O_WRONLY); @@ -474,7 +474,7 @@ static char *create_qcow2_with_mbr(MBRpartitions mbr, u= int64_t sectors) close(fd); =20 fd =3D mkstemp(qcow2_path); - g_assert(fd); + g_assert(fd >=3D 0); close(fd); =20 qemu_img_path =3D getenv("QTEST_QEMU_IMG"); --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737752; cv=none; d=zohomail.com; s=zohoarc; b=IvT0+6vjNMTAx1U58a4K3EIZMGOJFlu22csq9OYHJi8kfRLKFgqkqOqD0GHRyrw1X8fPi8foQNP7DrnFPVEG6q71FUPeIm9MpaqnrZRTX9Tqu1KZiWaIsCJuCT2zHjyYKsHe3K9XqeTkEhwGFTFZJRD6artD580zCdSQ87x6b4U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737752; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=30mcllybotT9ZUvdTQo+V2rYRwrN4iGSwp36CDv+3mQ=; b=fYKmtB0Hi9H9GGGbi42mS4HEEMAz+kB9vyW2DE3hoUuWoaP9rW0wZUz0FNCbYP6WYTHcC+pdvpEcxuQnB4Fo1Powo/Hvs8xX8H8xzOLD0CHdsi+3/JWlj1V+ELLhJXoVcf53vf/60WdFeZmkW8fVETdFYpvFNQ1m1LMARs5G/XE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737752050667.1353900310475; Thu, 3 Jun 2021 09:29:12 -0700 (PDT) Received: from localhost ([::1]:35412 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loqDX-0003Mu-08 for importer2@patchew.org; Thu, 03 Jun 2021 12:29:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36112) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loplA-00028C-En for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:52 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:53841) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopl7-0007Ke-KU for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:52 -0400 Received: by mail-wm1-x32e.google.com with SMTP id h3so3717350wmq.3 for ; Thu, 03 Jun 2021 08:59:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=30mcllybotT9ZUvdTQo+V2rYRwrN4iGSwp36CDv+3mQ=; b=CCfcSFZTAHO8albR41Cod11K51K6gLTJdUWQImjQXZJjDu8wJ+6BWeqECsOvyM/ZyV yKbXKAYhwTSDVg7PWSy+g6gcv6A9wKri+t7jcqL7QGDDc0dLm1ycFZqJCzr/2EEKggoD D5FgIK2g9Db1dMIw1WRQURQLzoAsrZQZ6OragXHEy0ktpkZA4JfFV9xj1x5RDfvYRLZb 1nkNWyMg0eUpC/CWAK2t4/KXDC7AyCaaz8UKyolq0LAjMMPVs9LJg3LrgnoQMB4Knljr bsrfxd8mOZ6n/w1cpOS3mHfBwefDYQy7wxAuw1Io5thZ9+uOZx850IS0rCEsjcUXs8oQ Fh9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=30mcllybotT9ZUvdTQo+V2rYRwrN4iGSwp36CDv+3mQ=; b=anY2TdzYJgDzDAB//J56GV9Au4YrV3X3Wn1d2Aug9NActCpfTL15BoAejCt3cZMXlp /VhZEpuJYLRxcAyK/GiiFDWMlIeIUWbnoUKcIFzQALM6b6thV8fdTsox+fxx1msEG3sw Xn6XjaJceOHLXKjKd3VTpolDgcX0SnCMw0tZUuad+Zyv+043iz+B3Kv6FlOhPFEYqQ7m 82Hpx0f7IDxWEVP0oB7CmxrdsxyN+vveOTVaWE997gOuYYWt7c/r1MwchVKjtm9r2JlT yC7aZrPIKqwydwYjbq9iVY3ZN/v8HctQ8SuhqWo+Mncu5o1/hAp8xlmqSUWVnCH0MvMf 18bA== X-Gm-Message-State: AOAM530Fz6HueKfoMG9KY0LRcw8+JCiL30PVv7UQqw3YFLmK+WJgoA9y /5UNNUVJrd24hdOElSf7rzYAl8d2QRWFv0vG X-Google-Smtp-Source: ABdhPJwLpZtaRdSNoQlMhJvFQs1W27a1wM/B5Yk+o9PWsklO+fNeDvXY0TJ3JYyQD1xmfTM/6WjLAA== X-Received: by 2002:a7b:cd9a:: with SMTP id y26mr11030967wmj.133.1622735988300; Thu, 03 Jun 2021 08:59:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/45] tests/qtest/pflash-cfi02-test: Avoid potential integer overflow Date: Thu, 3 Jun 2021 16:59:02 +0100 Message-Id: <20210603155904.26021-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Coverity points out that we calculate a 64-bit value using 32-bit arithmetic; add the cast to force the multiply to be done as 64-bits. (The overflow will never happen with the current test data.) Fixes: Coverity CID 1432320 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Stefan Berger Message-id: 20210525134458.6675-5-peter.maydell@linaro.org --- tests/qtest/pflash-cfi02-test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/pflash-cfi02-test.c b/tests/qtest/pflash-cfi02-tes= t.c index 60db81a3a2b..6168edc821a 100644 --- a/tests/qtest/pflash-cfi02-test.c +++ b/tests/qtest/pflash-cfi02-test.c @@ -406,7 +406,7 @@ static void test_geometry(const void *opaque) =20 for (int region =3D 0; region < nb_erase_regions; ++region) { for (uint32_t i =3D 0; i < c->nb_blocs[region]; ++i) { - uint64_t byte_addr =3D i * c->sector_len[region]; + uint64_t byte_addr =3D (uint64_t)i * c->sector_len[region]; g_assert_cmphex(flash_read(c, byte_addr), =3D=3D, bank_mask(c)= ); } } --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737285; cv=none; d=zohomail.com; s=zohoarc; b=JJZ9Cr3gXFlbQmCa9+OcCreaUGGmtVSM7DAbJkF+DlYmH9mihGrRA06TlCfYL+wU4/6kNUlKNkWJ5icDjiUSHbM+QzIfitT7tbDZrDjjp8lSWJmaiHAoXKdeJtWwGZ2Wm83/jT7aafqulut21WMoysj8+RpFDlmK4U9xd251p2w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737285; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vB763nEKsycGOOwLmyzgDlOyxRqYkf2isox8y68EQSM=; b=nyhcz4BYVIFBHgfBC33pEfsvWqU6Thdx16cQmSWyVwxWBJ1frSb0RW+p8cNMQjZGz2l8x0KCfbVTuYchliY2Iu1fYXS/8o4DP7iv7fLt1pG8omDyJpJoSt4Sa1Q8MeFbCIVdu0+OSDEf6sLGwb93NF9gaK2DpwycNDRW4z5/KVQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737285498199.70029700675332; Thu, 3 Jun 2021 09:21:25 -0700 (PDT) Received: from localhost ([::1]:58150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loq60-0005DH-FH for importer2@patchew.org; Thu, 03 Jun 2021 12:21:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lopl9-00025r-Vd for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:52 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:44927) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopl8-0007L6-5G for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:51 -0400 Received: by mail-wr1-x434.google.com with SMTP id f2so6355912wri.11 for ; Thu, 03 Jun 2021 08:59:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vB763nEKsycGOOwLmyzgDlOyxRqYkf2isox8y68EQSM=; b=aFdQZPAafVJ3tE4CfQnuCqfHiJPS4te81ibLEMCbl2tTO2YhzxK5Yu/HWFXqPGQvn1 YFXN9Tl/w20mtLarPQ1KqAsFac5cdcRh9q17jUNMsPhk6XKq8zhKGocJ7EChRk8sHN0d PaaMWLxInMI6bLvXMAPpE/EZckFtDBgI4Rx1vcne9ixZmLvMH+iN0h7K0E14zAd5opct /S+pdL5wpu7D+1/VIPcbsFM9bbGR9Vy9L4bUFHhGvIMUXYiu+37SByTTCH04l4PlSv+G fKKm5224tpLFRhLAi6Li4rlGLlGKP7IrXBPMfj1zPwMjRggb6H+mHC2E8dAuWgsdZ7rO rPTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vB763nEKsycGOOwLmyzgDlOyxRqYkf2isox8y68EQSM=; b=MtChFSoUJ2H5geDqPlBxa8ceNbmNMkLfgvovxpj/Cyo3enTLxm4dgcoSvp2nY9VE8J 7Y7NUIQLEyDp+mSsXAQHqIYpYQscihOe8m5AqGaJ7I25/w4dUnnT1WbIucCIQ4StHEug mmmWlZ6ntMCnL4vqeyWTqbhzSq9K6P3y+Z492RqgHyuXoRozHE9pzm60QLMJPe1KZpOJ /FlQqK9hS04pfS20xAj8fXjU45ozSe0/75CpkLKwzFLsdGbVK3qIp63baEqbfFWOK6qz ajrMk8TICLvGKyCN3NJaq2O2iBtP5ZuwW6IFmKOMwFOtUbRui9S4LCuuMDNiFPKUnVb/ nw5w== X-Gm-Message-State: AOAM531KnAW308yR/f/0pEUIkzl14chytNPPK9u3sr85zeIrNO8M697Z UmqqG7YfyNOtC2S+Xn34Qq9wTpG7pMnHKeSI X-Google-Smtp-Source: ABdhPJwMruFbzwJPbRETIoZlAbGkOL3oHCVIwH4SsRplAoHOLPYAmZnhYvCmGuz0ClADpHIGHBL1jw== X-Received: by 2002:adf:dcc3:: with SMTP id x3mr617244wrm.177.1622735988907; Thu, 03 Jun 2021 08:59:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/45] tests/qtest/tpm-tests: Remove unnecessary NULL checks Date: Thu, 3 Jun 2021 16:59:03 +0100 Message-Id: <20210603155904.26021-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Coverity points out that in tpm_test_swtpm_migration_test() we assume that src_tpm_addr and dst_tpm_addr are non-NULL (we pass them to tpm_util_migration_start_qemu() which will unconditionally dereference them) but then later explicitly check them for NULL. Remove the pointless checks. Fixes: Coverity CID 1432367, 1432359 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Stefan Berger Message-id: 20210525134458.6675-6-peter.maydell@linaro.org --- tests/qtest/tpm-tests.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/tests/qtest/tpm-tests.c b/tests/qtest/tpm-tests.c index 0da3a8a4df5..25073d1f9e9 100644 --- a/tests/qtest/tpm-tests.c +++ b/tests/qtest/tpm-tests.c @@ -123,14 +123,10 @@ void tpm_test_swtpm_migration_test(const char *src_tp= m_path, qtest_quit(src_qemu); =20 tpm_util_swtpm_kill(dst_tpm_pid); - if (dst_tpm_addr) { - g_unlink(dst_tpm_addr->u.q_unix.path); - qapi_free_SocketAddress(dst_tpm_addr); - } + g_unlink(dst_tpm_addr->u.q_unix.path); + qapi_free_SocketAddress(dst_tpm_addr); =20 tpm_util_swtpm_kill(src_tpm_pid); - if (src_tpm_addr) { - g_unlink(src_tpm_addr->u.q_unix.path); - qapi_free_SocketAddress(src_tpm_addr); - } + g_unlink(src_tpm_addr->u.q_unix.path); + qapi_free_SocketAddress(src_tpm_addr); } --=20 2.20.1 From nobody Thu May 2 09:20:03 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622737559; cv=none; d=zohomail.com; s=zohoarc; b=oCFEF4BB/QcIYX0S0a3yX5OG4hPjocnsrQnlIKj1h6GnDiYItRmasbwuIrmAIMra82zi4Xp2/Y7W+X6cLkqM8bziNFjc7vmmLz69vp2rQAtAIPQE915bdeuvc92j44cUYFgB7DiFCDdnRyDhSzRfg8buJGD1Za3w7bR77jH9PM4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622737559; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=m1JvP1lXOK3zZvLip3asXuEZCo/dk9yce1L53z04jlM=; b=YTiXAVv/gy76zwBMI5xCEkLWPXAzS6ysuNP7VneyF+v6J40p4uR+rApG1UCQOEAR2xIgG2KxPQ30DcdyNRO+Cn8k2VSkPqCp4kqmSYYSC+3zpcrORQls/J7X06piGMYCLztlHkfspRgETpo6DUXof9JIvLFLF6lp6sujT/VXiqE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622737559899927.8266633895563; Thu, 3 Jun 2021 09:25:59 -0700 (PDT) Received: from localhost ([::1]:48502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loqAQ-0001J9-SL for importer2@patchew.org; Thu, 03 Jun 2021 12:25:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36122) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loplC-0002Eo-1C for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:54 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:36691) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lopl8-0007M2-QE for qemu-devel@nongnu.org; Thu, 03 Jun 2021 11:59:53 -0400 Received: by mail-wm1-x332.google.com with SMTP id n17-20020a7bc5d10000b0290169edfadac9so6224863wmk.1 for ; Thu, 03 Jun 2021 08:59:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m7sm3856470wrv.35.2021.06.03.08.59.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:59:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=m1JvP1lXOK3zZvLip3asXuEZCo/dk9yce1L53z04jlM=; b=go2SwTodvQ5Oo6JbHtc0qYeIhtGrgVPDwsJlQyQew/mOFwzt3tm2DeRNpY20V7CTXC +5aul4Xq+x2Z9N/2mVralhIJCJC3w6SnBHl7aNSPN/rOsYwzp6qwdll4wJkMccnav9Hx M+6kL4BCsH6CkLfuyu8aAfa8Sg3/4KPciSosP0pOU7JZ/bNXVt8BL4/JEeKKIeRrqDZ2 Yv2+n0AbCo1Xmcl5HlvXSuHeS/s54F4SWz7EQVQ6kZmWj0e+6T6c5t66EisuqEKJOY5e R0qrDMIw3qb1bXFoFYlxbc6haQmmt6bkgVZRmbftPqAuz2G9gA028edBuS4fup60+BtM 8KvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m1JvP1lXOK3zZvLip3asXuEZCo/dk9yce1L53z04jlM=; b=n/NJxZr2uFEurMRu1Ll7VnAX+iISPmsID53APPcADV4hIo2d7V73W1/GHBGZM7VMXQ LdqnJ4v0Z594QlDUI/BnEhYYmmHjCGig+qxgeFz7HlD0eesn1zj442AV3CjLhT0La19a I0dP+GB4Y4tgqlQKvqCZtzZA9VGB/ojorvmmSp795axsDJSKxs0/5qJHQFk64lZB1LpM ZcIJwZDolL6RRtBU6tpMmWjjMvr0bYhZf6AbuMjdWUHcMXYBte/ncpP2m2pMLm3NjJY8 5J6gH08UI9oFnA/7BV2Th64RpBJCuNxODd1ZiBnBvxJny+jjw/0QsMON9WexVC1TVefk qOjQ== X-Gm-Message-State: AOAM531jd8W3M1EB9kwQrR3wC7+89uuSAgjpAMMh20eUo9odsItiJYTl Q7eCPxhYftLIePP21OhYsHOcwT09GWV1IbB9 X-Google-Smtp-Source: ABdhPJw5f0UxO8qJGSoq5UlzIGnQT7KBZ3QvIuNl7Dz6Sc1RHQKIDEXKpSTsuopul+O3b1IEsZHWiA== X-Received: by 2002:a7b:c095:: with SMTP id r21mr10546895wmh.86.1622735989550; Thu, 03 Jun 2021 08:59:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/45] tests/unit/test-vmstate: Assert that dup() and mkstemp() succeed Date: Thu, 3 Jun 2021 16:59:04 +0100 Message-Id: <20210603155904.26021-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210603155904.26021-1-peter.maydell@linaro.org> References: <20210603155904.26021-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Coverity complains that we don't check for failures from dup() and mkstemp(); add asserts that these syscalls succeeded. Fixes: Coverity CID 1432516, 1432574 Signed-off-by: Peter Maydell Reviewed-by: Stefan Berger Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210525134458.6675-7-peter.maydell@linaro.org --- tests/unit/test-vmstate.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/unit/test-vmstate.c b/tests/unit/test-vmstate.c index a001879585e..4688c03ea72 100644 --- a/tests/unit/test-vmstate.c +++ b/tests/unit/test-vmstate.c @@ -40,10 +40,12 @@ static int temp_fd; /* Duplicate temp_fd and seek to the beginning of the file */ static QEMUFile *open_test_file(bool write) { - int fd =3D dup(temp_fd); + int fd; QIOChannel *ioc; QEMUFile *f; =20 + fd =3D dup(temp_fd); + g_assert(fd >=3D 0); lseek(fd, 0, SEEK_SET); if (write) { g_assert_cmpint(ftruncate(fd, 0), =3D=3D, 0); @@ -1486,6 +1488,7 @@ int main(int argc, char **argv) g_autofree char *temp_file =3D g_strdup_printf("%s/vmst.test.XXXXXX", g_get_tmp_dir()); temp_fd =3D mkstemp(temp_file); + g_assert(temp_fd >=3D 0); =20 module_call_init(MODULE_INIT_QOM); =20 --=20 2.20.1