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bh=LSx2jtQjUJeTxuXeBdmCGIP7i5svwoMufs43KL7oqsA=; b=O2AtKAgvBKEbSWhPcbZoiVQ1JbwOXCD2m037pg+WIPbBZKGtgBWdeaZDpG+/cVcYE9+zwV ErqjsB0uaA5SDfrFTTwrc0g5WDfnMZ3sqMHiU+9rPOtzpD1IHHf0mG3mnHtDtM6E7t50Jr TX3AS+gU2dw7VZwY3OG6Gu30LEK2gaY= X-MC-Unique: Md_NwRtCOISJxk-YmPxZvg-1 From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 1/4] docs: add a table showing x86-64 ABI compatibility levels Date: Mon, 7 Jun 2021 14:58:40 +0100 Message-Id: <20210607135843.196595-2-berrange@redhat.com> In-Reply-To: <20210607135843.196595-1-berrange@redhat.com> References: <20210607135843.196595-1-berrange@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=berrange@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.2, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Cleber Rosa , Paolo Bonzini Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) It is useful to know which CPUs satisfy each x86-64 ABI compatibility level, when dealing with guest OS that require something newer than the baseline ABI. These ABI levels are defined in: https://gitlab.com/x86-psABIs/x86-64-ABI/ and supported by GCC, Clang, glibc and more. Signed-off-by: Daniel P. Berrang=C3=A9 --- MAINTAINERS | 2 +- docs/system/cpu-models-x86-abi.csv | 67 ++++++++++++++++++++++++++++++ docs/system/cpu-models-x86.rst.inc | 22 ++++++++++ 3 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 docs/system/cpu-models-x86-abi.csv diff --git a/MAINTAINERS b/MAINTAINERS index 7d9cd29042..56888121ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -328,7 +328,7 @@ F: tests/tcg/i386/ F: tests/tcg/x86_64/ F: hw/i386/ F: disas/i386.c -F: docs/system/cpu-models-x86.rst.inc +F: docs/system/cpu-models-x86* T: git https://gitlab.com/ehabkost/qemu.git x86-next =20 Xtensa TCG CPUs diff --git a/docs/system/cpu-models-x86-abi.csv b/docs/system/cpu-models-x8= 6-abi.csv new file mode 100644 index 0000000000..f3f3b60be1 --- /dev/null +++ b/docs/system/cpu-models-x86-abi.csv @@ -0,0 +1,67 @@ +Model,baseline,v2,v3,v4 +486-v1,,,, +Broadwell-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Broadwell-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Broadwell-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Broadwell-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Cascadelake-Server-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Cascadelake-Server-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Cascadelake-Server-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Cascadelake-Server-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Conroe-v1,=E2=9C=85,,, +Cooperlake-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Denverton-v1,=E2=9C=85,=E2=9C=85,, +Denverton-v2,=E2=9C=85,=E2=9C=85,, +Dhyana-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +EPYC-Milan-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +EPYC-Rome-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +EPYC-Rome-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, +EPYC-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +EPYC-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, +EPYC-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Haswell-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Haswell-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Haswell-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Haswell-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Icelake-Client-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Icelake-Client-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Icelake-Server-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Icelake-Server-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Icelake-Server-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Icelake-Server-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +IvyBridge-v1,=E2=9C=85,=E2=9C=85,, +IvyBridge-v2,=E2=9C=85,=E2=9C=85,, +KnightsMill-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Nehalem-v1,=E2=9C=85,=E2=9C=85,, +Nehalem-v2,=E2=9C=85,=E2=9C=85,, +Opteron_G1-v1,=E2=9C=85,,, +Opteron_G2-v1,=E2=9C=85,,, +Opteron_G3-v1,=E2=9C=85,,, +Opteron_G4-v1,=E2=9C=85,=E2=9C=85,, +Opteron_G5-v1,=E2=9C=85,=E2=9C=85,, +Penryn-v1,=E2=9C=85,,, +SandyBridge-v1,=E2=9C=85,=E2=9C=85,, +SandyBridge-v2,=E2=9C=85,=E2=9C=85,, +Skylake-Client-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Skylake-Client-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Skylake-Client-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Skylake-Server-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Skylake-Server-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Skylake-Server-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Skylake-Server-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Snowridge-v1,=E2=9C=85,=E2=9C=85,, +Snowridge-v2,=E2=9C=85,=E2=9C=85,, +Westmere-v1,=E2=9C=85,=E2=9C=85,, +Westmere-v2,=E2=9C=85,=E2=9C=85,, +athlon-v1,,,, +core2duo-v1,=E2=9C=85,,, +coreduo-v1,,,, +kvm32-v1,,,, +kvm64-v1,=E2=9C=85,,, +n270-v1,,,, +pentium-v1,,,, +pentium2-v1,,,, +pentium3-v1,,,, +phenom-v1,=E2=9C=85,,, +qemu32-v1,,,, +qemu64-v1,=E2=9C=85,,, diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x8= 6.rst.inc index 867c8216b5..f40ee03ecc 100644 --- a/docs/system/cpu-models-x86.rst.inc +++ b/docs/system/cpu-models-x86.rst.inc @@ -39,6 +39,28 @@ CPU, as they would with "Host passthrough", but gives mu= ch of the benefit of passthrough, while making live migration safe. =20 =20 +ABI compatibility levels for CPU models +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The x86_64 architecture has a number of `ABI compatibility levels`_ +defined. Traditionally most operating systems and toolchains would +only target the original baseline ABI. It is expected that in +future OS and toolchains are likely to target newer ABIs. The +table that follows illustrates which ABI compatibility levels +can be satisfied by the QEMU CPU models. Note that the table only +lists the long term stable CPU model versions (eg Haswell-v4). +In addition to whats listed, there are also many CPU model +aliases which resolve to a different CPU model version, +depending on the machine type is in use. + +.. _ABI compatibility levels: https://gitlab.com/x86-psABIs/x86-64-ABI/ + +.. csv-table:: x86-64 ABI compatibility levels + :file: cpu-models-x86-abi.csv + :widths: 40,15,15,15,15 + :header-rows: 2 + + Preferred CPU models for Intel x86 hosts ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ =20 --=20 2.31.1 From nobody Sun May 19 14:58:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1623074667; cv=none; d=zohomail.com; s=zohoarc; b=MazBP0pubSdHCyY4n9MoAGGCN71OEInZZxsu+l3Sa8xegpv0aC0SIK9gzI4kvT99iLezDJ9+0wOt3HJPJfcOa9H+Gqhye+Bp1UOdXqFmSBKeZYsPRhzvE2sTyEvrZhokHuWE9gp80xS0LS1nslddl0G2uyaFIAlkBuQ22e2JmHM= ARC-Message-Signature: i=1; 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Mon, 7 Jun 2021 13:58:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1623074337; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IjIubWPyAzOcULJGYeGMQYxnUiYQmJrHtQiHfHN2Ctg=; b=Wb4nnE6v5CEw67LVF1qwfafVdt+aUKP0rugRwMNAi8y7+NesOtGVK96xl/ExvpEH4RMz5W Y9lWwWGmWJZjKvEGP2luyJ7nfGfRaY6muXKq21m1PUq+dBbXZq7CLT6DmY+LjLYx3TPVjY ZNjMSoE6IjPZ9An/0n8dwK4JmjQCLqg= X-MC-Unique: Ky1AMKr6OsW1FOePWP519Q-1 From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 2/4] target/i386: define CPU models to model x86-64 ABI levels Date: Mon, 7 Jun 2021 14:58:41 +0100 Message-Id: <20210607135843.196595-3-berrange@redhat.com> In-Reply-To: <20210607135843.196595-1-berrange@redhat.com> References: <20210607135843.196595-1-berrange@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; 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Tsirkin" , Richard Henderson , Cleber Rosa , Paolo Bonzini Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) To paraphrase: https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterprise= -linux-9-for-the-x86-64-v2-microarchitecture-level/ In 2020, AMD, Intel, Red Hat, and SUSE worked together to define three microarchitecture levels on top of the historical x86-64 baseline: * x86-64: original x86_64 baseline instruction set * x86-64-v2: vector instructions up to Streaming SIMD Extensions 4.2 (SSE4.2) and Supplemental Streaming SIMD Extensions 3 (SSSE3), the POPCNT instruction, and CMPXCHG16B * x86-64-v3: vector instructions up to AVX2, MOVBE, and additional bit-manipulation instructions. * x86-64-v4: vector instructions from some of the AVX-512 variants. This list of features is defined in the doc at: https://gitlab.com/x86-psABIs/x86-64-ABI/ QEMU has historically defaulted to the "qemu64" CPU model on x86_64 targets, which is approximately the x86-64 baseline ABI, with 'SVM' added. It is thought it might be desirable if QEMU could provide CPU models that closely correspond to the ABI levels, while offering portability across the maximum number of physical CPUs. Historically we've found that defining CPU models with an arbitrary combination of CPU features can be problematic, as some guest OS will not check all features they use, and instead assume that if they see feature "XX", then "YY" will always exist. This is reasonable in bare metal, but subject to breakage in virtualization. Thus in defining the CPU models for the ABI levels, this patch attempted to base them off an existing CPU model. While each x86-64-abiNNN has a designated vendor, they are designed to be vendor agnostic models. ie they are capable of running on any physical x86_64 CPU model that satisfies the ABI level. eg although the x86-64-abi2 model is based on Nehalem, it should be able to run guests on an Opteron_G4/G5/EPYC host, since those CPUs support the features required by the x86-64 v2 ABI. More precisely the models were defined as: * x86-64-abi1: close match for Opteron_G1, minus vme * x86-64-abi2: perfect match for Nehalem * x86-64-abi3: close match of Haswell-noTSX, minus aes pcid erms invpcid tsc-deadline x2apic pclmulqdq * x86-64-abi4: close match of Skylake-Server-noTSX-IBRS, minus spec-ctrl None of the CPU models declare any VMX/SVM capability features. IOW, even if a "vmx"/"svm" flag is added, it will still be unsafe to attempt to live migrate the L1 guest if there are any L2 guests running with hardware virtualization. Given their vendor agnostic design, these CPU models are primarily thought tobe useful as the default CPU model for machine types. QEMU upstream is quite conservative in mandating new hardware features, but a downstream vendor may choose to mandate a newer x86-64 ABI level for downstream only machine types. Note that TCG is not capable of supporting the 2 newest ABI levels currently due to missing features: * x86-64-abi3: CPUID.01H:ECX.fma [bit 12] CPUID.01H:ECX.avx [bit 28] CPUID.01H:ECX.f16c [bit 29] CPUID.07H:EBX.avx2 [bit 5] * x86-64-abi4: CPUID.01H:ECX.pcid [bit 17] CPUID.01H:ECX.x2apic [bit 21] CPUID.01H:ECX.tsc-deadline [bit 24] CPUID.07H:EBX.invpcid [bit 10] CPUID.07H:EBX.avx512f [bit 16] CPUID.07H:EBX.avx512dq [bit 17] CPUID.07H:EBX.rdseed [bit 18] CPUID.07H:EBX.avx512cd [bit 28] CPUID.07H:EBX.avx512bw [bit 30] CPUID.07H:EBX.avx512vl [bit 31] CPUID.80000001H:ECX.3dnowprefetch [bit 8] CPUID.0DH:EAX.xsavec [bit 1] Signed-off-by: Daniel P. Berrang=C3=A9 --- docs/system/cpu-models-x86-abi.csv | 8 ++ target/i386/cpu.c | 156 +++++++++++++++++++++++++++++ 2 files changed, 164 insertions(+) diff --git a/docs/system/cpu-models-x86-abi.csv b/docs/system/cpu-models-x8= 6-abi.csv index f3f3b60be1..3392c39753 100644 --- a/docs/system/cpu-models-x86-abi.csv +++ b/docs/system/cpu-models-x86-abi.csv @@ -65,3 +65,11 @@ pentium3-v1,,,, phenom-v1,=E2=9C=85,,, qemu32-v1,,,, qemu64-v1,=E2=9C=85,,, +x86-64-abi1,=E2=9C=85,,, +x86-64-abi1-v1,=E2=9C=85,,, +x86-64-abi2,=E2=9C=85,=E2=9C=85,, +x86-64-abi2-v1,=E2=9C=85,=E2=9C=85,, +x86-64-abi3,=E2=9C=85,=E2=9C=85,=E2=9C=85, +x86-64-abi3-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +x86-64-abi4,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +x86-64-abi4-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a9fe1662d3..e3b8a6f6f1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1711,6 +1711,162 @@ static const CPUCaches epyc_milan_cache_info =3D { */ =20 static const X86CPUDefinition builtin_x86_defs[] =3D { + /* + * These first few CPU models are designed to satisfy the + * x86_64 ABI levels defined in: + * + * https://gitlab.com/x86-psABIs/x86-64-ABI/ + * + * They were constructed as follows: + * + * - Find all the CPU models which can satisfy the ABI + * - Calculate the lowest common denominator (LCD) of these + * models' features + * - Find the named model most closely matching the LCD + * - Strip its features back to the LCD + * + * The above spec uses the "x86-64-vNN" naming convention. + * This clashes with the "vNN" suffix QEMU uses for versioning. + * Thus we use "abiNNN" as a suffix. + */ + { + /* + * Derived from Opteron_G1, minus + * vme + */ + .name =3D "x86-64-abi1", + .level =3D 5, + .vendor =3D CPUID_VENDOR_AMD, + .family =3D 15, + .model =3D 6, + .stepping =3D 1, + .features[FEAT_1_EDX] =3D + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_SSE3, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, + .xlevel =3D 0x80000008, + .model_id =3D "QEMU x86-64 baseline ABI", + }, + { + /* Derived from Nehalem */ + .name =3D "x86-64-abi2", + .level =3D 11, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 26, + .stepping =3D 3, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_LAHF_LM, + .xlevel =3D 0x80000008, + .model_id =3D "QEMU x86-64-v2 ABI", + }, + { + /* + * Derived from Haswell-noTSX, minus + * aes pcid erms invpcid tsc-deadline x2apic pclmulqdq + */ + .name =3D "x86-64-abi3", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 60, + .stepping =3D 1, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_AVX | CPUID_EXT_XSAVE | + CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_SSE3 | + CPUID_EXT_FMA | CPUID_EXT_MOVBE | + CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x80000008, + .model_id =3D "QEMU x86-64-v3 ABI", + }, + + { + /* + * Derived from Skylake-Server-noTSX-IBRS, minus: + * spec-ctrl + */ + .name =3D "x86-64-abi4", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 85, + .stepping =3D 4, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE= | + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | + CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCI= D | + CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | + CPUID_7_0_EBX_AVX512VL, + .features[FEAT_7_0_ECX] =3D + CPUID_7_0_ECX_PKU, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x80000008, + .model_id =3D "QEMU x86-64-v4 ABI", + }, + { .name =3D "qemu64", .level =3D 0xd, --=20 2.31.1 From nobody Sun May 19 14:58:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1623074677; cv=none; d=zohomail.com; s=zohoarc; b=YvrFa9t1EYH9wWvGunxeVBPHJJ6cdNFSURSyfgGJKkRzvsdjdN+85J2G2TiVA61wtL8M8qM2yas8gB+rr8IWDOSySgEaMHVBU5VkXJPfXOqgty2YFhbaYHtxC6sQfq1UTPMmFuWbacxUzDJYuDwzT4MgVg3Bf1ouiZ4nMIX7soM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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to generate x86_64 CPU ABI compat info Date: Mon, 7 Jun 2021 14:58:42 +0100 Message-Id: <20210607135843.196595-4-berrange@redhat.com> In-Reply-To: <20210607135843.196595-1-berrange@redhat.com> References: <20210607135843.196595-1-berrange@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=berrange@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.205.24.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.2, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Cleber Rosa , Paolo Bonzini Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This script is what is used to generate the docs data table in: docs/system/cpu-models-x86-abi.csv It can be useful to run if adding new CPU models / versions and the csv needs updating. Signed-off-by: Daniel P. Berrang=C3=A9 Acked-by: Eduardo Habkost --- scripts/cpu-x86-uarch-abi.py | 194 +++++++++++++++++++++++++++++++++++ 1 file changed, 194 insertions(+) create mode 100644 scripts/cpu-x86-uarch-abi.py diff --git a/scripts/cpu-x86-uarch-abi.py b/scripts/cpu-x86-uarch-abi.py new file mode 100644 index 0000000000..08acc52a81 --- /dev/null +++ b/scripts/cpu-x86-uarch-abi.py @@ -0,0 +1,194 @@ +#!/usr/bin/python3 +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# A script to generate a CSV file showing the x86_64 ABI +# compatibility levels for each CPU model. +# + +from qemu import qmp +import sys + +if len(sys.argv) !=3D 1: + print("syntax: %s QMP-SOCK\n\n" % __file__ + + "Where QMP-SOCK points to a QEMU process such as\n\n" + + " # qemu-system-x86_64 -qmp unix:/tmp/qmp,server,nowait " + + "-display none -accel kvm", file=3Dsys.stderr) + sys.exit(1) + +# Mandatory CPUID features for each microarch ABI level +levels =3D [ + [ # x86-64 baseline + "cmov", + "cx8", + "fpu", + "fxsr", + "mmx", + "syscall", + "sse", + "sse2", + ], + [ # x86-64-v2 + "cx16", + "lahf-lm", + "popcnt", + "pni", + "sse4.1", + "sse4.2", + "ssse3", + ], + [ # x86-64-v3 + "avx", + "avx2", + "bmi1", + "bmi2", + "f16c", + "fma", + "abm", + "movbe", + ], + [ # x86-64-v4 + "avx512f", + "avx512bw", + "avx512cd", + "avx512dq", + "avx512vl", + ], +] + +# Assumes externally launched process such as +# +# qemu-system-x86_64 -qmp unix:/tmp/qmp,server,nowait -display none -acc= el kvm +# +# Note different results will be obtained with TCG, as +# TCG masks out certain features otherwise present in +# the CPU model definitions, as does KVM. + + +sock =3D sys.argv[1] +cmd =3D sys.argv[2] +shell =3D qmp.QEMUMonitorProtocol(sock) +shell.connect() + +models =3D shell.cmd("query-cpu-definitions") + +# These QMP props don't correspond to CPUID fatures +# so ignore them +skip =3D [ + "family", + "min-level", + "min-xlevel", + "vendor", + "model", + "model-id", + "stepping", +] + +names =3D [] + +for model in models["return"]: + if "alias-of" in model: + continue + names.append(model["name"]) + +models =3D {} + +for name in sorted(names): + cpu =3D shell.cmd("query-cpu-model-expansion", + { "type": "static", + "model": { "name": name }}) + + got =3D {} + for (feature, present) in cpu["return"]["model"]["props"].items(): + if present and feature not in skip: + got[feature] =3D True + + if name in ["host", "max", "base"]: + continue + + models[name] =3D { + # Dict of all present features in this CPU model + "features": got, + + # Whether each x86-64 ABI level is satisfied + "levels": [False, False, False, False], + + # Number of extra CPUID features compared to the x86-64 ABI level + "distance":[-1, -1, -1, -1], + + # CPUID features present in model, but not in ABI level + "delta":[[], [], [], []], + + # CPUID features in ABI level but not present in model + "missing": [[], [], [], []], + } + + +# Calculate whether the CPU models satisfy each ABI level +for name in models.keys(): + for level in range(len(levels)): + got =3D set(models[name]["features"]) + want =3D set(levels[level]) + missing =3D want - got + match =3D True + if len(missing) > 0: + match =3D False + models[name]["levels"][level] =3D match + models[name]["missing"][level] =3D missing + +# Cache list of CPU models satisfying each ABI level +abi_models =3D [ + [], + [], + [], + [], +] + +for name in models.keys(): + for level in range(len(levels)): + if models[name]["levels"][level]: + abi_models[level].append(name) + + +for level in range(len(abi_models)): + # Find the union of features in all CPU models satisfying this ABI + allfeatures =3D {} + for name in abi_models[level]: + for feat in models[name]["features"]: + allfeatures[feat] =3D True + + # Find the intersection of features in all CPU models satisfying this = ABI + commonfeatures =3D [] + for feat in allfeatures: + present =3D True + for name in models.keys(): + if not models[name]["levels"][level]: + continue + if feat not in models[name]["features"]: + present =3D False + if present: + commonfeatures.append(feat) + + # Determine how many extra features are present compared to the lowest + # common denominator + for name in models.keys(): + if not models[name]["levels"][level]: + continue + + delta =3D set(models[name]["features"].keys()) - set(commonfeature= s) + models[name]["distance"][level] =3D len(delta) + models[name]["delta"][level] =3D delta + +def print_uarch_abi_csv(): + print("# Automatically generated from '%s'" % __file__) + print("Model,baseline,v2,v3,v4") + for name in models.keys(): + print(name, end=3D"") + for level in range(len(levels)): + if models[name]["levels"][level]: + print(",=E2=9C=85", end=3D"") + else: + print(",", end=3D"") + print() + +print_uarch_abi_csv() --=20 2.31.1 From nobody Sun May 19 14:58:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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bh=/fFaUz1XLeopnUn2h0gMRc/EfqneVbJVfK3qdt52W2Y=; b=H43T8oHUomRBmIflXp0o78hflNdzc9UqAJtMeZmwDWZE9Ls3Vh0vSpEy6kGlhEXFK/+6oP SyRtaPWXqvruGLaX2KrNyb8i61nkFzduoPQ5hwKSUUC7CEf2r/4rCwBo4AZ1PzJ7ZvzIL/ SSx598SQvMKfVBbVq4wuqnQJJMAA7rI= X-MC-Unique: 2WK-MCi2MVet9oFIJNHq3A-1 From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 4/4] NOT FOR MERGE target/i386: use x86-64-abi1 CPU model as default on x86_64 Date: Mon, 7 Jun 2021 14:58:43 +0100 Message-Id: <20210607135843.196595-5-berrange@redhat.com> In-Reply-To: <20210607135843.196595-1-berrange@redhat.com> References: <20210607135843.196595-1-berrange@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=berrange@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.205.24.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.2, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Cleber Rosa , Paolo Bonzini Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The only differences between x86-64-abi1 and qemu64 is that the former does not have the 'vme' or 'svm' flags. In practice I don't think we should make this change, because it doesn't especially add any value as-is. The only possible case is around 'svm' because KVM already masks that feature, but TCG allows it. Thus using x86-64-abi1 would mean that KVM and TCG expose a more consistent feature set. Also note that while libvirt can cope with default CPUs changing now, it can't with the default CPU being a model name that it does not already know about. Signed-off-by: Daniel P. Berrang=C3=A9 --- hw/i386/pc_piix.c | 3 +++ hw/i386/pc_q35.c | 3 +++ target/i386/cpu.h | 2 +- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 30b8bd6ea9..8f23bad647 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -444,6 +444,9 @@ static void pc_i440fx_5_2_machine_options(MachineClass = *m) m->is_default =3D false; compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); +#ifdef TARGET_X86_64 + m->default_cpu_type =3D X86_CPU_TYPE_NAME("qemu64"); +#endif } =20 DEFINE_I440FX_MACHINE(v5_2, "pc-i440fx-5.2", NULL, diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 46a0f196f4..a684c1db3b 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -372,6 +372,9 @@ static void pc_q35_5_2_machine_options(MachineClass *m) m->alias =3D NULL; compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); +#ifdef TARGET_X86_64 + m->default_cpu_type =3D X86_CPU_TYPE_NAME("qemu64"); +#endif } =20 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ac3abea97c..9b895a63c7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1999,7 +1999,7 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define CPU_RESOLVING_TYPE TYPE_X86_CPU =20 #ifdef TARGET_X86_64 -#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") +#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("x86-64-abi1") #else #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") #endif --=20 2.31.1