From nobody Sun May 5 01:47:15 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623835352880211.0070149220095; Wed, 16 Jun 2021 02:22:32 -0700 (PDT) Received: from localhost ([::1]:43332 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltRkl-0007mV-Ji for importer2@patchew.org; Wed, 16 Jun 2021 05:22:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltRbX-0004iq-G0 for qemu-devel@nongnu.org; Wed, 16 Jun 2021 05:12:59 -0400 Received: from mail02.asahi-net.or.jp ([202.224.55.14]:57991) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltRbS-00048h-Nv for qemu-devel@nongnu.org; Wed, 16 Jun 2021 05:12:59 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail02.asahi-net.or.jp (Postfix) with ESMTPA id BC00844A4D; Wed, 16 Jun 2021 18:12:50 +0900 (JST) Received: from yo-satoh-debian.localdomain (z215167.dynamic.ppp.asahi-net.or.jp [110.4.215.167]) by sakura.ysato.name (Postfix) with ESMTPSA id 2D89F1C05E1; Wed, 16 Jun 2021 18:12:50 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 1/3] hw/char: renesas_sci: Refactor for merge all SCI variant.. Date: Wed, 16 Jun 2021 18:12:42 +0900 Message-Id: <20210616091244.33049-2-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210616091244.33049-1-ysato@users.sourceforge.jp> References: <20210616091244.33049-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=202.224.55.14; envelope-from=ysato@users.sourceforge.jp; helo=mail02.asahi-net.or.jp X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL=1.31, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" In order to handle unified all of the SCI, SCIa and SCIF in one part, to separate the transmission and reception portion and a register portion. RenesasSCIBase - common registers operation and event handling. RenesasSCIA - SCIa specific reigisters / functions. Signed-off-by: Yoshinori Sato --- include/hw/char/renesas_sci.h | 80 ++++- include/hw/rx/rx62n.h | 2 +- hw/char/renesas_sci.c | 568 +++++++++++++++++++++++----------- hw/rx/rx62n.c | 2 +- 4 files changed, 457 insertions(+), 195 deletions(-) diff --git a/include/hw/char/renesas_sci.h b/include/hw/char/renesas_sci.h index a4764e3eee..c666cf81d1 100644 --- a/include/hw/char/renesas_sci.h +++ b/include/hw/char/renesas_sci.h @@ -1,7 +1,7 @@ /* * Renesas Serial Communication Interface * - * Copyright (c) 2018 Yoshinori Sato + * Copyright (c) 2020 Yoshinori Sato * * SPDX-License-Identifier: GPL-2.0-or-later */ @@ -10,45 +10,91 @@ #define HW_CHAR_RENESAS_SCI_H =20 #include "chardev/char-fe.h" +#include "qemu/timer.h" +#include "qemu/fifo8.h" #include "hw/sysbus.h" #include "qom/object.h" =20 -#define TYPE_RENESAS_SCI "renesas-sci" -typedef struct RSCIState RSCIState; -DECLARE_INSTANCE_CHECKER(RSCIState, RSCI, - TYPE_RENESAS_SCI) +#define TYPE_RENESAS_SCI_BASE "renesas-sci-base" +#define TYPE_RENESAS_SCIA "renesas-scia" + +OBJECT_DECLARE_TYPE(RenesasSCIBaseState, RenesasSCIBaseClass, + RENESAS_SCI_BASE) +OBJECT_DECLARE_TYPE(RenesasSCIAState, RenesasSCIAClass, + RENESAS_SCIA) =20 enum { ERI =3D 0, RXI =3D 1, TXI =3D 2, - TEI =3D 3, - SCI_NR_IRQ =3D 4 + BRI_TEI =3D 3, + SCI_NR_IRQ =3D 4, +}; + +enum { + RXNEXT, + TXEMPTY, + TXEND, + NR_SCI_EVENT, }; =20 -struct RSCIState { +enum { + SCI_REGWIDTH_8 =3D 8, + SCI_REGWIDTH_16 =3D 16, + SCI_REGWIDTH_32 =3D 32, +}; + +typedef struct RenesasSCIBaseState { /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ =20 MemoryRegion memory; - QEMUTimer timer; + QEMUTimer *event_timer; + + /*< public >*/ + uint64_t input_freq; + int64_t etu; + int64_t trtime; + int64_t tx_start_time; + Fifo8 rxfifo; + int regshift; + uint32_t unit; CharBackend chr; qemu_irq irq[SCI_NR_IRQ]; + struct { + int64_t time; + int64_t (*handler)(struct RenesasSCIBaseState *sci); + } event[NR_SCI_EVENT]; =20 + /* common SCI register */ uint8_t smr; uint8_t brr; uint8_t scr; uint8_t tdr; - uint8_t ssr; - uint8_t rdr; + uint16_t Xsr; +} RenesasSCIBaseState; + +struct RenesasSCIAState { + RenesasSCIBaseState parent_obj; + + /* SCIa specific register */ uint8_t scmr; uint8_t semr; - - uint8_t read_ssr; - int64_t trtime; - int64_t rx_next; - uint64_t input_freq; }; =20 +typedef struct RenesasSCIBaseClass { + SysBusDeviceClass parent; + + const struct MemoryRegionOps *ops; + void (*irq_fn)(struct RenesasSCIBaseState *sci, int request); + int (*divrate)(struct RenesasSCIBaseState *sci); +} RenesasSCIBaseClass; + +typedef struct RenesasSCIAClass { + RenesasSCIBaseClass parent; + + void (*p_irq_fn)(struct RenesasSCIBaseState *sci, int request); + int (*p_divrate)(struct RenesasSCIBaseState *sci); +} RenesasSCIAClass; + #endif diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 3ed80dba0d..d6e6e168f9 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h @@ -57,7 +57,7 @@ struct RX62NState { RXICUState icu; RTMRState tmr[RX62N_NR_TMR]; RCMTState cmt[RX62N_NR_CMT]; - RSCIState sci[RX62N_NR_SCI]; + RenesasSCIAState sci[RX62N_NR_SCI]; =20 MemoryRegion *sysmem; bool kernel; diff --git a/hw/char/renesas_sci.c b/hw/char/renesas_sci.c index 1c63467290..c1126b7817 100644 --- a/hw/char/renesas_sci.c +++ b/hw/char/renesas_sci.c @@ -4,7 +4,7 @@ * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware * (Rev.1.40 R01UH0033EJ0140) * - * Copyright (c) 2019 Yoshinori Sato + * Copyright (c) 2020 Yoshinori Sato * * SPDX-License-Identifier: GPL-2.0-or-later * @@ -23,15 +23,22 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/hw.h" #include "hw/irq.h" +#include "hw/sysbus.h" #include "hw/registerfields.h" -#include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" #include "hw/char/renesas_sci.h" #include "migration/vmstate.h" +#include "qemu/error-report.h" =20 -/* SCI register map */ -REG8(SMR, 0) +/* + * SCI register map + * SCI(a) register size all 8bit. + */ +REG32(SMR, 0) /* 8bit */ FIELD(SMR, CKS, 0, 2) FIELD(SMR, MP, 2, 1) FIELD(SMR, STOP, 3, 1) @@ -39,263 +46,447 @@ REG8(SMR, 0) FIELD(SMR, PE, 5, 1) FIELD(SMR, CHR, 6, 1) FIELD(SMR, CM, 7, 1) -REG8(BRR, 1) -REG8(SCR, 2) - FIELD(SCR, CKE, 0, 2) +REG32(BRR, 4) /* 8bit */ +REG32(SCR, 8) + FIELD(SCR, CKE, 0, 2) FIELD(SCR, TEIE, 2, 1) FIELD(SCR, MPIE, 3, 1) + FIELD(SCR, REIE, 3, 1) FIELD(SCR, RE, 4, 1) FIELD(SCR, TE, 5, 1) FIELD(SCR, RIE, 6, 1) FIELD(SCR, TIE, 7, 1) -REG8(TDR, 3) -REG8(SSR, 4) +REG32(TDR, 12) /* 8bit */ +REG32(SSR, 16) /* 8bit */ FIELD(SSR, MPBT, 0, 1) FIELD(SSR, MPB, 1, 1) FIELD(SSR, TEND, 2, 1) - FIELD(SSR, ERR, 3, 3) + FIELD(SSR, ERR, 3, 3) FIELD(SSR, PER, 3, 1) FIELD(SSR, FER, 4, 1) FIELD(SSR, ORER, 5, 1) FIELD(SSR, RDRF, 6, 1) FIELD(SSR, TDRE, 7, 1) -REG8(RDR, 5) -REG8(SCMR, 6) +REG32(RDR, 20) /* 8bit */ +REG32(SCMR, 24) /* 8bit */ FIELD(SCMR, SMIF, 0, 1) FIELD(SCMR, SINV, 2, 1) FIELD(SCMR, SDIR, 3, 1) FIELD(SCMR, BCP2, 7, 1) -REG8(SEMR, 7) +REG8(SEMR, 28) FIELD(SEMR, ACS0, 0, 1) FIELD(SEMR, ABCS, 4, 1) =20 -static int can_receive(void *opaque) +#define SCIF_FIFO_DEPTH 16 + +static int sci_can_receive(void *opaque) { - RSCIState *sci =3D RSCI(opaque); - if (sci->rx_next > qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { - return 0; + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + if (FIELD_EX16(sci->scr, SCR, RE)) { + return fifo8_num_free(&sci->rxfifo); } else { - return FIELD_EX8(sci->scr, SCR, RE); + /* Receiver disabled. can't receive. */ + return 0; } } =20 -static void receive(void *opaque, const uint8_t *buf, int size) +static void update_expire_time(RenesasSCIBaseState *sci) { - RSCIState *sci =3D RSCI(opaque); - sci->rx_next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime; - if (FIELD_EX8(sci->ssr, SSR, RDRF) || size > 1) { - sci->ssr =3D FIELD_DP8(sci->ssr, SSR, ORER, 1); - if (FIELD_EX8(sci->scr, SCR, RIE)) { - qemu_set_irq(sci->irq[ERI], 1); + int64_t next; + int i; + + next =3D INT64_MAX; + for (i =3D 0; i < NR_SCI_EVENT; i++) { + if (sci->event[i].time > 0) { + next =3D MIN(next, sci->event[i].time); } + } + if (next < INT64_MAX) { + timer_mod(sci->event_timer, next); } else { - sci->rdr =3D buf[0]; - sci->ssr =3D FIELD_DP8(sci->ssr, SSR, RDRF, 1); - if (FIELD_EX8(sci->scr, SCR, RIE)) { - qemu_irq_pulse(sci->irq[RXI]); + timer_del(sci->event_timer); + } +} + +static void update_event_time(RenesasSCIBaseState *sci, int evt, int64_t t) +{ + if (t > 0) { + t +=3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + sci->event[evt].time =3D t; + } else { + sci->event[evt].time =3D 0; + } + update_expire_time(sci); +} + +static void sci_receive(void *opaque, const uint8_t *buf, int size) +{ + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + RenesasSCIBaseClass *rc =3D RENESAS_SCI_BASE_GET_CLASS(sci); + fifo8_push_all(&sci->rxfifo, buf, size); + if (FIELD_EX16(sci->scr, SCR, RE)) { + if (sci->event[RXNEXT].time =3D=3D 0) { + /* Receiver wake up */ + sci->Xsr =3D FIELD_DP16(sci->Xsr, SSR, RDRF, 1); + rc->irq_fn(sci, RXI); + update_event_time(sci, RXNEXT, sci->trtime); } } } =20 -static void send_byte(RSCIState *sci) +static void scia_irq(RenesasSCIBaseState *sci, int req) +{ + int irq =3D 0; + int rie; + int tie; + + rie =3D FIELD_EX16(sci->scr, SCR, RIE); + tie =3D FIELD_EX16(sci->scr, SCR, TIE); + switch (req) { + case ERI: + irq =3D (FIELD_EX16(sci->Xsr, SSR, ERR) !=3D 0) && rie; + break; + case RXI: + irq =3D FIELD_EX16(sci->Xsr, SSR, RDRF) && rie; + break; + case TXI: + irq =3D FIELD_EX16(sci->Xsr, SSR, TDRE) && tie; + break; + case BRI_TEI: + irq =3D FIELD_EX16(sci->Xsr, SSR, TEND) && + FIELD_EX16(sci->scr, SCR, TEIE); + break; + } + if (req =3D=3D RXI || req =3D=3D TXI) { + if (irq) { + qemu_irq_pulse(sci->irq[req]); + } + } else { + qemu_set_irq(sci->irq[req], irq); + } +} + +static void sci_send_byte(RenesasSCIBaseState *sci) { if (qemu_chr_fe_backend_connected(&sci->chr)) { qemu_chr_fe_write_all(&sci->chr, &sci->tdr, 1); } - timer_mod(&sci->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->tr= time); - sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TEND, 0); - sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TDRE, 1); - qemu_set_irq(sci->irq[TEI], 0); - if (FIELD_EX8(sci->scr, SCR, TIE)) { - qemu_irq_pulse(sci->irq[TXI]); + sci->Xsr =3D FIELD_DP16(sci->Xsr, SSR, TEND, 0); + sci->Xsr =3D FIELD_DP16(sci->Xsr, SSR, TDRE, 1); +} + +static int64_t sci_rx_next(RenesasSCIBaseState *sci) +{ + RenesasSCIBaseClass *rc =3D RENESAS_SCI_BASE_GET_CLASS(sci); + if (!fifo8_is_empty(&sci->rxfifo)) { + /* have receive charactor */ + if (FIELD_EX16(sci->Xsr, SSR, RDRF)) { + /* Receiver overrun */ + sci->Xsr =3D FIELD_DP16(sci->Xsr, SSR, ORER, 1); + rc->irq_fn(sci, ERI); + return 0; + } + sci->Xsr =3D FIELD_DP16(sci->Xsr, SSR, RDRF, 1); + rc->irq_fn(sci, RXI); + /* next receive time */ + return sci->trtime; + } else { + /* No receive charactor. move to idle state */ + return 0; } } =20 -static void txend(void *opaque) +static int64_t sci_tx_empty(RenesasSCIBaseState *sci) { - RSCIState *sci =3D RSCI(opaque); - if (!FIELD_EX8(sci->ssr, SSR, TDRE)) { - send_byte(sci); + int64_t ret =3D 0; + RenesasSCIBaseClass *rc =3D RENESAS_SCI_BASE_GET_CLASS(sci); + if (!FIELD_EX16(sci->Xsr, SSR, TDRE)) { + sci_send_byte(sci); + ret =3D sci->trtime; + rc->irq_fn(sci, TXI); } else { - sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TEND, 1); - if (FIELD_EX8(sci->scr, SCR, TEIE)) { - qemu_set_irq(sci->irq[TEI], 1); + sci->Xsr =3D FIELD_DP16(sci->Xsr, SSR, TEND, 1); + rc->irq_fn(sci, BRI_TEI); + } + return ret; +} + +static void sci_timer_event(void *opaque) +{ + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + int64_t now, t; + int i; + + now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + for (i =3D 0; i < NR_SCI_EVENT; i++) { + if (sci->event[i].time > 0 && sci->event[i].time <=3D now) { + t =3D sci->event[i].handler(sci); + if (t > 0) { + sci->event[i].time =3D now + t; + } else { + /* No next event */ + sci->event[i].time =3D 0; + } } } + update_expire_time(sci); } =20 -static void update_trtime(RSCIState *sci) +static int scia_divrate(RenesasSCIBaseState *sci) { - /* char per bits */ - sci->trtime =3D 8 - FIELD_EX8(sci->smr, SMR, CHR); - sci->trtime +=3D FIELD_EX8(sci->smr, SMR, PE); - sci->trtime +=3D FIELD_EX8(sci->smr, SMR, STOP) + 1; - /* x bit transmit time (32 * divrate * brr) / base freq */ - sci->trtime *=3D 32 * sci->brr; - sci->trtime *=3D 1 << (2 * FIELD_EX8(sci->smr, SMR, CKS)); - sci->trtime *=3D NANOSECONDS_PER_SECOND; - sci->trtime /=3D sci->input_freq; + /* + * SEMR.ABCS =3D 0 -> 32 + * SEMR.ABCS =3D 1 -> 16 + */ + RenesasSCIAState *scia =3D RENESAS_SCIA(sci); + return 16 * (2 - FIELD_EX8(scia->semr, SEMR, ABCS)); } =20 -static bool sci_is_tr_enabled(RSCIState *sci) +static void update_trtime(RenesasSCIBaseState *sci) { - return FIELD_EX8(sci->scr, SCR, TE) || FIELD_EX8(sci->scr, SCR, RE); + RenesasSCIBaseClass *rc =3D RENESAS_SCI_BASE_GET_CLASS(sci); + int cks =3D 1 << (2 * FIELD_EX16(sci->smr, SMR, CKS)); + if (sci->input_freq > 0) { + /* x bit transmit time (divrate * brr) / base freq */ + sci->etu =3D rc->divrate(sci) * cks; + sci->etu *=3D sci->brr + 1; + sci->etu *=3D NANOSECONDS_PER_SECOND; + sci->etu /=3D sci->input_freq; + + /* char per bits */ + sci->trtime =3D 8 - FIELD_EX16(sci->smr, SMR, CHR); + sci->trtime +=3D FIELD_EX16(sci->smr, SMR, PE); + sci->trtime +=3D FIELD_EX16(sci->smr, SMR, STOP) + 1 + 1; + sci->trtime *=3D sci->etu; + } } =20 -static void sci_write(void *opaque, hwaddr offset, uint64_t val, unsigned = size) +#define IS_TR_ENABLED(scr) \ + (FIELD_EX16(scr, SCR, TE) || FIELD_EX16(scr, SCR, RE)) + +static hwaddr map_address(RenesasSCIBaseState *sci, hwaddr addr) { - RSCIState *sci =3D RSCI(opaque); + return addr << (2 - sci->regshift); +} =20 - switch (offset) { - case A_SMR: - if (!sci_is_tr_enabled(sci)) { - sci->smr =3D val; - update_trtime(sci); +static void sci_common_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + RenesasSCIBaseClass *rc =3D RENESAS_SCI_BASE_GET_CLASS(opaque); + switch (addr) { + case A_SCR: + sci->scr =3D val; + if (FIELD_EX16(sci->scr, SCR, TE)) { + /* Transmitter enable */ + sci->Xsr =3D FIELD_DP16(sci->Xsr, SSR, TDRE, 1); + sci->Xsr =3D FIELD_DP16(sci->Xsr, SSR, TEND, 1); + rc->irq_fn(sci, TXI); + rc->irq_fn(sci, BRI_TEI); + } else { + /* Transmitter disable */ + update_event_time(sci, TXEND, 0); + update_event_time(sci, TXEMPTY, 0); } break; + case A_SMR: + sci->smr =3D val; + update_trtime(sci); + break; case A_BRR: - if (!sci_is_tr_enabled(sci)) { - sci->brr =3D val; - update_trtime(sci); - } + sci->brr =3D val; + update_trtime(sci); break; - case A_SCR: - sci->scr =3D val; - if (FIELD_EX8(sci->scr, SCR, TE)) { - sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TDRE, 1); - sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TEND, 1); - if (FIELD_EX8(sci->scr, SCR, TIE)) { - qemu_irq_pulse(sci->irq[TXI]); - } - } - if (!FIELD_EX8(sci->scr, SCR, TEIE)) { - qemu_set_irq(sci->irq[TEI], 0); + default: + qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX + " not implemented\n", addr); + } +} + +static void scia_write(void *opaque, hwaddr addr, uint64_t val, unsigned s= ize) +{ + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + RenesasSCIAState *scia =3D RENESAS_SCIA(opaque); + + addr =3D map_address(sci, addr); + switch (addr) { + case A_SMR: + if (IS_TR_ENABLED(sci->scr)) { + qemu_log_mask(LOG_GUEST_ERROR, + "reneas_sci: SMR write protected.\n"); + } else { + sci_common_write(sci, addr, val, size); } - if (!FIELD_EX8(sci->scr, SCR, RIE)) { - qemu_set_irq(sci->irq[ERI], 0); + break; + case A_BRR: + if (IS_TR_ENABLED(sci->scr)) { + qemu_log_mask(LOG_GUEST_ERROR, + "reneas_sci: BRR write protected.\n"); + break; + } else { + sci_common_write(sci, addr, val, size); } break; case A_TDR: sci->tdr =3D val; - if (FIELD_EX8(sci->ssr, SSR, TEND)) { - send_byte(sci); + if (FIELD_EX16(sci->Xsr, SSR, TEND)) { + /* Transmitter wakeup */ + update_event_time(sci, TXEMPTY, sci->trtime); + sci_send_byte(sci); } else { - sci->ssr =3D FIELD_DP8(sci->ssr, SSR, TDRE, 0); + sci->Xsr =3D FIELD_DP16(sci->Xsr, SSR, TDRE, 0); } + /* Clear TEI */ + scia_irq(sci, BRI_TEI); break; case A_SSR: - sci->ssr =3D FIELD_DP8(sci->ssr, SSR, MPBT, - FIELD_EX8(val, SSR, MPBT)); - sci->ssr =3D FIELD_DP8(sci->ssr, SSR, ERR, - FIELD_EX8(val, SSR, ERR) & 0x07); - if (FIELD_EX8(sci->read_ssr, SSR, ERR) && - FIELD_EX8(sci->ssr, SSR, ERR) =3D=3D 0) { - qemu_set_irq(sci->irq[ERI], 0); + /* SSR.MBP and SSR.TEND is read only */ + val =3D FIELD_DP16(val, SSR, MPB, 1); + val =3D FIELD_DP16(val, SSR, TEND, 1); + /* SSR.RDRF and SSR.TDRE can write 1 */ + if (FIELD_EX16(val, SSR, RDRF) =3D=3D 0 || + FIELD_EX16(val, SSR, TDRE) =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "reneas_sci: SSR invalid write value %02lux.\n",= val); } - break; - case A_RDR: - qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: RDR is read only.\n"); + val =3D FIELD_DP16(val, SSR, RDRF, 1); + val =3D FIELD_DP16(val, SSR, TDRE, 1); + /* SSR.MBP and SSR.TEND is read only */ + val =3D FIELD_DP16(val, SSR, MPB, 1); + val =3D FIELD_DP16(val, SSR, TEND, 1); + /* SSR.PER, SSR.FER and SSR.ORER can write only 0 */ + sci->Xsr &=3D val; + /* SSR.MPBT can write any value */ + sci->Xsr =3D FIELD_DP16(RENESAS_SCI_BASE(sci)->Xsr, SSR, MPBT, + FIELD_EX16(val, SSR, MPBT)); + /* Clear ERI */ + scia_irq(sci, ERI); break; case A_SCMR: - sci->scmr =3D val; break; - case A_SEMR: /* SEMR */ - sci->semr =3D val; break; + scia->scmr =3D val; + break; + case A_SEMR: + scia->semr =3D val; + break; default: - qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX "= " - "not implemented\n", - offset); + sci_common_write(sci, addr, val, size); + break; } } =20 -static uint64_t sci_read(void *opaque, hwaddr offset, unsigned size) +static uint64_t sci_common_read(void *opaque, hwaddr addr, unsigned size) { - RSCIState *sci =3D RSCI(opaque); - - switch (offset) { + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + switch (addr) { case A_SMR: return sci->smr; case A_BRR: return sci->brr; case A_SCR: return sci->scr; + case A_SSR: + return sci->Xsr; case A_TDR: return sci->tdr; - case A_SSR: - sci->read_ssr =3D sci->ssr; - return sci->ssr; case A_RDR: - sci->ssr =3D FIELD_DP8(sci->ssr, SSR, RDRF, 0); - return sci->rdr; - case A_SCMR: - return sci->scmr; - case A_SEMR: - return sci->semr; + if (fifo8_num_used(&sci->rxfifo) > 0) { + return fifo8_pop(&sci->rxfifo); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "renesas_sci: Receiver underrun."); + return 0xff; + } default: qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX - " not implemented.\n", offset); + " not implemented.\n", addr); } return UINT64_MAX; } =20 -static const MemoryRegionOps sci_ops =3D { - .write =3D sci_write, - .read =3D sci_read, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .impl.max_access_size =3D 1, - .valid.max_access_size =3D 1, -}; +static uint64_t scia_read(void *opaque, hwaddr addr, unsigned size) +{ + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + RenesasSCIAState *scia =3D RENESAS_SCIA(opaque); + + addr =3D map_address(sci, addr); + switch (addr) { + case A_RDR: + sci->Xsr =3D FIELD_DP16(sci->Xsr, SSR, RDRF, 0); + return sci_common_read(sci, addr, size); + case A_SCMR: + return scia->scmr; + default: + return sci_common_read(sci, addr, size); + } + return UINT64_MAX; +} =20 -static void rsci_reset(DeviceState *dev) +static void rsci_common_init(Object *obj) { - RSCIState *sci =3D RSCI(dev); - sci->smr =3D sci->scr =3D 0x00; - sci->brr =3D 0xff; - sci->tdr =3D 0xff; - sci->rdr =3D 0x00; - sci->ssr =3D 0x84; - sci->scmr =3D 0x00; - sci->semr =3D 0x00; - sci->rx_next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(obj); + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); + int i; + + for (i =3D 0; i < SCI_NR_IRQ; i++) { + sysbus_init_irq(d, &sci->irq[i]); + } + fifo8_create(&sci->rxfifo, SCIF_FIFO_DEPTH); + sci->event_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, sci_timer_event,= sci); } =20 static void sci_event(void *opaque, QEMUChrEvent event) { - RSCIState *sci =3D RSCI(opaque); + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + RenesasSCIBaseClass *rc =3D RENESAS_SCI_BASE_GET_CLASS(sci); if (event =3D=3D CHR_EVENT_BREAK) { - sci->ssr =3D FIELD_DP8(sci->ssr, SSR, FER, 1); - if (FIELD_EX8(sci->scr, SCR, RIE)) { - qemu_set_irq(sci->irq[ERI], 1); - } + sci->Xsr =3D FIELD_DP16(sci->Xsr, SSR, FER, 1); + rc->irq_fn(sci, BRI_TEI); } } =20 -static void rsci_realize(DeviceState *dev, Error **errp) +static void rsci_common_realize(DeviceState *dev, Error **errp) { - RSCIState *sci =3D RSCI(dev); + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(dev); + int r; =20 - if (sci->input_freq =3D=3D 0) { + r =3D sci->regshift; + if ((r % 8) !=3D 0 || ((r / 8) >> 1) > 2) { qemu_log_mask(LOG_GUEST_ERROR, - "renesas_sci: input-freq property must be set."); + "renesas_sci: Invalid register size."); return; } - qemu_chr_fe_set_handlers(&sci->chr, can_receive, receive, - sci_event, NULL, sci, NULL, true); + sci->regshift =3D (r / 8) >> 1; + sci->smr =3D sci->scr =3D 0x00; + sci->brr =3D 0xff; + sci->tdr =3D 0xff; + sci->Xsr =3D 0x84; + update_trtime(sci); + } =20 -static void rsci_init(Object *obj) +static void register_mmio(RenesasSCIBaseState *sci, int size) { - SysBusDevice *d =3D SYS_BUS_DEVICE(obj); - RSCIState *sci =3D RSCI(obj); - int i; + SysBusDevice *d =3D SYS_BUS_DEVICE(sci); + RenesasSCIBaseClass *rc =3D RENESAS_SCI_BASE_GET_CLASS(sci); =20 - memory_region_init_io(&sci->memory, OBJECT(sci), &sci_ops, - sci, "renesas-sci", 0x8); + memory_region_init_io(&sci->memory, OBJECT(sci), rc->ops, + sci, "renesas-sci", size); sysbus_init_mmio(d, &sci->memory); +} =20 - for (i =3D 0; i < SCI_NR_IRQ; i++) { - sysbus_init_irq(d, &sci->irq[i]); - } - timer_init_ns(&sci->timer, QEMU_CLOCK_VIRTUAL, txend, sci); +static void rscia_realize(DeviceState *dev, Error **errp) +{ + RenesasSCIAState *sci =3D RENESAS_SCIA(dev); + RenesasSCIBaseState *common =3D RENESAS_SCI_BASE(dev); + + rsci_common_realize(dev, errp); + + register_mmio(common, 8 * (1 << common->regshift)); + qemu_chr_fe_set_handlers(&common->chr, sci_can_receive, sci_receive, + sci_event, NULL, sci, NULL, true); + + sci->scmr =3D 0x00; + sci->semr =3D 0x00; } =20 static const VMStateDescription vmstate_rsci =3D { @@ -303,49 +494,74 @@ static const VMStateDescription vmstate_rsci =3D { .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_INT64(trtime, RSCIState), - VMSTATE_INT64(rx_next, RSCIState), - VMSTATE_UINT8(smr, RSCIState), - VMSTATE_UINT8(brr, RSCIState), - VMSTATE_UINT8(scr, RSCIState), - VMSTATE_UINT8(tdr, RSCIState), - VMSTATE_UINT8(ssr, RSCIState), - VMSTATE_UINT8(rdr, RSCIState), - VMSTATE_UINT8(scmr, RSCIState), - VMSTATE_UINT8(semr, RSCIState), - VMSTATE_UINT8(read_ssr, RSCIState), - VMSTATE_TIMER(timer, RSCIState), VMSTATE_END_OF_LIST() } }; =20 static Property rsci_properties[] =3D { - DEFINE_PROP_UINT64("input-freq", RSCIState, input_freq, 0), - DEFINE_PROP_CHR("chardev", RSCIState, chr), + DEFINE_PROP_UINT64("input-freq", RenesasSCIBaseState, input_freq, 0), + DEFINE_PROP_INT32("register-size", RenesasSCIBaseState, + regshift, 0), + DEFINE_PROP_UINT32("unit", RenesasSCIBaseState, unit, 0), + DEFINE_PROP_CHR("chardev", RenesasSCIBaseState, chr), DEFINE_PROP_END_OF_LIST(), }; =20 -static void rsci_class_init(ObjectClass *klass, void *data) +static void rsci_init(Object *obj) +{ + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(obj); + sci->event[RXNEXT].handler =3D sci_rx_next; + sci->event[TXEMPTY].handler =3D sci_tx_empty; +} + +static void rsci_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - dc->realize =3D rsci_realize; dc->vmsd =3D &vmstate_rsci; - dc->reset =3D rsci_reset; device_class_set_props(dc, rsci_properties); } =20 -static const TypeInfo rsci_info =3D { - .name =3D TYPE_RENESAS_SCI, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(RSCIState), - .instance_init =3D rsci_init, - .class_init =3D rsci_class_init, +static const MemoryRegionOps scia_ops =3D { + .read =3D scia_read, + .write =3D scia_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, }; =20 -static void rsci_register_types(void) +static void rscia_class_init(ObjectClass *klass, void *data) { - type_register_static(&rsci_info); + RenesasSCIBaseClass *comm_rc =3D RENESAS_SCI_BASE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + comm_rc->ops =3D &scia_ops; + comm_rc->irq_fn =3D scia_irq; + comm_rc->divrate =3D scia_divrate; + + dc->realize =3D rscia_realize; } =20 -type_init(rsci_register_types) +static const TypeInfo renesas_sci_info[] =3D { + { + .name =3D TYPE_RENESAS_SCI_BASE, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RenesasSCIBaseState), + .instance_init =3D rsci_common_init, + .class_init =3D rsci_common_class_init, + .class_size =3D sizeof(RenesasSCIBaseClass), + .abstract =3D true, + }, + { + .name =3D TYPE_RENESAS_SCIA, + .parent =3D TYPE_RENESAS_SCI_BASE, + .instance_size =3D sizeof(RenesasSCIAState), + .instance_init =3D rsci_init, + .class_init =3D rscia_class_init, + .class_size =3D sizeof(RenesasSCIAClass), + }, +}; + +DEFINE_TYPES(renesas_sci_info) diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index fa5add9f9d..32c44ead1f 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -199,7 +199,7 @@ static void register_sci(RX62NState *s, int unit) int i, irqbase; =20 object_initialize_child(OBJECT(s), "sci[*]", - &s->sci[unit], TYPE_RENESAS_SCI); + &s->sci[unit], TYPE_RENESAS_SCIA); sci =3D SYS_BUS_DEVICE(&s->sci[unit]); qdev_prop_set_chr(DEVICE(sci), "chardev", serial_hd(unit)); qdev_prop_set_uint64(DEVICE(sci), "input-freq", s->pclk_freq_hz); --=20 2.20.1 From nobody Sun May 5 01:47:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623835211919304.3365932897801; Wed, 16 Jun 2021 02:20:11 -0700 (PDT) Received: from localhost ([::1]:40074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltRiU-0005Sb-Lu for importer2@patchew.org; Wed, 16 Jun 2021 05:20:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41008) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltRbX-0004iI-8x for qemu-devel@nongnu.org; Wed, 16 Jun 2021 05:12:59 -0400 Received: from mail02.asahi-net.or.jp ([202.224.55.14]:57993) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltRbS-00048j-OS for qemu-devel@nongnu.org; Wed, 16 Jun 2021 05:12:59 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail02.asahi-net.or.jp (Postfix) with ESMTPA id DBD1544A53; Wed, 16 Jun 2021 18:12:50 +0900 (JST) Received: from yo-satoh-debian.localdomain (z215167.dynamic.ppp.asahi-net.or.jp [110.4.215.167]) by sakura.ysato.name (Postfix) with ESMTPSA id 748C21C06CF; Wed, 16 Jun 2021 18:12:50 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 2/3] hw/char: renesas_sci Add SCI and SCIF support. Date: Wed, 16 Jun 2021 18:12:43 +0900 Message-Id: <20210616091244.33049-3-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210616091244.33049-1-ysato@users.sourceforge.jp> References: <20210616091244.33049-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=202.224.55.14; envelope-from=ysato@users.sourceforge.jp; helo=mail02.asahi-net.or.jp X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL=1.31, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This peripheral using SH7750. Signed-off-by: Yoshinori Sato --- include/hw/char/renesas_sci.h | 43 ++- hw/char/renesas_sci.c | 489 ++++++++++++++++++++++++++++++++++ 2 files changed, 531 insertions(+), 1 deletion(-) diff --git a/include/hw/char/renesas_sci.h b/include/hw/char/renesas_sci.h index c666cf81d1..aa6be53628 100644 --- a/include/hw/char/renesas_sci.h +++ b/include/hw/char/renesas_sci.h @@ -16,12 +16,18 @@ #include "qom/object.h" =20 #define TYPE_RENESAS_SCI_BASE "renesas-sci-base" +#define TYPE_RENESAS_SCI "renesas-sci" #define TYPE_RENESAS_SCIA "renesas-scia" +#define TYPE_RENESAS_SCIF "renesas-scif" =20 OBJECT_DECLARE_TYPE(RenesasSCIBaseState, RenesasSCIBaseClass, RENESAS_SCI_BASE) +OBJECT_DECLARE_TYPE(RenesasSCIState, RenesasSCIClass, + RENESAS_SCI) OBJECT_DECLARE_TYPE(RenesasSCIAState, RenesasSCIAClass, RENESAS_SCIA) +OBJECT_DECLARE_TYPE(RenesasSCIFState, RenesasSCIFClass, + RENESAS_SCIF) =20 enum { ERI =3D 0, @@ -32,6 +38,7 @@ enum { }; =20 enum { + RXTOUT, RXNEXT, TXEMPTY, TXEND, @@ -49,13 +56,14 @@ typedef struct RenesasSCIBaseState { SysBusDevice parent_obj; =20 MemoryRegion memory; + MemoryRegion memory_p4; + MemoryRegion memory_a7; QEMUTimer *event_timer; =20 /*< public >*/ uint64_t input_freq; int64_t etu; int64_t trtime; - int64_t tx_start_time; Fifo8 rxfifo; int regshift; uint32_t unit; @@ -65,6 +73,7 @@ typedef struct RenesasSCIBaseState { int64_t time; int64_t (*handler)(struct RenesasSCIBaseState *sci); } event[NR_SCI_EVENT]; + uint16_t read_Xsr; =20 /* common SCI register */ uint8_t smr; @@ -74,6 +83,13 @@ typedef struct RenesasSCIBaseState { uint16_t Xsr; } RenesasSCIBaseState; =20 +struct RenesasSCIState { + RenesasSCIBaseState parent_obj; + + /* SCI specific register */ + uint8_t sptr; +}; + struct RenesasSCIAState { RenesasSCIBaseState parent_obj; =20 @@ -82,6 +98,19 @@ struct RenesasSCIAState { uint8_t semr; }; =20 +struct RenesasSCIFState { + RenesasSCIBaseState parent_obj; + + /* SCIF specific register */ + uint16_t fcr; + uint16_t sptr; + uint16_t lsr; + + /* private */ + int64_t tx_fifo_top_t; + int txremain; +}; + typedef struct RenesasSCIBaseClass { SysBusDeviceClass parent; =20 @@ -90,6 +119,12 @@ typedef struct RenesasSCIBaseClass { int (*divrate)(struct RenesasSCIBaseState *sci); } RenesasSCIBaseClass; =20 +typedef struct RenesasSCIClass { + RenesasSCIBaseClass parent; + + void (*p_irq_fn)(struct RenesasSCIBaseState *sci, int request); +} RenesasSCIClass; + typedef struct RenesasSCIAClass { RenesasSCIBaseClass parent; =20 @@ -97,4 +132,10 @@ typedef struct RenesasSCIAClass { int (*p_divrate)(struct RenesasSCIBaseState *sci); } RenesasSCIAClass; =20 +typedef struct RenesasSCIFClass { + RenesasSCIBaseClass parent; + + void (*p_irq_fn)(struct RenesasSCIBaseState *sci, int request); +} RenesasSCIFClass; + #endif diff --git a/hw/char/renesas_sci.c b/hw/char/renesas_sci.c index c1126b7817..ba304fa1fa 100644 --- a/hw/char/renesas_sci.c +++ b/hw/char/renesas_sci.c @@ -3,6 +3,8 @@ * * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware * (Rev.1.40 R01UH0033EJ0140) + * And SH7751 Group, SH7751R Group User's Manual: Hardware + * (Rev.4.01 R01UH0457EJ0401) * * Copyright (c) 2020 Yoshinori Sato * @@ -67,17 +69,58 @@ REG32(SSR, 16) /* 8bit */ FIELD(SSR, ORER, 5, 1) FIELD(SSR, RDRF, 6, 1) FIELD(SSR, TDRE, 7, 1) +REG32(FSR, 16) + FIELD(FSR, DR, 0, 1) + FIELD(FSR, RDF, 1, 1) + FIELD(FSR, RDF_DR, 0, 2) + FIELD(FSR, PER, 2, 1) + FIELD(FSR, FER, 3, 1) + FIELD(FSR, BRK, 4, 1) + FIELD(FSR, TDFE, 5, 1) + FIELD(FSR, TEND, 6, 1) + FIELD(FSR, ER, 7, 1) + FIELD(FSR, FERn, 8, 4) + FIELD(FSR, PERn, 12, 4) REG32(RDR, 20) /* 8bit */ REG32(SCMR, 24) /* 8bit */ FIELD(SCMR, SMIF, 0, 1) FIELD(SCMR, SINV, 2, 1) FIELD(SCMR, SDIR, 3, 1) FIELD(SCMR, BCP2, 7, 1) +REG32(FCR, 24) + FIELD(FCR, LOOP, 0, 1) + FIELD(FCR, RFRST, 1, 1) + FIELD(FCR, TFRST, 2, 1) + FIELD(FCR, MCE, 3, 1) + FIELD(FCR, TTRG, 4, 2) + FIELD(FCR, RTRG, 6, 2) + FIELD(FCR, RSTRG, 8, 3) REG8(SEMR, 28) FIELD(SEMR, ACS0, 0, 1) FIELD(SEMR, ABCS, 4, 1) +REG32(FDR, 28) + FIELD(FDR, Rn, 0, 4) + FIELD(FDR, Tn, 8, 4) +REG32(SPTR, 32) + FIELD(SPTR, SPB2DT, 0, 1) + FIELD(SPTR, SPB2IO, 1, 1) + FIELD(SPTR, SCKDT, 2, 1) + FIELD(SPTR, SCKIO, 3, 1) + FIELD(SPTR, CTSDT, 4, 1) + FIELD(SPTR, CTSIO, 5, 1) + FIELD(SPTR, RTSDT, 6, 1) + FIELD(SPTR, RTSIO, 7, 1) + FIELD(SPTR, EIO, 7, 1) +REG32(LSR, 36) + FIELD(LSR, ORER, 0, 1) =20 #define SCIF_FIFO_DEPTH 16 +static const int scif_rtrg[] =3D {1, 4, 8, 14}; +/* TTRG =3D 0 - 8byte */ +/* TTRG =3D 1 - 4byte */ +/* TTRG =3D 2 - 2byte */ +/* TTRG =3D 3 - 1byte */ +#define scif_ttrg(scif) (1 << (3 - FIELD_EX16(scif->fcr, FCR, TTRG))) =20 static int sci_can_receive(void *opaque) { @@ -134,6 +177,71 @@ static void sci_receive(void *opaque, const uint8_t *b= uf, int size) } } =20 +static int scif_can_receive(void *opaque) +{ + RenesasSCIFState *scif =3D RENESAS_SCIF(opaque); + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + RenesasSCIBaseClass *rc =3D RENESAS_SCI_BASE_GET_CLASS(sci); + int fifo_free =3D 0; + if (FIELD_EX16(sci->scr, SCR, RE)) { + /* Receiver enabled */ + fifo_free =3D fifo8_num_free(&sci->rxfifo); + if (fifo_free =3D=3D 0) { + /* FIFO overrun */ + scif->lsr =3D FIELD_DP16(scif->lsr, LSR, ORER, 1); + rc->irq_fn(sci, ERI); + } + } + return fifo_free; +} + +static void scif_receive(void *opaque, const uint8_t *buf, int size) +{ + RenesasSCIFState *scif =3D RENESAS_SCIF(opaque); + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + RenesasSCIBaseClass *rc =3D RENESAS_SCI_BASE_GET_CLASS(sci); + int rtrg; + + fifo8_push_all(&sci->rxfifo, buf, size); + if (sci->event[RXNEXT].time =3D=3D 0) { + rtrg =3D scif_rtrg[FIELD_EX16(scif->fcr, FCR, RTRG)]; + if (fifo8_num_used(&sci->rxfifo) >=3D rtrg) { + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, RDF, 1); + rc->irq_fn(sci, RXI); + } else { + update_event_time(sci, RXTOUT, 15 * sci->etu); + } + } +} + +static void sci_irq(RenesasSCIBaseState *sci_common, int req) +{ + int irq =3D 0; + int rie; + int tie; + RenesasSCIState *sci =3D RENESAS_SCI(sci_common); + + rie =3D FIELD_EX16(sci_common->scr, SCR, RIE); + tie =3D FIELD_EX16(sci_common->scr, SCR, TIE); + switch (req) { + case ERI: + irq =3D rie && (FIELD_EX16(sci_common->Xsr, SSR, ERR) !=3D 0); + break; + case RXI: + irq =3D FIELD_EX16(sci_common->Xsr, SSR, RDRF) && rie && + !FIELD_EX16(sci->sptr, SPTR, EIO); + break; + case TXI: + irq =3D FIELD_EX16(sci_common->Xsr, SSR, TDRE) && tie; + break; + case BRI_TEI: + irq =3D FIELD_EX16(sci_common->Xsr, SSR, TEND) && + FIELD_EX16(sci_common->scr, SCR, TEIE); + break; + } + qemu_set_irq(sci_common->irq[req], irq); +} + static void scia_irq(RenesasSCIBaseState *sci, int req) { int irq =3D 0; @@ -166,6 +274,33 @@ static void scia_irq(RenesasSCIBaseState *sci, int req) } } =20 +static void scif_irq(RenesasSCIBaseState *sci, int req) +{ + int irq =3D 0; + int rie; + int reie; + int tie; + + rie =3D FIELD_EX16(sci->scr, SCR, RIE); + reie =3D FIELD_EX16(sci->scr, SCR, REIE); + tie =3D FIELD_EX16(sci->scr, SCR, TIE); + switch (req) { + case ERI: + irq =3D (rie || reie) && FIELD_EX16(sci->Xsr, FSR, ER); + break; + case RXI: + irq =3D (FIELD_EX16(sci->Xsr, FSR, RDF_DR) !=3D 0) && rie; + break; + case TXI: + irq =3D FIELD_EX16(sci->Xsr, FSR, TDFE) & tie; + break; + case BRI_TEI: + irq =3D (rie || reie) && FIELD_EX16(sci->Xsr, FSR, BRK); + break; + } + qemu_set_irq(sci->irq[req], irq); +} + static void sci_send_byte(RenesasSCIBaseState *sci) { if (qemu_chr_fe_backend_connected(&sci->chr)) { @@ -211,6 +346,46 @@ static int64_t sci_tx_empty(RenesasSCIBaseState *sci) return ret; } =20 +static int scif_txremain_byte(RenesasSCIFState *scif) +{ + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(scif); + int64_t now, elapsed; + int byte =3D 0; + if (scif->tx_fifo_top_t > 0) { + now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + elapsed =3D now - scif->tx_fifo_top_t; + scif->tx_fifo_top_t =3D now; + byte =3D elapsed / sci->trtime + 1; + byte =3D MIN(scif->txremain, byte); + } + scif->txremain -=3D byte; + return scif->txremain; +} + +static int64_t scif_rx_timeout(RenesasSCIBaseState *sci) +{ + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, DR, 1); + scif_irq(sci, RXI); + return 0; +} + +static int64_t scif_tx_empty(RenesasSCIBaseState *sci) +{ + RenesasSCIFState *scif =3D RENESAS_SCIF(sci); + scif_txremain_byte(scif); + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, TDFE, 1); + scif_irq(sci, TXI); + return 0; +} + +static int64_t scif_tx_end(RenesasSCIBaseState *sci) +{ + RenesasSCIFState *scif =3D RENESAS_SCIF(sci); + scif->txremain =3D 0; + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, TEND, 1); + return 0; +} + static void sci_timer_event(void *opaque) { RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); @@ -232,6 +407,12 @@ static void sci_timer_event(void *opaque) update_expire_time(sci); } =20 +static int sci_divrate(RenesasSCIBaseState *sci) +{ + /* SCI / SCIF have static divide rate */ + return 32; +} + static int scia_divrate(RenesasSCIBaseState *sci) { /* @@ -303,6 +484,45 @@ static void sci_common_write(void *opaque, hwaddr addr, } } =20 +static void sci_write(void *opaque, hwaddr addr, uint64_t val, unsigned si= ze) +{ + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + RenesasSCIBaseClass *rc =3D RENESAS_SCI_BASE_GET_CLASS(sci); + bool tdre_reset; + + addr =3D map_address(sci, addr); + switch (addr) { + case A_TDR: + sci->tdr =3D val; + break; + case A_SSR: + /* SSR.MBP and SSR.TEND is read only */ + val =3D FIELD_DP16(val, SSR, MPB, 1); + val =3D FIELD_DP16(val, SSR, TEND, 1); + /* SSR can write only 0 */ + sci->Xsr &=3D val; + /* SSR.MPBT can write any value */ + sci->Xsr =3D FIELD_DP16(RENESAS_SCI_BASE(sci)->Xsr, SSR, MPBT, + FIELD_EX16(val, SSR, MPBT)); + /* Clear ERI */ + rc->irq_fn(sci, ERI); + /* Is TX start operation ? */ + tdre_reset =3D FIELD_EX16(sci->read_Xsr, SSR, TDRE) && + !FIELD_EX16(sci->Xsr, SSR, TDRE); + if (tdre_reset && FIELD_EX16(sci->Xsr, SSR, ERR) =3D=3D 0) { + sci_send_byte(sci); + update_event_time(sci, TXEMPTY, sci->trtime); + rc->irq_fn(sci, TXI); + } + break; + case A_SPTR: + RENESAS_SCI(sci)->sptr =3D val; + break; + default: + sci_common_write(sci, addr, val, size); + } +} + static void scia_write(void *opaque, hwaddr addr, uint64_t val, unsigned s= ize) { RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); @@ -374,6 +594,120 @@ static void scia_write(void *opaque, hwaddr addr, uin= t64_t val, unsigned size) } } =20 +static void scif_write(void *opaque, hwaddr addr, uint64_t val, unsigned s= ize) +{ + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + RenesasSCIFState *scif =3D RENESAS_SCIF(opaque); + int txtrg; + int rxtrg; + uint8_t txd; + + addr =3D map_address(sci, addr); + switch (addr) { + case A_SCR: + sci->scr =3D val; + if (FIELD_EX16(sci->scr, SCR, TE)) { + /* Transmiter enable */ + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, TEND, 1); + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, TDFE, 1); + scif->tx_fifo_top_t =3D 0; + scif_irq(sci, TXI); + } else { + /* Transmiter disable */ + update_event_time(sci, TXEND, 0); + update_event_time(sci, TXEMPTY, 0); + } + break; + case A_TDR: + if (scif->tx_fifo_top_t > 0) { + if (scif_txremain_byte(scif) >=3D SCIF_FIFO_DEPTH) { + qemu_log_mask(LOG_GUEST_ERROR, + "reneas_sci: Tx FIFO is full."); + break; + } + } else { + scif->tx_fifo_top_t =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } + txd =3D val; + if (qemu_chr_fe_backend_connected(&sci->chr)) { + qemu_chr_fe_write_all(&sci->chr, &txd, 1); + } + if (FIELD_EX16(scif->fcr, FCR, LOOP) && scif_can_receive(sci) > 0)= { + /* Loopback mode */ + scif_receive(sci, &txd, 1); + } + scif->txremain++; + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, TEND, 0); + update_event_time(sci, TXEND, scif->txremain * sci->trtime); + txtrg =3D scif_ttrg(scif); + if (scif->txremain > txtrg) { + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, TDFE, 0); + update_event_time(sci, TXEMPTY, + (scif->txremain - txtrg) * sci->trtime); + scif_irq(sci, TXI); + } + break; + case A_FSR: + rxtrg =3D scif_rtrg[FIELD_EX16(scif->fcr, FCR, RTRG)]; + txtrg =3D scif_ttrg(scif); + /* FSR.FER and FSR.PER read only. Keep old value. */ + val =3D FIELD_DP16(val, FSR, FER, 1); + val =3D FIELD_DP16(val, FSR, PER, 1); + val =3D FIELD_DP16(val, FSR, FERn, 15); + val =3D FIELD_DP16(val, FSR, PERn, 15); + if (scif_txremain_byte(scif) <=3D txtrg) { + /* It cannot be cleared when FIFO is free. */ + val =3D FIELD_DP16(val, FSR, TDFE, 1); + } + if (fifo8_num_used(&sci->rxfifo) >=3D rxtrg) { + /* It cannot be cleared when FIFO is full. */ + val =3D FIELD_DP16(val, FSR, TDFE, 1); + } + if (scif->txremain =3D=3D 0) { + /* It cannot be cleared when FIFO is not empty. */ + val =3D FIELD_DP16(val, FSR, TEND, 1); + } + sci->Xsr &=3D val; + scif_irq(sci, ERI); + scif_irq(sci, RXI); + scif_irq(sci, TXI); + break; + case A_FCR: + scif->fcr =3D val; + if (FIELD_EX16(scif->fcr, FCR, RFRST)) { + fifo8_reset(&sci->rxfifo); + update_event_time(sci, RXTOUT, 0); + update_event_time(sci, RXNEXT, 0); + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, ER, 0); + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, BRK, 0); + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, FER, 0); + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, PER, 0); + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, RDF_DR, 0); + } + if (FIELD_EX16(scif->fcr, FCR, TFRST)) { + scif->txremain =3D 0; + update_event_time(sci, TXEMPTY, 0); + update_event_time(sci, TXEND, 0); + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, TEND, 1); + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, TDFE, 1); + } + break; + case A_FDR: + qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: FDR is read only.\n"); + break; + case A_SPTR: + scif->sptr =3D val; + break; + case A_LSR: + scif->lsr &=3D val; + scif_irq(sci, ERI); + break; + default: + sci_common_write(sci, addr, val, size); + break; + } +} + static uint64_t sci_common_read(void *opaque, hwaddr addr, unsigned size) { RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); @@ -385,6 +719,7 @@ static uint64_t sci_common_read(void *opaque, hwaddr ad= dr, unsigned size) case A_SCR: return sci->scr; case A_SSR: + sci->read_Xsr =3D sci->Xsr; return sci->Xsr; case A_TDR: return sci->tdr; @@ -403,6 +738,20 @@ static uint64_t sci_common_read(void *opaque, hwaddr a= ddr, unsigned size) return UINT64_MAX; } =20 +static uint64_t sci_read(void *opaque, hwaddr addr, unsigned size) +{ + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + addr =3D map_address(sci, addr); + + switch (addr) { + case A_SPTR: + return RENESAS_SCI(sci)->sptr; + default: + return sci_common_read(sci, addr, size); + } + return UINT64_MAX; +} + static uint64_t scia_read(void *opaque, hwaddr addr, unsigned size) { RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); @@ -421,6 +770,34 @@ static uint64_t scia_read(void *opaque, hwaddr addr, u= nsigned size) return UINT64_MAX; } =20 +static uint64_t scif_read(void *opaque, hwaddr addr, unsigned size) +{ + RenesasSCIFState *scif =3D RENESAS_SCIF(opaque); + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + uint64_t ret; + + addr =3D map_address(sci, addr); + switch (addr) { + case A_TDR: + qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: TDR is write only.\n"); + return UINT64_MAX; + case A_FCR: + return scif->fcr & 0x7ff; + case A_FDR: + ret =3D 0; + ret =3D FIELD_DP16(ret, FDR, Rn, fifo8_num_used(&sci->rxfifo)); + ret =3D FIELD_DP16(ret, FDR, Tn, scif_txremain_byte(scif)); + return ret; + case A_SPTR: + return scif->sptr; + case A_LSR: + return scif->lsr; + default: + return sci_common_read(sci, addr, size); + } + return UINT64_MAX; +} + static void rsci_common_init(Object *obj) { RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(obj); @@ -444,6 +821,15 @@ static void sci_event(void *opaque, QEMUChrEvent event) } } =20 +static void scif_event(void *opaque, QEMUChrEvent event) +{ + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(opaque); + if (event =3D=3D CHR_EVENT_BREAK) { + sci->Xsr =3D FIELD_DP16(sci->Xsr, FSR, BRK, 1); + scif_irq(sci, BRI_TEI); + } +} + static void rsci_common_realize(DeviceState *dev, Error **errp) { RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(dev); @@ -472,6 +858,26 @@ static void register_mmio(RenesasSCIBaseState *sci, in= t size) memory_region_init_io(&sci->memory, OBJECT(sci), rc->ops, sci, "renesas-sci", size); sysbus_init_mmio(d, &sci->memory); + memory_region_init_alias(&sci->memory_p4, NULL, "renesas-sci-p4", + &sci->memory, 0, size); + sysbus_init_mmio(d, &sci->memory_p4); + memory_region_init_alias(&sci->memory_a7, NULL, "renesas-sci-a7", + &sci->memory, 0, size); + sysbus_init_mmio(d, &sci->memory_a7); +} + +static void rsci_realize(DeviceState *dev, Error **errp) +{ + RenesasSCIState *sci =3D RENESAS_SCI(dev); + RenesasSCIBaseState *common =3D RENESAS_SCI_BASE(dev); + + rsci_common_realize(dev, errp); + + register_mmio(common, 8 * (1 << common->regshift)); + qemu_chr_fe_set_handlers(&common->chr, sci_can_receive, sci_receive, + sci_event, NULL, sci, NULL, true); + + sci->sptr =3D 0x00; } =20 static void rscia_realize(DeviceState *dev, Error **errp) @@ -489,6 +895,22 @@ static void rscia_realize(DeviceState *dev, Error **er= rp) sci->semr =3D 0x00; } =20 +static void rscif_realize(DeviceState *dev, Error **errp) +{ + RenesasSCIFState *sci =3D RENESAS_SCIF(dev); + RenesasSCIBaseState *common =3D RENESAS_SCI_BASE(sci); + + rsci_common_realize(dev, errp); + + register_mmio(common, 10 * (1 << common->regshift)); + qemu_chr_fe_set_handlers(&common->chr, scif_can_receive, scif_receive, + scif_event, NULL, sci, NULL, true); + common->Xsr =3D 0x0060; + sci->fcr =3D 0x0000; + sci->sptr =3D 0x0000; + sci->lsr =3D 0x0000; +} + static const VMStateDescription vmstate_rsci =3D { .name =3D "renesas-sci", .version_id =3D 1, @@ -514,6 +936,14 @@ static void rsci_init(Object *obj) sci->event[TXEMPTY].handler =3D sci_tx_empty; } =20 +static void rscif_init(Object *obj) +{ + RenesasSCIBaseState *sci =3D RENESAS_SCI_BASE(obj); + sci->event[RXTOUT].handler =3D scif_rx_timeout; + sci->event[TXEMPTY].handler =3D scif_tx_empty; + sci->event[TXEND].handler =3D scif_tx_end; +} + static void rsci_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -522,6 +952,27 @@ static void rsci_common_class_init(ObjectClass *klass,= void *data) device_class_set_props(dc, rsci_properties); } =20 +static const MemoryRegionOps sci_ops =3D { + .read =3D sci_read, + .write =3D sci_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void rsci_class_init(ObjectClass *klass, void *data) +{ + RenesasSCIBaseClass *comm_rc =3D RENESAS_SCI_BASE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + comm_rc->ops =3D &sci_ops; + comm_rc->irq_fn =3D sci_irq; + comm_rc->divrate =3D sci_divrate; + dc->realize =3D rsci_realize; +} + static const MemoryRegionOps scia_ops =3D { .read =3D scia_read, .write =3D scia_write, @@ -544,6 +995,28 @@ static void rscia_class_init(ObjectClass *klass, void = *data) dc->realize =3D rscia_realize; } =20 +static const MemoryRegionOps scif_ops =3D { + .read =3D scif_read, + .write =3D scif_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void rscif_class_init(ObjectClass *klass, void *data) +{ + RenesasSCIBaseClass *comm_rc =3D RENESAS_SCI_BASE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + comm_rc->ops =3D &scif_ops; + comm_rc->irq_fn =3D scif_irq; + comm_rc->divrate =3D sci_divrate; + + dc->realize =3D rscif_realize; +} + static const TypeInfo renesas_sci_info[] =3D { { .name =3D TYPE_RENESAS_SCI_BASE, @@ -554,6 +1027,14 @@ static const TypeInfo renesas_sci_info[] =3D { .class_size =3D sizeof(RenesasSCIBaseClass), .abstract =3D true, }, + { + .name =3D TYPE_RENESAS_SCI, + .parent =3D TYPE_RENESAS_SCI_BASE, + .instance_size =3D sizeof(RenesasSCIState), + .instance_init =3D rsci_init, + .class_init =3D rsci_class_init, + .class_size =3D sizeof(RenesasSCIClass), + }, { .name =3D TYPE_RENESAS_SCIA, .parent =3D TYPE_RENESAS_SCI_BASE, @@ -562,6 +1043,14 @@ static const TypeInfo renesas_sci_info[] =3D { .class_init =3D rscia_class_init, .class_size =3D sizeof(RenesasSCIAClass), }, + { + .name =3D TYPE_RENESAS_SCIF, + .parent =3D TYPE_RENESAS_SCI_BASE, + .instance_size =3D sizeof(RenesasSCIFState), + .instance_init =3D rscif_init, + .class_init =3D rscif_class_init, + .class_size =3D sizeof(RenesasSCIFClass), + }, }; =20 DEFINE_TYPES(renesas_sci_info) --=20 2.20.1 From nobody Sun May 5 01:47:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623834859185281.70628228024066; Wed, 16 Jun 2021 02:14:19 -0700 (PDT) Received: from localhost ([::1]:56668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltRco-00060g-4k for importer2@patchew.org; Wed, 16 Jun 2021 05:14:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltRbU-0004gi-Sm for qemu-devel@nongnu.org; Wed, 16 Jun 2021 05:12:57 -0400 Received: from mail02.asahi-net.or.jp ([202.224.55.14]:57994) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltRbS-00048k-Nd for qemu-devel@nongnu.org; Wed, 16 Jun 2021 05:12:56 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail02.asahi-net.or.jp (Postfix) with ESMTPA id 2624744A54; Wed, 16 Jun 2021 18:12:51 +0900 (JST) Received: from yo-satoh-debian.localdomain (z215167.dynamic.ppp.asahi-net.or.jp [110.4.215.167]) by sakura.ysato.name (Postfix) with ESMTPSA id C41391C06F8; Wed, 16 Jun 2021 18:12:50 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH 3/3] hw/sh4: sh7750 using renesas_sci. Date: Wed, 16 Jun 2021 18:12:44 +0900 Message-Id: <20210616091244.33049-4-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210616091244.33049-1-ysato@users.sourceforge.jp> References: <20210616091244.33049-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=202.224.55.14; envelope-from=ysato@users.sourceforge.jp; helo=mail02.asahi-net.or.jp X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL=1.31, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Yoshinori Sato --- include/hw/sh4/sh.h | 8 -------- hw/sh4/sh7750.c | 41 +++++++++++++++++++++++++++++++++++++++++ hw/sh4/Kconfig | 2 +- 3 files changed, 42 insertions(+), 9 deletions(-) diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index becb596979..74e1ba59a8 100644 --- a/include/hw/sh4/sh.h +++ b/include/hw/sh4/sh.h @@ -55,14 +55,6 @@ int sh7750_register_io_device(struct SH7750State *s, =20 /* sh_serial.c */ #define SH_SERIAL_FEAT_SCIF (1 << 0) -void sh_serial_init(MemoryRegion *sysmem, - hwaddr base, int feat, - uint32_t freq, Chardev *chr, - qemu_irq eri_source, - qemu_irq rxi_source, - qemu_irq txi_source, - qemu_irq tei_source, - qemu_irq bri_source); =20 /* sh7750.c */ qemu_irq sh7750_irl(struct SH7750State *s); diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index d53a436d8c..1ef8b73c65 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -24,6 +24,7 @@ */ =20 #include "qemu/osdep.h" +#include "qapi/error.h" #include "hw/irq.h" #include "hw/sh4/sh.h" #include "sysemu/sysemu.h" @@ -32,6 +33,8 @@ #include "hw/sh4/sh_intc.h" #include "hw/timer/tmu012.h" #include "exec/exec-all.h" +#include "hw/char/renesas_sci.h" +#include "hw/qdev-properties.h" =20 #define NB_DEVICES 4 =20 @@ -752,6 +755,44 @@ static const MemoryRegionOps sh7750_mmct_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static void sh_serial_init(MemoryRegion *sysmem, + hwaddr base, int feat, + uint32_t freq, Chardev *chr, + qemu_irq eri_source, + qemu_irq rxi_source, + qemu_irq txi_source, + qemu_irq tei_source, + qemu_irq bri_source) +{ + RenesasSCIBaseState *sci; + char ckname[16]; + + switch(feat) { + case 0: /* SCI */ + sci =3D RENESAS_SCI_BASE(qdev_new(TYPE_RENESAS_SCI)); + snprintf(ckname, sizeof(ckname), "pck_sci"); + break; + case SH_SERIAL_FEAT_SCIF: + sci =3D RENESAS_SCI_BASE(qdev_new(TYPE_RENESAS_SCIF)); + snprintf(ckname, sizeof(ckname), "pck_scif"); + break; + } + qdev_prop_set_chr(DEVICE(sci), "chardev", chr); + qdev_prop_set_uint32(DEVICE(sci), "register-size", SCI_REGWIDTH_32); + qdev_prop_set_uint64(DEVICE(sci), "input-freq", freq); + sysbus_connect_irq(SYS_BUS_DEVICE(sci), 0, eri_source); + sysbus_connect_irq(SYS_BUS_DEVICE(sci), 1, rxi_source); + sysbus_connect_irq(SYS_BUS_DEVICE(sci), 2, txi_source); + if (tei_source) + sysbus_connect_irq(SYS_BUS_DEVICE(sci), 3, tei_source); + if (bri_source) + sysbus_connect_irq(SYS_BUS_DEVICE(sci), 3, bri_source); + sysbus_realize(SYS_BUS_DEVICE(sci), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(sci), 0, base); + sysbus_mmio_map(SYS_BUS_DEVICE(sci), 1, P4ADDR(base)); + sysbus_mmio_map(SYS_BUS_DEVICE(sci), 2, A7ADDR(base)); +} + SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) { SH7750State *s; diff --git a/hw/sh4/Kconfig b/hw/sh4/Kconfig index ab733a3f76..d23d5f5b1c 100644 --- a/hw/sh4/Kconfig +++ b/hw/sh4/Kconfig @@ -20,5 +20,5 @@ config SHIX config SH7750 bool select SH_INTC - select SH_SCI + select RENESAS_SCI select SH_TIMER --=20 2.20.1