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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=laramglazier@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lara Lazier Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" Added cpu_svm_has_intercept to reduce duplication when checking the corresponding intercept bit outside of cpu_svm_check_intercept_param Signed-off-by: Lara Lazier --- target/i386/cpu.h | 3 + target/i386/tcg/sysemu/svm_helper.c | 105 +++++++++++++++------------- 2 files changed, 61 insertions(+), 47 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ac3abea97c..59b9231ee2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2149,9 +2149,12 @@ static inline void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, uint64_t param, uintptr_t retaddr) { /* no-op */ } +bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type) +{ return false; } #else void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, uint64_t param, uintptr_t retaddr); +bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type); #endif =20 /* apic.c */ diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/s= vm_helper.c index 9d671297cf..2f7606bebf 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -412,80 +412,91 @@ void helper_clgi(CPUX86State *env) env->hflags2 &=3D ~HF2_GIF_MASK; } =20 -void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, - uint64_t param, uintptr_t retaddr) +bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type) { - CPUState *cs =3D env_cpu(env); - - if (likely(!(env->hflags & HF_GUEST_MASK))) { - return; - } switch (type) { case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR0 + 8: if (env->intercept_cr_read & (1 << (type - SVM_EXIT_READ_CR0))) { - cpu_vmexit(env, type, param, retaddr); + return true; } break; case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR0 + 8: if (env->intercept_cr_write & (1 << (type - SVM_EXIT_WRITE_CR0))) { - cpu_vmexit(env, type, param, retaddr); + return true; } break; case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR0 + 7: if (env->intercept_dr_read & (1 << (type - SVM_EXIT_READ_DR0))) { - cpu_vmexit(env, type, param, retaddr); + return true; } break; case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR0 + 7: if (env->intercept_dr_write & (1 << (type - SVM_EXIT_WRITE_DR0))) { - cpu_vmexit(env, type, param, retaddr); + return true; } break; case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 31: if (env->intercept_exceptions & (1 << (type - SVM_EXIT_EXCP_BASE))= ) { - cpu_vmexit(env, type, param, retaddr); - } - break; - case SVM_EXIT_MSR: - if (env->intercept & (1ULL << (SVM_EXIT_MSR - SVM_EXIT_INTR))) { - /* FIXME: this should be read in at vmrun (faster this way?) */ - uint64_t addr =3D x86_ldq_phys(cs, env->vm_vmcb + - offsetof(struct vmcb, - control.msrpm_base_pa)); - uint32_t t0, t1; - - switch ((uint32_t)env->regs[R_ECX]) { - case 0 ... 0x1fff: - t0 =3D (env->regs[R_ECX] * 2) % 8; - t1 =3D (env->regs[R_ECX] * 2) / 8; - break; - case 0xc0000000 ... 0xc0001fff: - t0 =3D (8192 + env->regs[R_ECX] - 0xc0000000) * 2; - t1 =3D (t0 / 8); - t0 %=3D 8; - break; - case 0xc0010000 ... 0xc0011fff: - t0 =3D (16384 + env->regs[R_ECX] - 0xc0010000) * 2; - t1 =3D (t0 / 8); - t0 %=3D 8; - break; - default: - cpu_vmexit(env, type, param, retaddr); - t0 =3D 0; - t1 =3D 0; - break; - } - if (x86_ldub_phys(cs, addr + t1) & ((1 << param) << t0)) { - cpu_vmexit(env, type, param, retaddr); - } + return true; } break; default: if (env->intercept & (1ULL << (type - SVM_EXIT_INTR))) { - cpu_vmexit(env, type, param, retaddr); + return true; } break; } + return false; +} + +void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, + uint64_t param, uintptr_t retaddr) +{ + CPUState *cs =3D env_cpu(env); + + if (likely(!(env->hflags & HF_GUEST_MASK))) { + return; + } + + if (!cpu_svm_has_intercept(env, type)) { + return; + } + + if (type =3D=3D SVM_EXIT_MSR) { + /* FIXME: this should be read in at vmrun (faster this way?) */ + uint64_t addr =3D x86_ldq_phys(cs, env->vm_vmcb + + offsetof(struct vmcb, + control.msrpm_base_pa)); + uint32_t t0, t1; + + switch ((uint32_t)env->regs[R_ECX]) { + case 0 ... 0x1fff: + t0 =3D (env->regs[R_ECX] * 2) % 8; + t1 =3D (env->regs[R_ECX] * 2) / 8; + break; + case 0xc0000000 ... 0xc0001fff: + t0 =3D (8192 + env->regs[R_ECX] - 0xc0000000) * 2; + t1 =3D (t0 / 8); + t0 %=3D 8; + break; + case 0xc0010000 ... 0xc0011fff: + t0 =3D (16384 + env->regs[R_ECX] - 0xc0010000) * 2; + t1 =3D (t0 / 8); + t0 %=3D 8; + break; + default: + cpu_vmexit(env, type, param, retaddr); + t0 =3D 0; + t1 =3D 0; + break; + } + if (x86_ldub_phys(cs, addr + t1) & ((1 << param) << t0)) { + cpu_vmexit(env, type, param, retaddr); + } + return; + } + + cpu_vmexit(env, type, param, retaddr); } =20 void helper_svm_check_intercept(CPUX86State *env, uint32_t type) --=20 2.25.1