[PULL 00/25] target-arm queue

Only 0 patches received!
There is a newer version of this series
include/qemu/bitops.h             |  29 +++
include/qemu/int128.h             |  10 +
target/arm/translate-a32.h        |   2 +
target/arm/translate.h            |   9 +
target/arm/vec_internal.h         |   9 +
target/arm/mve.decode             |  20 ++
target/arm/t32.decode             |  15 +-
hw/arm/aspeed.c                   |  11 +-
hw/arm/npcm7xx_boards.c           | 107 ++++++++++-
hw/arm/virt.c                     |   2 +
hw/intc/arm_gicv3_cpuif.c         |   5 +-
hw/intc/armv7m_nvic.c             |   6 -
target/arm/m_helper.c             |  54 +++++-
target/arm/mte_helper.c           |   2 +-
target/arm/sve_helper.c           | 381 +++++++++++++-------------------------
target/arm/translate-a64.c        |  87 +++++----
target/arm/translate-m-nocp.c     |  16 +-
target/arm/translate-mve.c        |  29 +++
target/arm/translate-vfp.c        |  65 +++++--
target/arm/translate.c            | 300 ++++++++++++++++++++++++++++--
target/arm/vec_helper.c           | 116 +++++++++++-
target/arm/vfp_helper.c           |   3 +-
tests/tcg/aarch64/mte-7.c         |  31 ++++
hw/arm/Kconfig                    |   2 +
target/arm/meson.build            |   2 +
tests/tcg/aarch64/Makefile.target |   2 +-
26 files changed, 967 insertions(+), 348 deletions(-)
create mode 100644 target/arm/mve.decode
create mode 100644 target/arm/translate-mve.c
create mode 100644 tests/tcg/aarch64/mte-7.c
[PULL 00/25] target-arm queue
Posted by Peter Maydell 2 years, 9 months ago
v2: dropped the hw/acpi/ghes-stub.c changes, which produce a
weird Meson error ("Tried to extract unknown source ghes-stub.c")
which didn't happen on my local builds; I'll investigate later...

-- PMM

The following changes since commit 1ea06abceec61b6f3ab33dadb0510b6e09fb61e2:

  Merge remote-tracking branch 'remotes/berrange-gitlab/tags/misc-fixes-pull-request' into staging (2021-06-14 15:59:13 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210616

for you to fetch changes up to 703235a303d6862a7e3f5c6aa9eff7471cb138b2:

  include/qemu/int128.h: Add function to create Int128 from int64_t (2021-06-16 14:33:52 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
 * handle some UNALLOCATED decode cases correctly rather
   than asserting
 * hw: virt: consider hw_compat_6_0
 * hw/arm: add quanta-gbs-bmc machine
 * hw/intc/armv7m_nvic: Remove stale comment
 * target/arm: Fix mte page crossing test
 * hw/arm: quanta-q71l add pca954x muxes
 * target/arm: First few parts of MVE support

----------------------------------------------------------------
Heinrich Schuchardt (1):
      hw: virt: consider hw_compat_6_0

Jean-Philippe Brucker (1):
      hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes

Patrick Venture (5):
      hw/arm: add quanta-gbs-bmc machine
      hw/arm: quanta-gbs-bmc add i2c comments
      hw/arm: gsj add i2c comments
      hw/arm: gsj add pca9548
      hw/arm: quanta-q71l add pca954x muxes

Peter Maydell (14):
      hw/intc/armv7m_nvic: Remove stale comment
      target/arm: Provide and use H8 and H1_8 macros
      target/arm: Enable FPSCR.QC bit for MVE
      target/arm: Handle VPR semantics in existing code
      target/arm: Add handling for PSR.ECI/ICI
      target/arm: Let vfp_access_check() handle late NOCP checks
      target/arm: Implement MVE LCTP
      target/arm: Implement MVE WLSTP insn
      target/arm: Implement MVE DLSTP
      target/arm: Implement MVE LETP insn
      target/arm: Add framework for MVE decode
      target/arm: Move expand_pred_b() data to vec_helper.c
      bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
      include/qemu/int128.h: Add function to create Int128 from int64_t

Richard Henderson (4):
      target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16
      target/arm: Remove fprintf from disas_simd_mod_imm
      target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16
      target/arm: Fix mte page crossing test

 include/qemu/bitops.h             |  29 +++
 include/qemu/int128.h             |  10 +
 target/arm/translate-a32.h        |   2 +
 target/arm/translate.h            |   9 +
 target/arm/vec_internal.h         |   9 +
 target/arm/mve.decode             |  20 ++
 target/arm/t32.decode             |  15 +-
 hw/arm/aspeed.c                   |  11 +-
 hw/arm/npcm7xx_boards.c           | 107 ++++++++++-
 hw/arm/virt.c                     |   2 +
 hw/intc/arm_gicv3_cpuif.c         |   5 +-
 hw/intc/armv7m_nvic.c             |   6 -
 target/arm/m_helper.c             |  54 +++++-
 target/arm/mte_helper.c           |   2 +-
 target/arm/sve_helper.c           | 381 +++++++++++++-------------------------
 target/arm/translate-a64.c        |  87 +++++----
 target/arm/translate-m-nocp.c     |  16 +-
 target/arm/translate-mve.c        |  29 +++
 target/arm/translate-vfp.c        |  65 +++++--
 target/arm/translate.c            | 300 ++++++++++++++++++++++++++++--
 target/arm/vec_helper.c           | 116 +++++++++++-
 target/arm/vfp_helper.c           |   3 +-
 tests/tcg/aarch64/mte-7.c         |  31 ++++
 hw/arm/Kconfig                    |   2 +
 target/arm/meson.build            |   2 +
 tests/tcg/aarch64/Makefile.target |   2 +-
 26 files changed, 967 insertions(+), 348 deletions(-)
 create mode 100644 target/arm/mve.decode
 create mode 100644 target/arm/translate-mve.c
 create mode 100644 tests/tcg/aarch64/mte-7.c

Re: [PULL 00/25] target-arm queue
Posted by Peter Maydell 2 years, 9 months ago
On Wed, 16 Jun 2021 at 14:36, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> v2: dropped the hw/acpi/ghes-stub.c changes, which produce a
> weird Meson error ("Tried to extract unknown source ghes-stub.c")
> which didn't happen on my local builds; I'll investigate later...
>
> -- PMM
>
> The following changes since commit 1ea06abceec61b6f3ab33dadb0510b6e09fb61e2:
>
>   Merge remote-tracking branch 'remotes/berrange-gitlab/tags/misc-fixes-pull-request' into staging (2021-06-14 15:59:13 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210616
>
> for you to fetch changes up to 703235a303d6862a7e3f5c6aa9eff7471cb138b2:
>
>   include/qemu/int128.h: Add function to create Int128 from int64_t (2021-06-16 14:33:52 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
>  * handle some UNALLOCATED decode cases correctly rather
>    than asserting
>  * hw: virt: consider hw_compat_6_0
>  * hw/arm: add quanta-gbs-bmc machine
>  * hw/intc/armv7m_nvic: Remove stale comment
>  * target/arm: Fix mte page crossing test
>  * hw/arm: quanta-q71l add pca954x muxes
>  * target/arm: First few parts of MVE support
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.

-- PMM