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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a1sm6961970wra.63.2021.06.17.05.16.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jun 2021 05:17:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gXtKXcT35dV5WA49iFwUTffxPZHOQ0cnpW8MEYlDQGY=; b=NkWLfVAX7Vt2bF9SWGDhFt0Jd49dhalE8wmV4o30U6gjkWztp2LX7KuheHqvunCSkl 7syzkdJsshyiIqnQUYBr0GlycUcJFpvIxepp2DFrbPJ1Q6rIZtWL8mDUPVxXzJZRbAD9 mWEPl5YWbNuTFjobI1GbDyKZn7YUrOi9yFOPgdrusHO1bsRmBxaon9Fq++FNhrXb/ayj /rTPYnm2OxWFCZsUE/r8hFmPVULoIi8XyLJM9aMvLN763nneZzg9F0g4HtvdPJXvgkm2 3E9uipwtuwZMQspIjfGOJHW6meNCqS95eNzq1jSIIAjFLH49RpnhGnK7d8Lx1CaCv1OO 2s6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gXtKXcT35dV5WA49iFwUTffxPZHOQ0cnpW8MEYlDQGY=; b=RQT0FVNazljuidUTsyTf4bmvfTuMJ1oYqwyK+AtaaJcXk20wTp9ary3effTM7YyXjC 1pWtAMIOWxyM31vw0jGLh/qrGlI+qiVb2LeR9rs8rs/CbcKC6J+AVqqY+a6K8Qag4cDF msilO03c5h/lgXzASOR1QclHxF8ln3gUbK+redB33XBuKDrmPkggEq+DFUU3pByMsniR ynLrejzfgUil5UXiQeKmhw8Cv9BqrE5hgBjFLu7jxfKGZKZ1pFF89B1u25ByWeSrudkA IB3fW9yYxAwCniK/W8uJT1XXqU2NV1+RrG69o/dqsdL6Hf7SUways6wX/tVzbdVIEc7L ZXTw== X-Gm-Message-State: AOAM530Z98yblzD+t80Oh8+st64vkTphW7BmRCoAfi53+QwpTNGuvgoX 36i+VK0oK0r2VkDyfGP2BVXF5A== X-Google-Smtp-Source: ABdhPJzbDac+jNFhko/sQ0sqiduesgI6QpoVG1jEYaU5pbq1c1n72gStVgkoklezQCUbZFZmeLEAhw== X-Received: by 2002:a05:600c:3652:: with SMTP id y18mr4696974wmq.177.1623932220494; Thu, 17 Jun 2021 05:17:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 38/44] target/arm: Implement MVE VQDMULL (vector) Date: Thu, 17 Jun 2021 13:16:22 +0100 Message-Id: <20210617121628.20116-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210617121628.20116-1-peter.maydell@linaro.org> References: <20210617121628.20116-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the vector form of the MVE VQDMULL insn. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 5 +++++ target/arm/mve.decode | 5 +++++ target/arm/mve_helper.c | 30 ++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 61f8082e0e3..34a46ed38ee 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -233,6 +233,11 @@ DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxb, TCG_CALL_NO_WG, vo= id, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, p= tr) DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, p= tr) =20 +DEF_HELPER_FLAGS_4(mve_vqdmullbh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqdmullbw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqdmullth, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqdmulltw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index fa4fb1b2038..3a2a7e75a3a 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -39,6 +39,8 @@ @1op_nosz .... .... .... .... .... .... .... .... &1op qd=3D%qd qm=3D%qm s= ize=3D0 @2op .... .... .. size:2 .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn @2op_nosz .... .... .... .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn size=3D0 +@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn \ + size=3D%size_28 =20 # The _rev suffix indicates that Vn and Vm are reversed. This is # the case for shifts. In the Arm ARM these insns are documented @@ -152,6 +154,9 @@ VQDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 = . 0 ... 0 @2op VQRDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op VQRDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op =20 +VQDMULLB 111 . 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 1 @2op_sz28 +VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 1 @2op_sz28 + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 8db03003ce1..11eb99894bc 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -914,6 +914,36 @@ DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4= , int32_t, \ DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ do_qdmullw, SATMASK32) =20 +/* + * Long saturating ops + */ +#define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ + void *vm) \ + { \ + LTYPE *d =3D vd; \ + TYPE *n =3D vn, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned le; \ + bool qc =3D false; \ + for (le =3D 0; le < 16 / LESIZE; le++, mask >>=3D LESIZE) { = \ + bool sat =3D false; \ + LTYPE op1 =3D n[H##ESIZE(le * 2 + TOP)]; \ + LTYPE op2 =3D m[H##ESIZE(le * 2 + TOP)]; \ + mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ + qc |=3D sat && (mask & SATMASK); \ + } \ + if (qc) { \ + env->vfp.qc[0] =3D qc; \ + } \ + mve_advance_vpt(env); \ + } + +DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) +DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) +DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) +DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) + static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) { m &=3D 0xff; diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 27b3e378ac7..05789a19812 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -419,6 +419,36 @@ DO_2OP(VQDMLSDHX, vqdmlsdhx) DO_2OP(VQRDMLSDH, vqrdmlsdh) DO_2OP(VQRDMLSDHX, vqrdmlsdhx) =20 +static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) +{ + static MVEGenTwoOpFn * const fns[] =3D { + NULL, + gen_helper_mve_vqdmullbh, + gen_helper_mve_vqdmullbw, + NULL, + }; + if (a->size =3D=3D MO_32 && (a->qd =3D=3D a->qm || a->qd =3D=3D a->qn)= ) { + /* UNPREDICTABLE; we choose to undef */ + return false; + } + return do_2op(s, a, fns[a->size]); +} + +static bool trans_VQDMULLT(DisasContext *s, arg_2op *a) +{ + static MVEGenTwoOpFn * const fns[] =3D { + NULL, + gen_helper_mve_vqdmullth, + gen_helper_mve_vqdmulltw, + NULL, + }; + if (a->size =3D=3D MO_32 && (a->qd =3D=3D a->qm || a->qd =3D=3D a->qn)= ) { + /* UNPREDICTABLE; we choose to undef */ + return false; + } + return do_2op(s, a, fns[a->size]); +} + static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) { --=20 2.20.1