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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mrolnik@gmail.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/avr/translate.c | 238 +++++++++++++++++++++++------------------ 1 file changed, 132 insertions(+), 106 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 66e9882422..72117bf3b9 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2897,113 +2897,135 @@ static bool canonicalize_skip(DisasContext *ctx) return true; } =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) +static void gen_breakpoint(DisasContext *ctx) { + canonicalize_skip(ctx); + tcg_gen_movi_tl(cpu_pc, ctx->npc); + gen_helper_debug(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; +} + +static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUAVRState *env =3D cs->env_ptr; - DisasContext ctx1 =3D { - .base.tb =3D tb, - .base.is_jmp =3D DISAS_NEXT, - .base.pc_first =3D tb->pc, - .base.pc_next =3D tb->pc, - .base.singlestep_enabled =3D cs->singlestep_enabled, - .cs =3D cs, - .env =3D env, - .memidx =3D 0, - .skip_cond =3D TCG_COND_NEVER, - }; - DisasContext *ctx =3D &ctx1; - target_ulong pc_start =3D tb->pc / 2; - int num_insns =3D 0; + uint32_t tb_flags =3D ctx->base.tb->flags; =20 - if (tb->flags & TB_FLAGS_FULL_ACCESS) { - /* - * This flag is set by ST/LD instruction we will regenerate it ONLY - * with mem/cpu memory access instead of mem access - */ - max_insns =3D 1; - } - if (ctx->base.singlestep_enabled) { - max_insns =3D 1; - } + ctx->cs =3D cs, + ctx->env =3D env, + ctx->memidx =3D 0, + ctx->npc =3D ctx->base.pc_first / 2; =20 - gen_tb_start(tb); - - ctx->npc =3D pc_start; - if (tb->flags & TB_FLAGS_SKIP) { + ctx->skip_cond =3D TCG_COND_NEVER; + if (tb_flags & TB_FLAGS_SKIP) { ctx->skip_cond =3D TCG_COND_ALWAYS; ctx->skip_var0 =3D cpu_skip; } =20 - do { - TCGLabel *skip_label =3D NULL; - - /* translate current instruction */ - tcg_gen_insn_start(ctx->npc); - num_insns++; - + if (tb_flags & TB_FLAGS_FULL_ACCESS) { /* - * this is due to some strange GDB behavior - * let's assume main has address 0x100 - * b main - sets breakpoint at address 0x00000100 (code) - * b *0x100 - sets breakpoint at address 0x00800100 (data) + * This flag is set by ST/LD instruction we will regenerate it ONLY + * with mem/cpu memory access instead of mem access */ - if (unlikely(!ctx->base.singlestep_enabled && - (cpu_breakpoint_test(cs, OFFSET_CODE + ctx->npc * 2, BP_ANY) || - cpu_breakpoint_test(cs, OFFSET_DATA + ctx->npc * 2, BP_ANY)))= ) { - canonicalize_skip(ctx); - tcg_gen_movi_tl(cpu_pc, ctx->npc); - gen_helper_debug(cpu_env); - goto done_generating; - } + ctx->base.max_insns =3D 1; + } + if (ctx->base.singlestep_enabled) { + ctx->base.max_insns =3D 1; + } +} =20 - /* Conditionally skip the next instruction, if indicated. */ - if (ctx->skip_cond !=3D TCG_COND_NEVER) { - skip_label =3D gen_new_label(); - if (ctx->skip_var0 =3D=3D cpu_skip) { - /* - * Copy cpu_skip so that we may zero it before the branch. - * This ensures that cpu_skip is non-zero after the label - * if and only if the skipped insn itself sets a skip. - */ - ctx->free_skip_var0 =3D true; - ctx->skip_var0 =3D tcg_temp_new(); - tcg_gen_mov_tl(ctx->skip_var0, cpu_skip); - tcg_gen_movi_tl(cpu_skip, 0); - } - if (ctx->skip_var1 =3D=3D NULL) { - tcg_gen_brcondi_tl(ctx->skip_cond, ctx->skip_var0, - 0, skip_label); - } else { - tcg_gen_brcond_tl(ctx->skip_cond, ctx->skip_var0, - ctx->skip_var1, skip_label); - ctx->skip_var1 =3D NULL; - } - if (ctx->free_skip_var0) { - tcg_temp_free(ctx->skip_var0); - ctx->free_skip_var0 =3D false; - } - ctx->skip_cond =3D TCG_COND_NEVER; - ctx->skip_var0 =3D NULL; - } +static void avr_tr_tb_start(DisasContextBase *db, CPUState *cs) +{ +} =20 - translate(ctx); +static void avr_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - if (skip_label) { - canonicalize_skip(ctx); - gen_set_label(skip_label); - if (ctx->base.is_jmp =3D=3D DISAS_NORETURN) { - ctx->base.is_jmp =3D DISAS_CHAIN; - } - } - } while (ctx->base.is_jmp =3D=3D DISAS_NEXT - && num_insns < max_insns - && (ctx->npc - pc_start) * 2 < TARGET_PAGE_SIZE - 4 - && !tcg_op_buf_full()); + tcg_gen_insn_start(ctx->npc); +} =20 - if (tb->cflags & CF_LAST_IO) { - gen_io_end(); +static bool avr_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + gen_breakpoint(ctx); + return true; +} + +static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + TCGLabel *skip_label =3D NULL; + + /* + * This is due to some strange GDB behavior + * Let's assume main has address 0x100: + * b main - sets breakpoint at address 0x00000100 (code) + * b *0x100 - sets breakpoint at address 0x00800100 (data) + * + * The translator driver has already taken care of the code pointer. + */ + if (!ctx->base.singlestep_enabled && + cpu_breakpoint_test(cs, OFFSET_DATA + ctx->base.pc_next, BP_ANY)) { + gen_breakpoint(ctx); + return; } =20 + /* Conditionally skip the next instruction, if indicated. */ + if (ctx->skip_cond !=3D TCG_COND_NEVER) { + skip_label =3D gen_new_label(); + if (ctx->skip_var0 =3D=3D cpu_skip) { + /* + * Copy cpu_skip so that we may zero it before the branch. + * This ensures that cpu_skip is non-zero after the label + * if and only if the skipped insn itself sets a skip. + */ + ctx->free_skip_var0 =3D true; + ctx->skip_var0 =3D tcg_temp_new(); + tcg_gen_mov_tl(ctx->skip_var0, cpu_skip); + tcg_gen_movi_tl(cpu_skip, 0); + } + if (ctx->skip_var1 =3D=3D NULL) { + tcg_gen_brcondi_tl(ctx->skip_cond, ctx->skip_var0, 0, skip_lab= el); + } else { + tcg_gen_brcond_tl(ctx->skip_cond, ctx->skip_var0, + ctx->skip_var1, skip_label); + ctx->skip_var1 =3D NULL; + } + if (ctx->free_skip_var0) { + tcg_temp_free(ctx->skip_var0); + ctx->free_skip_var0 =3D false; + } + ctx->skip_cond =3D TCG_COND_NEVER; + ctx->skip_var0 =3D NULL; + } + + translate(ctx); + + ctx->base.pc_next =3D ctx->npc * 2; + + if (skip_label) { + canonicalize_skip(ctx); + gen_set_label(skip_label); + if (ctx->base.is_jmp =3D=3D DISAS_NORETURN) { + ctx->base.is_jmp =3D DISAS_CHAIN; + } + } + + if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { + target_ulong page_first =3D ctx->base.pc_first & TARGET_PAGE_MASK; + + if ((ctx->base.pc_next - page_first) >=3D TARGET_PAGE_SIZE - 4) { + ctx->base.is_jmp =3D DISAS_TOO_MANY; + } + } +} + +static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); bool nonconst_skip =3D canonicalize_skip(ctx); =20 switch (ctx->base.is_jmp) { @@ -3036,24 +3058,28 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) default: g_assert_not_reached(); } +} =20 -done_generating: - gen_tb_end(tb, num_insns); +static void avr_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); +} =20 - tb->size =3D (ctx->npc - pc_start) * 2; - tb->icount =3D num_insns; +static const TranslatorOps avr_tr_ops =3D { + .init_disas_context =3D avr_tr_init_disas_context, + .tb_start =3D avr_tr_tb_start, + .insn_start =3D avr_tr_insn_start, + .breakpoint_check =3D avr_tr_breakpoint_check, + .translate_insn =3D avr_tr_translate_insn, + .tb_stop =3D avr_tr_tb_stop, + .disas_log =3D avr_tr_disas_log, +}; =20 -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(tb->pc)) { - FILE *fd; - fd =3D qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(tb->pc)); - log_target_disas(cs, tb->pc, tb->size); - qemu_log("\n"); - qemu_log_unlock(fd); - } -#endif +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) +{ + DisasContext dc; + translator_loop(&avr_tr_ops, &dc.base, cs, tb, max_insns); } =20 void restore_state_to_opc(CPUAVRState *env, TranslationBlock *tb, --=20 2.25.1