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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mrolnik@gmail.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Migrate the bstate, tb and singlestep_enabled fields from DisasContext into the base. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/avr/translate.c | 58 +++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 850c5941d9..20c5062730 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -80,7 +80,7 @@ typedef struct DisasContext DisasContext; =20 /* This is the state at translation time. */ struct DisasContext { - TranslationBlock *tb; + DisasContextBase base; =20 CPUAVRState *env; CPUState *cs; @@ -90,8 +90,6 @@ struct DisasContext { =20 /* Routine used to access memory */ int memidx; - int bstate; - int singlestep; =20 /* * some AVR instructions can make the following instruction to be skip= ped @@ -191,7 +189,7 @@ static bool avr_have_feature(DisasContext *ctx, int fea= ture) { if (!avr_feature(ctx->env, feature)) { gen_helper_unsupported(cpu_env); - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; return false; } return true; @@ -1011,13 +1009,13 @@ static void gen_jmp_ez(DisasContext *ctx) { tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8); tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind); - ctx->bstate =3D DISAS_LOOKUP; + ctx->base.is_jmp =3D DISAS_LOOKUP; } =20 static void gen_jmp_z(DisasContext *ctx) { tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8); - ctx->bstate =3D DISAS_LOOKUP; + ctx->base.is_jmp =3D DISAS_LOOKUP; } =20 static void gen_push_ret(DisasContext *ctx, int ret) @@ -1083,9 +1081,9 @@ static void gen_pop_ret(DisasContext *ctx, TCGv ret) =20 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) { - TranslationBlock *tb =3D ctx->tb; + const TranslationBlock *tb =3D ctx->base.tb; =20 - if (ctx->singlestep =3D=3D 0) { + if (!ctx->base.singlestep_enabled) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(tb, n); @@ -1094,7 +1092,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) gen_helper_debug(cpu_env); tcg_gen_exit_tb(NULL, 0); } - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 /* @@ -1254,7 +1252,7 @@ static bool trans_RET(DisasContext *ctx, arg_RET *a) { gen_pop_ret(ctx, cpu_pc); =20 - ctx->bstate =3D DISAS_LOOKUP; + ctx->base.is_jmp =3D DISAS_LOOKUP; return true; } =20 @@ -1272,7 +1270,7 @@ static bool trans_RETI(DisasContext *ctx, arg_RETI *a) tcg_gen_movi_tl(cpu_If, 1); =20 /* Need to return to main loop to re-evaluate interrupts. */ - ctx->bstate =3D DISAS_EXIT; + ctx->base.is_jmp =3D DISAS_EXIT; return true; } =20 @@ -1484,7 +1482,7 @@ static bool trans_BRBC(DisasContext *ctx, arg_BRBC *a) gen_goto_tb(ctx, 0, ctx->npc + a->imm); gen_set_label(not_taken); =20 - ctx->bstate =3D DISAS_CHAIN; + ctx->base.is_jmp =3D DISAS_CHAIN; return true; } =20 @@ -1533,7 +1531,7 @@ static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a) gen_goto_tb(ctx, 0, ctx->npc + a->imm); gen_set_label(not_taken); =20 - ctx->bstate =3D DISAS_CHAIN; + ctx->base.is_jmp =3D DISAS_CHAIN; return true; } =20 @@ -1610,7 +1608,7 @@ static TCGv gen_get_zaddr(void) */ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) { - if (ctx->tb->flags & TB_FLAGS_FULL_ACCESS) { + if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { gen_helper_fullwr(cpu_env, data, addr); } else { tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] =3D data = */ @@ -1619,7 +1617,7 @@ static void gen_data_store(DisasContext *ctx, TCGv da= ta, TCGv addr) =20 static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { - if (ctx->tb->flags & TB_FLAGS_FULL_ACCESS) { + if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { gen_helper_fullrd(data, cpu_env, addr); } else { tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data =3D mem[addr]= */ @@ -2793,7 +2791,7 @@ static bool trans_BREAK(DisasContext *ctx, arg_BREAK = *a) #ifdef BREAKPOINT_ON_BREAK tcg_gen_movi_tl(cpu_pc, ctx->npc - 1); gen_helper_debug(cpu_env); - ctx->bstate =3D DISAS_EXIT; + ctx->base.is_jmp =3D DISAS_EXIT; #else /* NOP */ #endif @@ -2819,7 +2817,7 @@ static bool trans_NOP(DisasContext *ctx, arg_NOP *a) static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a) { gen_helper_sleep(cpu_env); - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; return true; } =20 @@ -2850,7 +2848,7 @@ static void translate(DisasContext *ctx) =20 if (!decode_insn(ctx, opcode)) { gen_helper_unsupported(cpu_env); - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } } =20 @@ -2903,13 +2901,15 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) { CPUAVRState *env =3D cs->env_ptr; DisasContext ctx =3D { - .tb =3D tb, + .base.tb =3D tb, + .base.is_jmp =3D DISAS_NEXT, + .base.pc_first =3D tb->pc, + .base.pc_next =3D tb->pc, + .base.singlestep_enabled =3D cs->singlestep_enabled, .cs =3D cs, .env =3D env, .memidx =3D 0, - .bstate =3D DISAS_NEXT, .skip_cond =3D TCG_COND_NEVER, - .singlestep =3D cs->singlestep_enabled, }; target_ulong pc_start =3D tb->pc / 2; int num_insns =3D 0; @@ -2921,7 +2921,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) */ max_insns =3D 1; } - if (ctx.singlestep) { + if (ctx.base.singlestep_enabled) { max_insns =3D 1; } =20 @@ -2946,7 +2946,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) * b main - sets breakpoint at address 0x00000100 (code) * b *0x100 - sets breakpoint at address 0x00800100 (data) */ - if (unlikely(!ctx.singlestep && + if (unlikely(!ctx.base.singlestep_enabled && (cpu_breakpoint_test(cs, OFFSET_CODE + ctx.npc * 2, BP_ANY= ) || cpu_breakpoint_test(cs, OFFSET_DATA + ctx.npc * 2, BP_ANY= )))) { canonicalize_skip(&ctx); @@ -2989,11 +2989,11 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) if (skip_label) { canonicalize_skip(&ctx); gen_set_label(skip_label); - if (ctx.bstate =3D=3D DISAS_NORETURN) { - ctx.bstate =3D DISAS_CHAIN; + if (ctx.base.is_jmp =3D=3D DISAS_NORETURN) { + ctx.base.is_jmp =3D DISAS_CHAIN; } } - } while (ctx.bstate =3D=3D DISAS_NEXT + } while (ctx.base.is_jmp =3D=3D DISAS_NEXT && num_insns < max_insns && (ctx.npc - pc_start) * 2 < TARGET_PAGE_SIZE - 4 && !tcg_op_buf_full()); @@ -3004,7 +3004,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) =20 bool nonconst_skip =3D canonicalize_skip(&ctx); =20 - switch (ctx.bstate) { + switch (ctx.base.is_jmp) { case DISAS_NORETURN: assert(!nonconst_skip); break; @@ -3019,13 +3019,13 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) tcg_gen_movi_tl(cpu_pc, ctx.npc); /* fall through */ case DISAS_LOOKUP: - if (!ctx.singlestep) { + if (!ctx.base.singlestep_enabled) { tcg_gen_lookup_and_goto_ptr(); break; } /* fall through */ case DISAS_EXIT: - if (ctx.singlestep) { + if (ctx.base.singlestep_enabled) { gen_helper_debug(cpu_env); } else { tcg_gen_exit_tb(NULL, 0); --=20 2.25.1 From nobody Wed May 8 20:15:35 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1624226036; cv=none; d=zohomail.com; s=zohoarc; b=LmGhhiTXkOVY7cZtcPy2rrDIie7nNc25pD/nCRMJBJxcoT+/hAaMNMgjOaun7FDYTL3XJPL9xLyC9mCwL+OMGQOaGGRcyZmnbFc7n823tkbwlfJVXf5W09yVRw218FP73BASMd8Z8s5n7OuQfpaSzJlyjSdmkzlEk3v5JQteEF8= ARC-Message-Signature: i=1; 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Sun, 20 Jun 2021 14:50:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 2/3] target/avr: Change ctx to DisasContext* in gen_intermediate_code Date: Sun, 20 Jun 2021 14:50:21 -0700 Message-Id: <20210620215022.1510617-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210620215022.1510617-1-richard.henderson@linaro.org> References: <20210620215022.1510617-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mrolnik@gmail.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Prepare for receiving it as a pointer input. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/avr/translate.c | 84 +++++++++++++++++++++--------------------- 1 file changed, 43 insertions(+), 41 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 20c5062730..66e9882422 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -104,7 +104,7 @@ struct DisasContext { * used in the following manner (sketch) * * TCGLabel *skip_label =3D NULL; - * if (ctx.skip_cond !=3D TCG_COND_NEVER) { + * if (ctx->skip_cond !=3D TCG_COND_NEVER) { * skip_label =3D gen_new_label(); * tcg_gen_brcond_tl(skip_cond, skip_var0, skip_var1, skip_label); * } @@ -114,7 +114,7 @@ struct DisasContext { * free_skip_var0 =3D false; * } * - * translate(&ctx); + * translate(ctx); * * if (skip_label) { * gen_set_label(skip_label); @@ -2900,7 +2900,7 @@ static bool canonicalize_skip(DisasContext *ctx) void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUAVRState *env =3D cs->env_ptr; - DisasContext ctx =3D { + DisasContext ctx1 =3D { .base.tb =3D tb, .base.is_jmp =3D DISAS_NEXT, .base.pc_first =3D tb->pc, @@ -2911,6 +2911,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) .memidx =3D 0, .skip_cond =3D TCG_COND_NEVER, }; + DisasContext *ctx =3D &ctx1; target_ulong pc_start =3D tb->pc / 2; int num_insns =3D 0; =20 @@ -2921,23 +2922,23 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) */ max_insns =3D 1; } - if (ctx.base.singlestep_enabled) { + if (ctx->base.singlestep_enabled) { max_insns =3D 1; } =20 gen_tb_start(tb); =20 - ctx.npc =3D pc_start; + ctx->npc =3D pc_start; if (tb->flags & TB_FLAGS_SKIP) { - ctx.skip_cond =3D TCG_COND_ALWAYS; - ctx.skip_var0 =3D cpu_skip; + ctx->skip_cond =3D TCG_COND_ALWAYS; + ctx->skip_var0 =3D cpu_skip; } =20 do { TCGLabel *skip_label =3D NULL; =20 /* translate current instruction */ - tcg_gen_insn_start(ctx.npc); + tcg_gen_insn_start(ctx->npc); num_insns++; =20 /* @@ -2946,65 +2947,66 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) * b main - sets breakpoint at address 0x00000100 (code) * b *0x100 - sets breakpoint at address 0x00800100 (data) */ - if (unlikely(!ctx.base.singlestep_enabled && - (cpu_breakpoint_test(cs, OFFSET_CODE + ctx.npc * 2, BP_ANY= ) || - cpu_breakpoint_test(cs, OFFSET_DATA + ctx.npc * 2, BP_ANY= )))) { - canonicalize_skip(&ctx); - tcg_gen_movi_tl(cpu_pc, ctx.npc); + if (unlikely(!ctx->base.singlestep_enabled && + (cpu_breakpoint_test(cs, OFFSET_CODE + ctx->npc * 2, BP_ANY) || + cpu_breakpoint_test(cs, OFFSET_DATA + ctx->npc * 2, BP_ANY)))= ) { + canonicalize_skip(ctx); + tcg_gen_movi_tl(cpu_pc, ctx->npc); gen_helper_debug(cpu_env); goto done_generating; } =20 /* Conditionally skip the next instruction, if indicated. */ - if (ctx.skip_cond !=3D TCG_COND_NEVER) { + if (ctx->skip_cond !=3D TCG_COND_NEVER) { skip_label =3D gen_new_label(); - if (ctx.skip_var0 =3D=3D cpu_skip) { + if (ctx->skip_var0 =3D=3D cpu_skip) { /* * Copy cpu_skip so that we may zero it before the branch. * This ensures that cpu_skip is non-zero after the label * if and only if the skipped insn itself sets a skip. */ - ctx.free_skip_var0 =3D true; - ctx.skip_var0 =3D tcg_temp_new(); - tcg_gen_mov_tl(ctx.skip_var0, cpu_skip); + ctx->free_skip_var0 =3D true; + ctx->skip_var0 =3D tcg_temp_new(); + tcg_gen_mov_tl(ctx->skip_var0, cpu_skip); tcg_gen_movi_tl(cpu_skip, 0); } - if (ctx.skip_var1 =3D=3D NULL) { - tcg_gen_brcondi_tl(ctx.skip_cond, ctx.skip_var0, 0, skip_l= abel); + if (ctx->skip_var1 =3D=3D NULL) { + tcg_gen_brcondi_tl(ctx->skip_cond, ctx->skip_var0, + 0, skip_label); } else { - tcg_gen_brcond_tl(ctx.skip_cond, ctx.skip_var0, - ctx.skip_var1, skip_label); - ctx.skip_var1 =3D NULL; + tcg_gen_brcond_tl(ctx->skip_cond, ctx->skip_var0, + ctx->skip_var1, skip_label); + ctx->skip_var1 =3D NULL; } - if (ctx.free_skip_var0) { - tcg_temp_free(ctx.skip_var0); - ctx.free_skip_var0 =3D false; + if (ctx->free_skip_var0) { + tcg_temp_free(ctx->skip_var0); + ctx->free_skip_var0 =3D false; } - ctx.skip_cond =3D TCG_COND_NEVER; - ctx.skip_var0 =3D NULL; + ctx->skip_cond =3D TCG_COND_NEVER; + ctx->skip_var0 =3D NULL; } =20 - translate(&ctx); + translate(ctx); =20 if (skip_label) { - canonicalize_skip(&ctx); + canonicalize_skip(ctx); gen_set_label(skip_label); - if (ctx.base.is_jmp =3D=3D DISAS_NORETURN) { - ctx.base.is_jmp =3D DISAS_CHAIN; + if (ctx->base.is_jmp =3D=3D DISAS_NORETURN) { + ctx->base.is_jmp =3D DISAS_CHAIN; } } - } while (ctx.base.is_jmp =3D=3D DISAS_NEXT + } while (ctx->base.is_jmp =3D=3D DISAS_NEXT && num_insns < max_insns - && (ctx.npc - pc_start) * 2 < TARGET_PAGE_SIZE - 4 + && (ctx->npc - pc_start) * 2 < TARGET_PAGE_SIZE - 4 && !tcg_op_buf_full()); =20 if (tb->cflags & CF_LAST_IO) { gen_io_end(); } =20 - bool nonconst_skip =3D canonicalize_skip(&ctx); + bool nonconst_skip =3D canonicalize_skip(ctx); =20 - switch (ctx.base.is_jmp) { + switch (ctx->base.is_jmp) { case DISAS_NORETURN: assert(!nonconst_skip); break; @@ -3013,19 +3015,19 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) case DISAS_CHAIN: if (!nonconst_skip) { /* Note gen_goto_tb checks singlestep. */ - gen_goto_tb(&ctx, 1, ctx.npc); + gen_goto_tb(ctx, 1, ctx->npc); break; } - tcg_gen_movi_tl(cpu_pc, ctx.npc); + tcg_gen_movi_tl(cpu_pc, ctx->npc); /* fall through */ case DISAS_LOOKUP: - if (!ctx.base.singlestep_enabled) { + if (!ctx->base.singlestep_enabled) { tcg_gen_lookup_and_goto_ptr(); break; } /* fall through */ case DISAS_EXIT: - if (ctx.base.singlestep_enabled) { + if (ctx->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else { tcg_gen_exit_tb(NULL, 0); @@ -3038,7 +3040,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) done_generating: gen_tb_end(tb, num_insns); =20 - tb->size =3D (ctx.npc - pc_start) * 2; + tb->size =3D (ctx->npc - pc_start) * 2; tb->icount =3D num_insns; =20 #ifdef DEBUG_DISAS --=20 2.25.1 From nobody Wed May 8 20:15:35 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1624226100; cv=none; d=zohomail.com; s=zohoarc; b=GhgzTUJHTougp+DZdBMu7JYlWJjraiWlhFpILEMJh5x19dOng7bzB7SZni6WmRHN7dCTDZxjukhboKj28yxBwhwHVvSXqLgoK8JyyL9mv+MqZ0YCWMZ5x+WV8suAV3sEjtI5kUUahEhAb2P0gmF1NuXdZZPa/lric88sCfoqYEY= ARC-Message-Signature: i=1; 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Sun, 20 Jun 2021 14:50:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 3/3] target/avr: Convert to TranslatorOps Date: Sun, 20 Jun 2021 14:50:22 -0700 Message-Id: <20210620215022.1510617-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210620215022.1510617-1-richard.henderson@linaro.org> References: <20210620215022.1510617-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mrolnik@gmail.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Michael Rolnik Tested-by: Michael Rolnik --- target/avr/translate.c | 234 ++++++++++++++++++++++------------------- 1 file changed, 128 insertions(+), 106 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 66e9882422..c06ce45bc7 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2897,113 +2897,131 @@ static bool canonicalize_skip(DisasContext *ctx) return true; } =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) +static void gen_breakpoint(DisasContext *ctx) { + canonicalize_skip(ctx); + tcg_gen_movi_tl(cpu_pc, ctx->npc); + gen_helper_debug(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; +} + +static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUAVRState *env =3D cs->env_ptr; - DisasContext ctx1 =3D { - .base.tb =3D tb, - .base.is_jmp =3D DISAS_NEXT, - .base.pc_first =3D tb->pc, - .base.pc_next =3D tb->pc, - .base.singlestep_enabled =3D cs->singlestep_enabled, - .cs =3D cs, - .env =3D env, - .memidx =3D 0, - .skip_cond =3D TCG_COND_NEVER, - }; - DisasContext *ctx =3D &ctx1; - target_ulong pc_start =3D tb->pc / 2; - int num_insns =3D 0; + uint32_t tb_flags =3D ctx->base.tb->flags; =20 - if (tb->flags & TB_FLAGS_FULL_ACCESS) { - /* - * This flag is set by ST/LD instruction we will regenerate it ONLY - * with mem/cpu memory access instead of mem access - */ - max_insns =3D 1; - } - if (ctx->base.singlestep_enabled) { - max_insns =3D 1; - } + ctx->cs =3D cs; + ctx->env =3D env; + ctx->npc =3D ctx->base.pc_first / 2; =20 - gen_tb_start(tb); - - ctx->npc =3D pc_start; - if (tb->flags & TB_FLAGS_SKIP) { + ctx->skip_cond =3D TCG_COND_NEVER; + if (tb_flags & TB_FLAGS_SKIP) { ctx->skip_cond =3D TCG_COND_ALWAYS; ctx->skip_var0 =3D cpu_skip; } =20 - do { - TCGLabel *skip_label =3D NULL; - - /* translate current instruction */ - tcg_gen_insn_start(ctx->npc); - num_insns++; - + if (tb_flags & TB_FLAGS_FULL_ACCESS) { /* - * this is due to some strange GDB behavior - * let's assume main has address 0x100 - * b main - sets breakpoint at address 0x00000100 (code) - * b *0x100 - sets breakpoint at address 0x00800100 (data) + * This flag is set by ST/LD instruction we will regenerate it ONLY + * with mem/cpu memory access instead of mem access */ - if (unlikely(!ctx->base.singlestep_enabled && - (cpu_breakpoint_test(cs, OFFSET_CODE + ctx->npc * 2, BP_ANY) || - cpu_breakpoint_test(cs, OFFSET_DATA + ctx->npc * 2, BP_ANY)))= ) { - canonicalize_skip(ctx); - tcg_gen_movi_tl(cpu_pc, ctx->npc); - gen_helper_debug(cpu_env); - goto done_generating; - } + ctx->base.max_insns =3D 1; + } +} =20 - /* Conditionally skip the next instruction, if indicated. */ - if (ctx->skip_cond !=3D TCG_COND_NEVER) { - skip_label =3D gen_new_label(); - if (ctx->skip_var0 =3D=3D cpu_skip) { - /* - * Copy cpu_skip so that we may zero it before the branch. - * This ensures that cpu_skip is non-zero after the label - * if and only if the skipped insn itself sets a skip. - */ - ctx->free_skip_var0 =3D true; - ctx->skip_var0 =3D tcg_temp_new(); - tcg_gen_mov_tl(ctx->skip_var0, cpu_skip); - tcg_gen_movi_tl(cpu_skip, 0); - } - if (ctx->skip_var1 =3D=3D NULL) { - tcg_gen_brcondi_tl(ctx->skip_cond, ctx->skip_var0, - 0, skip_label); - } else { - tcg_gen_brcond_tl(ctx->skip_cond, ctx->skip_var0, - ctx->skip_var1, skip_label); - ctx->skip_var1 =3D NULL; - } - if (ctx->free_skip_var0) { - tcg_temp_free(ctx->skip_var0); - ctx->free_skip_var0 =3D false; - } - ctx->skip_cond =3D TCG_COND_NEVER; - ctx->skip_var0 =3D NULL; - } +static void avr_tr_tb_start(DisasContextBase *db, CPUState *cs) +{ +} =20 - translate(ctx); +static void avr_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - if (skip_label) { - canonicalize_skip(ctx); - gen_set_label(skip_label); - if (ctx->base.is_jmp =3D=3D DISAS_NORETURN) { - ctx->base.is_jmp =3D DISAS_CHAIN; - } - } - } while (ctx->base.is_jmp =3D=3D DISAS_NEXT - && num_insns < max_insns - && (ctx->npc - pc_start) * 2 < TARGET_PAGE_SIZE - 4 - && !tcg_op_buf_full()); + tcg_gen_insn_start(ctx->npc); +} =20 - if (tb->cflags & CF_LAST_IO) { - gen_io_end(); +static bool avr_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + gen_breakpoint(ctx); + return true; +} + +static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + TCGLabel *skip_label =3D NULL; + + /* + * This is due to some strange GDB behavior + * Let's assume main has address 0x100: + * b main - sets breakpoint at address 0x00000100 (code) + * b *0x100 - sets breakpoint at address 0x00800100 (data) + * + * The translator driver has already taken care of the code pointer. + */ + if (!ctx->base.singlestep_enabled && + cpu_breakpoint_test(cs, OFFSET_DATA + ctx->base.pc_next, BP_ANY)) { + gen_breakpoint(ctx); + return; } =20 + /* Conditionally skip the next instruction, if indicated. */ + if (ctx->skip_cond !=3D TCG_COND_NEVER) { + skip_label =3D gen_new_label(); + if (ctx->skip_var0 =3D=3D cpu_skip) { + /* + * Copy cpu_skip so that we may zero it before the branch. + * This ensures that cpu_skip is non-zero after the label + * if and only if the skipped insn itself sets a skip. + */ + ctx->free_skip_var0 =3D true; + ctx->skip_var0 =3D tcg_temp_new(); + tcg_gen_mov_tl(ctx->skip_var0, cpu_skip); + tcg_gen_movi_tl(cpu_skip, 0); + } + if (ctx->skip_var1 =3D=3D NULL) { + tcg_gen_brcondi_tl(ctx->skip_cond, ctx->skip_var0, 0, skip_lab= el); + } else { + tcg_gen_brcond_tl(ctx->skip_cond, ctx->skip_var0, + ctx->skip_var1, skip_label); + ctx->skip_var1 =3D NULL; + } + if (ctx->free_skip_var0) { + tcg_temp_free(ctx->skip_var0); + ctx->free_skip_var0 =3D false; + } + ctx->skip_cond =3D TCG_COND_NEVER; + ctx->skip_var0 =3D NULL; + } + + translate(ctx); + + ctx->base.pc_next =3D ctx->npc * 2; + + if (skip_label) { + canonicalize_skip(ctx); + gen_set_label(skip_label); + if (ctx->base.is_jmp =3D=3D DISAS_NORETURN) { + ctx->base.is_jmp =3D DISAS_CHAIN; + } + } + + if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { + target_ulong page_first =3D ctx->base.pc_first & TARGET_PAGE_MASK; + + if ((ctx->base.pc_next - page_first) >=3D TARGET_PAGE_SIZE - 4) { + ctx->base.is_jmp =3D DISAS_TOO_MANY; + } + } +} + +static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); bool nonconst_skip =3D canonicalize_skip(ctx); =20 switch (ctx->base.is_jmp) { @@ -3036,24 +3054,28 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) default: g_assert_not_reached(); } +} =20 -done_generating: - gen_tb_end(tb, num_insns); +static void avr_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); +} =20 - tb->size =3D (ctx->npc - pc_start) * 2; - tb->icount =3D num_insns; +static const TranslatorOps avr_tr_ops =3D { + .init_disas_context =3D avr_tr_init_disas_context, + .tb_start =3D avr_tr_tb_start, + .insn_start =3D avr_tr_insn_start, + .breakpoint_check =3D avr_tr_breakpoint_check, + .translate_insn =3D avr_tr_translate_insn, + .tb_stop =3D avr_tr_tb_stop, + .disas_log =3D avr_tr_disas_log, +}; =20 -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(tb->pc)) { - FILE *fd; - fd =3D qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(tb->pc)); - log_target_disas(cs, tb->pc, tb->size); - qemu_log("\n"); - qemu_log_unlock(fd); - } -#endif +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) +{ + DisasContext dc =3D { }; + translator_loop(&avr_tr_ops, &dc.base, cs, tb, max_insns); } =20 void restore_state_to_opc(CPUAVRState *env, TranslationBlock *tb, --=20 2.25.1