From nobody Sat May 4 18:24:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624280125348570.8331572191385; Mon, 21 Jun 2021 05:55:25 -0700 (PDT) Received: from localhost ([::1]:46234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJSW-0000hg-5r for importer2@patchew.org; Mon, 21 Jun 2021 08:55:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41632) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvJP2-00061S-I9; Mon, 21 Jun 2021 08:51:48 -0400 Received: from [201.28.113.2] (port=53676 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJP0-0004ci-J5; Mon, 21 Jun 2021 08:51:48 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 21 Jun 2021 09:51:39 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id 2AAD7800055; Mon, 21 Jun 2021 09:51:39 -0300 (-03) From: "Bruno Larsen (billionai)" To: qemu-devel@nongnu.org Subject: [PATCH v2 01/10] target/ppc: Remove PowerPCCPUClass.handle_mmu_fault Date: Mon, 21 Jun 2021 09:51:06 -0300 Message-Id: <20210621125115.67717-2-bruno.larsen@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> References: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> X-OriginalArrivalTime: 21 Jun 2021 12:51:39.0289 (UTC) FILETIME=[2D5F9890:01D7669C] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=bruno.larsen@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: 0 X-Spam_score: -0.1 X-Spam_bar: / X-Spam_report: (-0.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SUBJ_WIPE_DEBT=1.004 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: farosas@linux.ibm.com, Richard Henderson , luis.pires@eldorado.org.br, Greg Kurz , lucas.araujo@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Instead, use a switch on env->mmu_model. This avoids some replicated information in cpu setup. Signed-off-by: Richard Henderson Reviewed-by: Greg Kurz --- target/ppc/cpu-qom.h | 1 - target/ppc/cpu_init.c | 45 ----------------------------------------- target/ppc/mmu_helper.c | 24 ++++++++++++++++++---- 3 files changed, 20 insertions(+), 50 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 06b6571bc9..3b14d2f134 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -198,7 +198,6 @@ struct PowerPCCPUClass { int n_host_threads; void (*init_proc)(CPUPPCState *env); int (*check_pow)(CPUPPCState *env); - int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu= _idx); bool (*interrupts_big_endian)(PowerPCCPU *cpu); }; =20 diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index d0411e7302..3a8d8d3f07 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -4578,9 +4578,6 @@ POWERPC_FAMILY(601)(ObjectClass *oc, void *data) (1ull << MSR_IR) | (1ull << MSR_DR); pcc->mmu_model =3D POWERPC_MMU_601; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model =3D POWERPC_EXCP_601; pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_601; @@ -4623,9 +4620,6 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) (1ull << MSR_IR) | (1ull << MSR_DR); pcc->mmu_model =3D POWERPC_MMU_601; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_601; pcc->flags =3D POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_H= ID0_LE; @@ -4889,9 +4883,6 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model =3D POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model =3D POWERPC_EXCP_604; pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_604; @@ -4973,9 +4964,6 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model =3D POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model =3D POWERPC_EXCP_604; pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_604; @@ -5044,9 +5032,6 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model =3D POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model =3D POWERPC_EXCP_7x0; pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_750; @@ -5124,9 +5109,6 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model =3D POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model =3D POWERPC_EXCP_7x0; pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_750; @@ -5327,9 +5309,6 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model =3D POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model =3D POWERPC_EXCP_7x0; pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_750; @@ -5410,9 +5389,6 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model =3D POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model =3D POWERPC_EXCP_7x0; pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_750; @@ -5498,9 +5474,6 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model =3D POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model =3D POWERPC_EXCP_7x0; pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_750; @@ -5586,9 +5559,6 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model =3D POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model =3D POWERPC_EXCP_7x0; pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_750; @@ -5828,9 +5798,6 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model =3D POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model =3D POWERPC_EXCP_74xx; pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_7400; @@ -5914,9 +5881,6 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model =3D POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model =3D POWERPC_EXCP_74xx; pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_7400; @@ -6743,9 +6707,6 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model =3D POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model =3D POWERPC_EXCP_74xx; pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; pcc->bfd_mach =3D bfd_mach_ppc_7400; @@ -7505,7 +7466,6 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) (1ull << MSR_RI); pcc->mmu_model =3D POWERPC_MMU_64B; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; pcc->hash64_opts =3D &ppc_hash64_opts_basic; #endif pcc->excp_model =3D POWERPC_EXCP_970; @@ -7583,7 +7543,6 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) LPCR_RMI | LPCR_HDICE; pcc->mmu_model =3D POWERPC_MMU_2_03; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; pcc->hash64_opts =3D &ppc_hash64_opts_basic; pcc->lrg_decr_bits =3D 32; #endif @@ -7727,7 +7686,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->lpcr_pm =3D LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; pcc->mmu_model =3D POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; pcc->lrg_decr_bits =3D 32; #endif @@ -7904,7 +7862,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) LPCR_P8_PECE3 | LPCR_P8_PECE4; pcc->mmu_model =3D POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; pcc->lrg_decr_bits =3D 32; pcc->n_host_threads =3D 8; @@ -8120,7 +8077,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; pcc->mmu_model =3D POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc64_v3_handle_mmu_fault; /* segment page size remain the same */ pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; pcc->radix_page_info =3D &POWER9_radix_page_info; @@ -8332,7 +8288,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; pcc->mmu_model =3D POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc64_v3_handle_mmu_fault; /* segment page size remain the same */ pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; pcc->radix_page_info =3D &POWER10_radix_page_info; diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 1ecb36e85a..c4b1c93e47 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -2947,14 +2947,30 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int= size, bool probe, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cs); CPUPPCState *env =3D &cpu->env; int ret; =20 - if (pcc->handle_mmu_fault) { - ret =3D pcc->handle_mmu_fault(cpu, addr, access_type, mmu_idx); - } else { + switch (env->mmu_model) { +#if defined(TARGET_PPC64) + case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: + case POWERPC_MMU_2_06: + case POWERPC_MMU_2_07: + ret =3D ppc_hash64_handle_mmu_fault(cpu, addr, access_type, mmu_id= x); + break; + case POWERPC_MMU_3_00: + ret =3D ppc64_v3_handle_mmu_fault(cpu, addr, access_type, mmu_idx); + break; +#endif + + case POWERPC_MMU_32B: + case POWERPC_MMU_601: + ret =3D ppc_hash32_handle_mmu_fault(cpu, addr, access_type, mmu_id= x); + break; + + default: ret =3D cpu_ppc_handle_mmu_fault(env, addr, access_type, mmu_idx); + break; } if (unlikely(ret !=3D 0)) { if (probe) { --=20 2.17.1 From nobody Sat May 4 18:24:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624280216506200.98783702289757; Mon, 21 Jun 2021 05:56:56 -0700 (PDT) Received: from localhost ([::1]:49152 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJTy-0002fn-83 for importer2@patchew.org; Mon, 21 Jun 2021 08:56:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41864) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvJQ6-0007Yc-1e; Mon, 21 Jun 2021 08:52:54 -0400 Received: from [201.28.113.2] (port=47857 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJQ4-0004nA-6X; Mon, 21 Jun 2021 08:52:53 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 21 Jun 2021 09:51:39 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id 6EF48800055; Mon, 21 Jun 2021 09:51:39 -0300 (-03) From: "Bruno Larsen (billionai)" To: qemu-devel@nongnu.org Subject: [PATCH v2 02/10] target/ppc: Use MMUAccessType with *_handle_mmu_fault Date: Mon, 21 Jun 2021 09:51:07 -0300 Message-Id: <20210621125115.67717-3-bruno.larsen@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> References: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> X-OriginalArrivalTime: 21 Jun 2021 12:51:39.0586 (UTC) FILETIME=[2D8CEA20:01D7669C] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=bruno.larsen@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: farosas@linux.ibm.com, Richard Henderson , luis.pires@eldorado.org.br, Greg Kurz , lucas.araujo@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson These changes were waiting until we didn't need to match the function type of PowerPCCPUClass.handle_mmu_fault. Signed-off-by: Richard Henderson Reviewed-by: Greg Kurz --- target/ppc/mmu-hash32.c | 7 ++----- target/ppc/mmu-hash32.h | 4 ++-- target/ppc/mmu-hash64.c | 6 +----- target/ppc/mmu-hash64.h | 4 ++-- target/ppc/mmu-radix64.c | 7 ++----- target/ppc/mmu-radix64.h | 4 ++-- 6 files changed, 11 insertions(+), 21 deletions(-) diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 9f0a497657..8f19b43e47 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -415,8 +415,8 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc= _hash_pte32_t pte, return (rpn & ~mask) | (eaddr & mask); } =20 -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, - int mmu_idx) +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; @@ -425,11 +425,8 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr= eaddr, int rwx, ppc_hash_pte32_t pte; int prot; int need_prot; - MMUAccessType access_type; hwaddr raddr; =20 - assert((rwx =3D=3D 0) || (rwx =3D=3D 1) || (rwx =3D=3D 2)); - access_type =3D rwx; need_prot =3D prot_for_access_type(access_type); =20 /* 1. Handle real mode accesses */ diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h index 898021f0d8..30e35718a7 100644 --- a/target/ppc/mmu-hash32.h +++ b/target/ppc/mmu-hash32.h @@ -5,8 +5,8 @@ =20 hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash); hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw, - int mmu_idx); +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, + MMUAccessType access_type, int mmu_idx); =20 /* * Segment register definitions diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 708dffc31b..2febd369b1 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -874,7 +874,7 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *= slb) } =20 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - int rwx, int mmu_idx) + MMUAccessType access_type, int mmu_idx) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; @@ -884,13 +884,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr= eaddr, hwaddr ptex; ppc_hash_pte64_t pte; int exec_prot, pp_prot, amr_prot, prot; - MMUAccessType access_type; int need_prot; hwaddr raddr; =20 - assert((rwx =3D=3D 0) || (rwx =3D=3D 1) || (rwx =3D=3D 2)); - access_type =3D rwx; - /* * Note on LPCR usage: 970 uses HID4, but our special variant of * store_spr copies relevant fields into env->spr[SPR_LPCR]. diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 4b8b8e7950..3e8a8eec1f 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -8,8 +8,8 @@ void dump_slb(PowerPCCPU *cpu); int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, target_ulong esid, target_ulong vsid); hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); -int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw, - int mmu_idx); +int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, + MMUAccessType access_type, int mmu_idx); void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong pte_index, target_ulong pte0, target_ulong pte1); diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index b6d191c1d8..1c707d387d 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -555,19 +555,16 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr e= addr, return 0; } =20 -int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, - int mmu_idx) +int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; int page_size, prot; bool relocation; - MMUAccessType access_type; hwaddr raddr; =20 assert(!(msr_hv && cpu->vhyp)); - assert((rwx =3D=3D 0) || (rwx =3D=3D 1) || (rwx =3D=3D 2)); - access_type =3D rwx; =20 relocation =3D (access_type =3D=3D MMU_INST_FETCH ? msr_ir : msr_dr); /* HV or virtual hypervisor Real Mode Access */ diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h index f28c5794d0..94bd72cb38 100644 --- a/target/ppc/mmu-radix64.h +++ b/target/ppc/mmu-radix64.h @@ -44,8 +44,8 @@ =20 #ifdef TARGET_PPC64 =20 -int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, - int mmu_idx); +int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx); hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); =20 static inline int ppc_radix64_get_prot_eaa(uint64_t pte) --=20 2.17.1 From nobody Sat May 4 18:24:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624280277236604.410729298502; Mon, 21 Jun 2021 05:57:57 -0700 (PDT) Received: from localhost ([::1]:51008 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJUx-0003yb-Vn for importer2@patchew.org; Mon, 21 Jun 2021 08:57:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvJQ8-0007gG-VW; Mon, 21 Jun 2021 08:52:56 -0400 Received: from [201.28.113.2] (port=47857 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJQ7-0004nA-3A; Mon, 21 Jun 2021 08:52:56 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 21 Jun 2021 09:51:39 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id 97D9980005E; Mon, 21 Jun 2021 09:51:39 -0300 (-03) From: "Bruno Larsen (billionai)" To: qemu-devel@nongnu.org Subject: [PATCH v2 03/10] target/ppc: Push real-mode handling into ppc_radix64_xlate Date: Mon, 21 Jun 2021 09:51:08 -0300 Message-Id: <20210621125115.67717-4-bruno.larsen@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> References: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> X-OriginalArrivalTime: 21 Jun 2021 12:51:39.0742 (UTC) FILETIME=[2DA4B7E0:01D7669C] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=bruno.larsen@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: farosas@linux.ibm.com, Richard Henderson , luis.pires@eldorado.org.br, Greg Kurz , lucas.araujo@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This removes some incomplete duplication between ppc_radix64_handle_mmu_fault and ppc_radix64_get_phys_page_debug. The former was correct wrt SPR_HRMOR and the latter was not. Signed-off-by: Richard Henderson --- target/ppc/mmu-radix64.c | 77 ++++++++++++++++++---------------------- 1 file changed, 34 insertions(+), 43 deletions(-) diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 1c707d387d..dd5ae69052 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -465,7 +465,6 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU = *cpu, */ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, - bool relocation, hwaddr *raddr, int *psizep, int *protp, bool guest_visible) { @@ -474,6 +473,37 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr ea= ddr, ppc_v3_pate_t pate; int psize, prot; hwaddr g_raddr; + bool relocation; + + assert(!(msr_hv && cpu->vhyp)); + + relocation =3D (access_type =3D=3D MMU_INST_FETCH ? msr_ir : msr_dr); + + /* HV or virtual hypervisor Real Mode Access */ + if (!relocation && (msr_hv || cpu->vhyp)) { + /* In real mode top 4 effective addr bits (mostly) ignored */ + *raddr =3D eaddr & 0x0FFFFFFFFFFFFFFFULL; + + /* In HV mode, add HRMOR if top EA bit is clear */ + if (msr_hv || !env->has_hv_mode) { + if (!(eaddr >> 63)) { + *raddr |=3D env->spr[SPR_HRMOR]; + } + } + *protp =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *psizep =3D TARGET_PAGE_BITS; + return 0; + } + + /* + * Check UPRT (we avoid the check in real mode to deal with + * transitional states during kexec. + */ + if (guest_visible && !ppc64_use_proc_tbl(cpu)) { + qemu_log_mask(LOG_GUEST_ERROR, + "LPCR:UPRT not set in radix mode ! LPCR=3D" + TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); + } =20 /* Virtual Mode Access - get the fully qualified address */ if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pi= d)) { @@ -559,43 +589,11 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vad= dr eaddr, MMUAccessType access_type, int mmu_idx) { CPUState *cs =3D CPU(cpu); - CPUPPCState *env =3D &cpu->env; int page_size, prot; - bool relocation; hwaddr raddr; =20 - assert(!(msr_hv && cpu->vhyp)); - - relocation =3D (access_type =3D=3D MMU_INST_FETCH ? msr_ir : msr_dr); - /* HV or virtual hypervisor Real Mode Access */ - if (!relocation && (msr_hv || cpu->vhyp)) { - /* In real mode top 4 effective addr bits (mostly) ignored */ - raddr =3D eaddr & 0x0FFFFFFFFFFFFFFFULL; - - /* In HV mode, add HRMOR if top EA bit is clear */ - if (msr_hv || !env->has_hv_mode) { - if (!(eaddr >> 63)) { - raddr |=3D env->spr[SPR_HRMOR]; - } - } - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, - PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, - TARGET_PAGE_SIZE); - return 0; - } - - /* - * Check UPRT (we avoid the check in real mode to deal with - * transitional states during kexec. - */ - if (!ppc64_use_proc_tbl(cpu)) { - qemu_log_mask(LOG_GUEST_ERROR, - "LPCR:UPRT not set in radix mode ! LPCR=3D" - TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); - } - /* Translate eaddr to raddr (where raddr is addr qemu needs for access= ) */ - if (ppc_radix64_xlate(cpu, eaddr, access_type, relocation, &raddr, + if (ppc_radix64_xlate(cpu, eaddr, access_type, &raddr, &page_size, &prot, true)) { return 1; } @@ -607,18 +605,11 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vad= dr eaddr, =20 hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) { - CPUPPCState *env =3D &cpu->env; int psize, prot; hwaddr raddr; =20 - /* Handle Real Mode */ - if ((msr_dr =3D=3D 0) && (msr_hv || cpu->vhyp)) { - /* In real mode top 4 effective addr bits (mostly) ignored */ - return eaddr & 0x0FFFFFFFFFFFFFFFULL; - } - - if (ppc_radix64_xlate(cpu, eaddr, 0, msr_dr, &raddr, &psize, - &prot, false)) { + if (ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, + &psize, &prot, false)) { return -1; } =20 --=20 2.17.1 From nobody Sat May 4 18:24:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624280601061157.10642778260853; Mon, 21 Jun 2021 06:03:21 -0700 (PDT) Received: from localhost ([::1]:33698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJaB-00033Y-U8 for importer2@patchew.org; Mon, 21 Jun 2021 09:03:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvJQB-0007oj-LB; Mon, 21 Jun 2021 08:52:59 -0400 Received: from [201.28.113.2] (port=47857 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJQA-0004nA-11; Mon, 21 Jun 2021 08:52:59 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 21 Jun 2021 09:51:39 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id C0679800055; Mon, 21 Jun 2021 09:51:39 -0300 (-03) From: "Bruno Larsen (billionai)" To: qemu-devel@nongnu.org Subject: [PATCH v2 04/10] target/ppc: Use bool success for ppc_radix64_xlate Date: Mon, 21 Jun 2021 09:51:09 -0300 Message-Id: <20210621125115.67717-5-bruno.larsen@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> References: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> X-OriginalArrivalTime: 21 Jun 2021 12:51:39.0898 (UTC) FILETIME=[2DBC85A0:01D7669C] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=bruno.larsen@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: farosas@linux.ibm.com, Richard Henderson , luis.pires@eldorado.org.br, Greg Kurz , lucas.araujo@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Instead of returning non-zero for failure, return true for success. Signed-off-by: Richard Henderson --- target/ppc/mmu-radix64.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index dd5ae69052..2d5f0850c9 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -463,10 +463,10 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCP= U *cpu, * | =3D On | Process Scoped | Scoped | * +-------------+----------------+---------------+ */ -static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, - hwaddr *raddr, int *psizep, int *protp, - bool guest_visible) +static bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, + hwaddr *raddr, int *psizep, int *protp, + bool guest_visible) { CPUPPCState *env =3D &cpu->env; uint64_t lpid, pid; @@ -492,7 +492,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr ead= dr, } *protp =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; *psizep =3D TARGET_PAGE_BITS; - return 0; + return true; } =20 /* @@ -510,7 +510,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr ead= dr, if (guest_visible) { ppc_radix64_raise_segi(cpu, access_type, eaddr); } - return 1; + return false; } =20 /* Get Process Table */ @@ -523,13 +523,13 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr e= addr, if (guest_visible) { ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE); } - return 1; + return false; } if (!validate_pate(cpu, lpid, &pate)) { if (guest_visible) { ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_R_BADC= ONFIG); } - return 1; + return false; } } =20 @@ -549,7 +549,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr ead= dr, pate, &g_raddr, &prot, &psize, guest_visible); if (ret) { - return ret; + return false; } *psizep =3D MIN(*psizep, psize); *protp &=3D prot; @@ -573,7 +573,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr ead= dr, &prot, &psize, false, guest_visible); if (ret) { - return ret; + return false; } *psizep =3D MIN(*psizep, psize); *protp &=3D prot; @@ -582,7 +582,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr ead= dr, } } =20 - return 0; + return true; } =20 int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, @@ -593,8 +593,8 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr= eaddr, hwaddr raddr; =20 /* Translate eaddr to raddr (where raddr is addr qemu needs for access= ) */ - if (ppc_radix64_xlate(cpu, eaddr, access_type, &raddr, - &page_size, &prot, true)) { + if (!ppc_radix64_xlate(cpu, eaddr, access_type, &raddr, + &page_size, &prot, true)) { return 1; } =20 @@ -608,8 +608,8 @@ hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu,= target_ulong eaddr) int psize, prot; hwaddr raddr; =20 - if (ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, - &psize, &prot, false)) { + if (!ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, + &psize, &prot, false)) { return -1; } =20 --=20 2.17.1 From nobody Sat May 4 18:24:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624280401726386.20040614265383; Mon, 21 Jun 2021 06:00:01 -0700 (PDT) Received: from localhost ([::1]:57500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJWy-0008KE-9E for importer2@patchew.org; Mon, 21 Jun 2021 09:00:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvJQE-0007x1-J1; Mon, 21 Jun 2021 08:53:02 -0400 Received: from [201.28.113.2] (port=47857 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJQC-0004nA-Oe; Mon, 21 Jun 2021 08:53:02 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 21 Jun 2021 09:51:40 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id E94A580005E; Mon, 21 Jun 2021 09:51:39 -0300 (-03) From: "Bruno Larsen (billionai)" To: qemu-devel@nongnu.org Subject: [PATCH v2 05/10] target/ppc: Split out ppc_hash64_xlate Date: Mon, 21 Jun 2021 09:51:10 -0300 Message-Id: <20210621125115.67717-6-bruno.larsen@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> References: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> X-OriginalArrivalTime: 21 Jun 2021 12:51:40.0211 (UTC) FILETIME=[2DEC4830:01D7669C] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=bruno.larsen@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: farosas@linux.ibm.com, Richard Henderson , luis.pires@eldorado.org.br, Greg Kurz , lucas.araujo@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Mirror the interface of ppc_radix64_xlate, putting all of the logic for hash64 translation into a single function. Signed-off-by: Richard Henderson --- target/ppc/mmu-hash64.c | 125 +++++++++++++++++++--------------------- 1 file changed, 59 insertions(+), 66 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 2febd369b1..c6b167b4dc 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -873,8 +873,10 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t = *slb) return -1; } =20 -int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) +static bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; @@ -918,9 +920,11 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr= eaddr, slb =3D &vrma_slbe; if (build_vrma_slbe(cpu, slb) !=3D 0) { /* Invalid VRMA setup, machine check */ - cs->exception_index =3D POWERPC_EXCP_MCHECK; - env->error_code =3D 0; - return 1; + if (guest_visible) { + cs->exception_index =3D POWERPC_EXCP_MCHECK; + env->error_code =3D 0; + } + return false; } =20 goto skip_slb_search; @@ -929,6 +933,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, =20 /* Emulated old-style RMO mode, bounds check against RMLS */ if (raddr >=3D limit) { + if (!guest_visible) { + return false; + } switch (access_type) { case MMU_INST_FETCH: ppc_hash64_set_isi(cs, SRR1_PROTFAULT); @@ -943,15 +950,16 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, default: g_assert_not_reached(); } - return 1; + return false; } =20 raddr |=3D env->spr[SPR_RMOR]; } - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, - PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, - TARGET_PAGE_SIZE); - return 0; + + *raddrp =3D raddr; + *protp =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *psizep =3D TARGET_PAGE_BITS; + return true; } =20 /* 2. Translation is on, so look up the SLB */ @@ -964,6 +972,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, exit(1); } /* Segment still not found, generate the appropriate interrupt */ + if (!guest_visible) { + return false; + } switch (access_type) { case MMU_INST_FETCH: cs->exception_index =3D POWERPC_EXCP_ISEG; @@ -978,20 +989,25 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, default: g_assert_not_reached(); } - return 1; + return false; } =20 -skip_slb_search: + skip_slb_search: =20 /* 3. Check for segment level no-execute violation */ if (access_type =3D=3D MMU_INST_FETCH && (slb->vsid & SLB_VSID_N)) { - ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD); - return 1; + if (guest_visible) { + ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD); + } + return false; } =20 /* 4. Locate the PTE in the hash table */ ptex =3D ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift); if (ptex =3D=3D -1) { + if (!guest_visible) { + return false; + } switch (access_type) { case MMU_INST_FETCH: ppc_hash64_set_isi(cs, SRR1_NOPTE); @@ -1005,7 +1021,7 @@ skip_slb_search: default: g_assert_not_reached(); } - return 1; + return false; } qemu_log_mask(CPU_LOG_MMU, "found PTE at index %08" HWADDR_PRIx "\n", ptex); @@ -1021,6 +1037,9 @@ skip_slb_search: if (need_prot & ~prot) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); + if (!guest_visible) { + return false; + } if (access_type =3D=3D MMU_INST_FETCH) { int srr1 =3D 0; if (PAGE_EXEC & ~exec_prot) { @@ -1045,7 +1064,7 @@ skip_slb_search: } ppc_hash64_set_dsi(cs, eaddr, dsisr); } - return 1; + return false; } =20 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); @@ -1069,66 +1088,40 @@ skip_slb_search: =20 /* 7. Determine the real address from the PTE */ =20 - raddr =3D deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr); - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, 1ULL << apshift); - - return 0; + *raddrp =3D deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr); + *protp =3D prot; + *psizep =3D apshift; + return true; } =20 -hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) +int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx) { - CPUPPCState *env =3D &cpu->env; - ppc_slb_t vrma_slbe; - ppc_slb_t *slb; - hwaddr ptex, raddr; - ppc_hash_pte64_t pte; - unsigned apshift; + CPUState *cs =3D CPU(cpu); + int page_size, prot; + hwaddr raddr; =20 - /* Handle real mode */ - if (msr_dr =3D=3D 0) { - /* In real mode the top 4 effective address bits are ignored */ - raddr =3D addr & 0x0FFFFFFFFFFFFFFFULL; + if (!ppc_hash64_xlate(cpu, eaddr, access_type, &raddr, + &page_size, &prot, true)) { + return 1; + } =20 - if (cpu->vhyp) { - /* - * In virtual hypervisor mode, there's nothing to do: - * EA =3D=3D GPA =3D=3D qemu guest address - */ - return raddr; - } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { - /* In HV mode, add HRMOR if top EA bit is clear */ - return raddr | env->spr[SPR_HRMOR]; - } else if (ppc_hash64_use_vrma(env)) { - /* Emulated VRMA mode */ - slb =3D &vrma_slbe; - if (build_vrma_slbe(cpu, slb) !=3D 0) { - return -1; - } - } else { - target_ulong limit =3D rmls_limit(cpu); + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + prot, mmu_idx, 1UL << page_size); + return 0; +} =20 - /* Emulated old-style RMO mode, bounds check against RMLS */ - if (raddr >=3D limit) { - return -1; - } - return raddr | env->spr[SPR_RMOR]; - } - } else { - slb =3D slb_lookup(cpu, addr); - if (!slb) { - return -1; - } - } +hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) +{ + int psize, prot; + hwaddr raddr; =20 - ptex =3D ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift); - if (ptex =3D=3D -1) { + if (!ppc_hash64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, + &psize, &prot, false)) { return -1; } =20 - return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr) - & TARGET_PAGE_MASK; + return raddr & TARGET_PAGE_MASK; } =20 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, --=20 2.17.1 From nobody Sat May 4 18:24:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162428086887979.59957143873521; Mon, 21 Jun 2021 06:07:48 -0700 (PDT) Received: from localhost ([::1]:42472 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJeV-0000c9-Gv for importer2@patchew.org; Mon, 21 Jun 2021 09:07:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42014) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvJQH-00085v-Kn; Mon, 21 Jun 2021 08:53:05 -0400 Received: from [201.28.113.2] (port=47857 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJQF-0004nA-Ii; Mon, 21 Jun 2021 08:53:05 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 21 Jun 2021 09:51:40 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id 1FC3F800055; Mon, 21 Jun 2021 09:51:40 -0300 (-03) From: "Bruno Larsen (billionai)" To: qemu-devel@nongnu.org Subject: [PATCH v2 06/10] target/ppc: Split out ppc_hash32_xlate Date: Mon, 21 Jun 2021 09:51:11 -0300 Message-Id: <20210621125115.67717-7-bruno.larsen@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> References: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> X-OriginalArrivalTime: 21 Jun 2021 12:51:40.0398 (UTC) FILETIME=[2E08D0E0:01D7669C] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=bruno.larsen@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: farosas@linux.ibm.com, Richard Henderson , luis.pires@eldorado.org.br, Greg Kurz , lucas.araujo@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Mirror the interface of ppc_radix64_xlate, putting all of the logic for hash32 translation into a single entry point. Signed-off-by: Richard Henderson --- target/ppc/mmu-hash32.c | 224 ++++++++++++++++++++-------------------- 1 file changed, 113 insertions(+), 111 deletions(-) diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 8f19b43e47..ad22372c07 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -218,10 +218,11 @@ static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, = target_ulong ea, return -1; } =20 -static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, - target_ulong eaddr, - MMUAccessType access_type, - hwaddr *raddr, int *prot) +static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, + target_ulong eaddr, + MMUAccessType access_type, + hwaddr *raddr, int *prot, + bool guest_visible) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; @@ -238,17 +239,23 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, t= arget_ulong sr, */ *raddr =3D ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF); *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return 0; + return true; } =20 if (access_type =3D=3D MMU_INST_FETCH) { /* No code fetch is allowed in direct-store areas */ - cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x10000000; - return 1; + if (guest_visible) { + cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0x10000000; + } + return false; } =20 - switch (env->access_type) { + /* + * From ppc_cpu_get_phys_page_debug, env->access_type is not set. + * Assume ACCESS_INT for that case. + */ + switch (guest_visible ? env->access_type : ACCESS_INT) { case ACCESS_INT: /* Integer load/store : only access allowed */ break; @@ -257,7 +264,7 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, tar= get_ulong sr, cs->exception_index =3D POWERPC_EXCP_ALIGN; env->error_code =3D POWERPC_EXCP_ALIGN_FP; env->spr[SPR_DAR] =3D eaddr; - return 1; + return false; case ACCESS_RES: /* lwarx, ldarx or srwcx. */ env->error_code =3D 0; @@ -267,7 +274,7 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, tar= get_ulong sr, } else { env->spr[SPR_DSISR] =3D 0x04000000; } - return 1; + return false; case ACCESS_CACHE: /* * dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi @@ -276,7 +283,7 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, tar= get_ulong sr, * no-op, it's quite easy :-) */ *raddr =3D eaddr; - return 0; + return true; case ACCESS_EXT: /* eciwx or ecowx */ cs->exception_index =3D POWERPC_EXCP_DSI; @@ -287,16 +294,18 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, t= arget_ulong sr, } else { env->spr[SPR_DSISR] =3D 0x04100000; } - return 1; + return false; default: - cpu_abort(cs, "ERROR: instruction should not need " - "address translation\n"); + cpu_abort(cs, "ERROR: insn should not need address translation\n"); } - if ((access_type =3D=3D MMU_DATA_STORE || key !=3D 1) && - (access_type =3D=3D MMU_DATA_LOAD || key !=3D 0)) { + + *prot =3D key ? PAGE_READ | PAGE_WRITE : PAGE_READ; + if (*prot & prot_for_access_type(access_type)) { *raddr =3D eaddr; - return 0; - } else { + return true; + } + + if (guest_visible) { cs->exception_index =3D POWERPC_EXCP_DSI; env->error_code =3D 0; env->spr[SPR_DAR] =3D eaddr; @@ -305,8 +314,8 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, tar= get_ulong sr, } else { env->spr[SPR_DSISR] =3D 0x08000000; } - return 1; } + return false; } =20 hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash) @@ -415,8 +424,10 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, pp= c_hash_pte32_t pte, return (rpn & ~mask) | (eaddr & mask); } =20 -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) +static bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; @@ -427,43 +438,43 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, int need_prot; hwaddr raddr; =20 - need_prot =3D prot_for_access_type(access_type); + /* There are no hash32 large pages. */ + *psizep =3D TARGET_PAGE_BITS; =20 /* 1. Handle real mode accesses */ if (access_type =3D=3D MMU_INST_FETCH ? !msr_ir : !msr_dr) { /* Translation is off */ - raddr =3D eaddr; - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, - PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, - TARGET_PAGE_SIZE); - return 0; + *raddrp =3D eaddr; + *protp =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return true; } =20 + need_prot =3D prot_for_access_type(access_type); + /* 2. Check Block Address Translation entries (BATs) */ if (env->nb_BATs !=3D 0) { - raddr =3D ppc_hash32_bat_lookup(cpu, eaddr, access_type, &prot); + raddr =3D ppc_hash32_bat_lookup(cpu, eaddr, access_type, protp); if (raddr !=3D -1) { - if (need_prot & ~prot) { - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x08000000; - } else { - cs->exception_index =3D POWERPC_EXCP_DSI; - env->error_code =3D 0; - env->spr[SPR_DAR] =3D eaddr; - if (access_type =3D=3D MMU_DATA_STORE) { - env->spr[SPR_DSISR] =3D 0x0a000000; + if (need_prot & ~*protp) { + if (guest_visible) { + if (access_type =3D=3D MMU_INST_FETCH) { + cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0x08000000; } else { - env->spr[SPR_DSISR] =3D 0x08000000; + cs->exception_index =3D POWERPC_EXCP_DSI; + env->error_code =3D 0; + env->spr[SPR_DAR] =3D eaddr; + if (access_type =3D=3D MMU_DATA_STORE) { + env->spr[SPR_DSISR] =3D 0x0a000000; + } else { + env->spr[SPR_DSISR] =3D 0x08000000; + } } } - return 1; + return false; } - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, - raddr & TARGET_PAGE_MASK, prot, mmu_idx, - TARGET_PAGE_SIZE); - return 0; + *raddrp =3D raddr; + return true; } } =20 @@ -472,42 +483,38 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, =20 /* 4. Handle direct store segments */ if (sr & SR32_T) { - if (ppc_hash32_direct_store(cpu, sr, eaddr, access_type, - &raddr, &prot) =3D=3D 0) { - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, - raddr & TARGET_PAGE_MASK, prot, mmu_idx, - TARGET_PAGE_SIZE); - return 0; - } else { - return 1; - } + return ppc_hash32_direct_store(cpu, sr, eaddr, access_type, + raddrp, protp, guest_visible); } =20 /* 5. Check for segment level no-execute violation */ if (access_type =3D=3D MMU_INST_FETCH && (sr & SR32_NX)) { - cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x10000000; - return 1; + if (guest_visible) { + cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0x10000000; + } + return false; } =20 /* 6. Locate the PTE in the hash table */ pte_offset =3D ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte); if (pte_offset =3D=3D -1) { - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x40000000; - } else { - cs->exception_index =3D POWERPC_EXCP_DSI; - env->error_code =3D 0; - env->spr[SPR_DAR] =3D eaddr; - if (access_type =3D=3D MMU_DATA_STORE) { - env->spr[SPR_DSISR] =3D 0x42000000; + if (guest_visible) { + if (access_type =3D=3D MMU_INST_FETCH) { + cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0x40000000; } else { - env->spr[SPR_DSISR] =3D 0x40000000; + cs->exception_index =3D POWERPC_EXCP_DSI; + env->error_code =3D 0; + env->spr[SPR_DAR] =3D eaddr; + if (access_type =3D=3D MMU_DATA_STORE) { + env->spr[SPR_DSISR] =3D 0x42000000; + } else { + env->spr[SPR_DSISR] =3D 0x40000000; + } } } - - return 1; + return false; } qemu_log_mask(CPU_LOG_MMU, "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); @@ -519,20 +526,22 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, if (need_prot & ~prot) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x08000000; - } else { - cs->exception_index =3D POWERPC_EXCP_DSI; - env->error_code =3D 0; - env->spr[SPR_DAR] =3D eaddr; - if (access_type =3D=3D MMU_DATA_STORE) { - env->spr[SPR_DSISR] =3D 0x0a000000; + if (guest_visible) { + if (access_type =3D=3D MMU_INST_FETCH) { + cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0x08000000; } else { - env->spr[SPR_DSISR] =3D 0x08000000; + cs->exception_index =3D POWERPC_EXCP_DSI; + env->error_code =3D 0; + env->spr[SPR_DAR] =3D eaddr; + if (access_type =3D=3D MMU_DATA_STORE) { + env->spr[SPR_DSISR] =3D 0x0a000000; + } else { + env->spr[SPR_DSISR] =3D 0x08000000; + } } } - return 1; + return false; } =20 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); @@ -556,45 +565,38 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, =20 /* 9. Determine the real address from the PTE */ =20 - raddr =3D ppc_hash32_pte_raddr(sr, pte, eaddr); - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); - - return 0; + *raddrp =3D ppc_hash32_pte_raddr(sr, pte, eaddr); + *protp =3D prot; + return true; } =20 -hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx) { - CPUPPCState *env =3D &cpu->env; - target_ulong sr; - hwaddr pte_offset; - ppc_hash_pte32_t pte; - int prot; - - if (msr_dr =3D=3D 0) { - /* Translation is off */ - return eaddr; - } + CPUState *cs =3D CPU(cpu); + int page_size, prot; + hwaddr raddr; =20 - if (env->nb_BATs !=3D 0) { - hwaddr raddr =3D ppc_hash32_bat_lookup(cpu, eaddr, 0, &prot); - if (raddr !=3D -1) { - return raddr; - } + /* Translate eaddr to raddr (where raddr is addr qemu needs for access= ) */ + if (!ppc_hash32_xlate(cpu, eaddr, access_type, &raddr, + &page_size, &prot, true)) { + return 1; } =20 - sr =3D env->sr[eaddr >> 28]; + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + prot, mmu_idx, 1UL << page_size); + return 0; +} =20 - if (sr & SR32_T) { - /* FIXME: Add suitable debug support for Direct Store segments */ - return -1; - } +hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) +{ + int psize, prot; + hwaddr raddr; =20 - pte_offset =3D ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte); - if (pte_offset =3D=3D -1) { + if (!ppc_hash32_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, + &psize, &prot, false)) { return -1; } =20 - return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK; + return raddr & TARGET_PAGE_MASK; } --=20 2.17.1 From nobody Sat May 4 18:24:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162428053955896.87215266871783; Mon, 21 Jun 2021 06:02:19 -0700 (PDT) Received: from localhost ([::1]:58954 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJZB-0000tb-9I for importer2@patchew.org; Mon, 21 Jun 2021 09:02:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvJQK-0008Ec-TE; Mon, 21 Jun 2021 08:53:08 -0400 Received: from [201.28.113.2] (port=47857 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJQI-0004nA-Qe; Mon, 21 Jun 2021 08:53:08 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 21 Jun 2021 09:51:40 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id 4A9F580005E; Mon, 21 Jun 2021 09:51:40 -0300 (-03) From: "Bruno Larsen (billionai)" To: qemu-devel@nongnu.org Subject: [PATCH v2 07/10] target/ppc: Split out ppc_jumbo_xlate Date: Mon, 21 Jun 2021 09:51:12 -0300 Message-Id: <20210621125115.67717-8-bruno.larsen@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> References: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> X-OriginalArrivalTime: 21 Jun 2021 12:51:40.0461 (UTC) FILETIME=[2E126DD0:01D7669C] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=bruno.larsen@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: farosas@linux.ibm.com, Richard Henderson , luis.pires@eldorado.org.br, Greg Kurz , lucas.araujo@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Mirror the interface of ppc_radix64_xlate (mostly), putting all of the logic for older mmu translation into a single entry point. For booke, we need to add mmu_idx to the xlate-style interface. Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 179 +++++++++++++++++++++------------------- 1 file changed, 96 insertions(+), 83 deletions(-) diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index c4b1c93e47..2e92deb105 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1435,48 +1435,6 @@ static int get_physical_address(CPUPPCState *env, mm= u_ctx_t *ctx, } #endif =20 -hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; - mmu_ctx_t ctx; - - switch (env->mmu_model) { -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_07: - return ppc_hash64_get_phys_page_debug(cpu, addr); - case POWERPC_MMU_3_00: - return ppc64_v3_get_phys_page_debug(cpu, addr); -#endif - - case POWERPC_MMU_32B: - case POWERPC_MMU_601: - return ppc_hash32_get_phys_page_debug(cpu, addr); - - default: - ; - } - - if (unlikely(get_physical_address(env, &ctx, addr, MMU_DATA_LOAD, - ACCESS_INT) !=3D 0)) { - - /* - * Some MMUs have separate TLBs for code and data. If we only - * try an ACCESS_INT, we may not be able to read instructions - * mapped by code TLBs, so we also try a ACCESS_CODE. - */ - if (unlikely(get_physical_address(env, &ctx, addr, MMU_INST_FETCH, - ACCESS_CODE) !=3D 0)) { - return -1; - } - } - - return ctx.raddr & TARGET_PAGE_MASK; -} - static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong ad= dress, MMUAccessType access_type, int mm= u_idx) { @@ -1532,30 +1490,38 @@ static void booke206_update_mas_tlb_miss(CPUPPCStat= e *env, target_ulong address, } =20 /* Perform address translation */ -static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, - MMUAccessType access_type, int mmu_idx) +/* TODO: Split this by mmu_model. */ +static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + int mmu_idx, bool guest_visible) { - CPUState *cs =3D env_cpu(env); - PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUState *cs =3D CPU(cpu); + CPUPPCState *env =3D &cpu->env; mmu_ctx_t ctx; int type; - int ret =3D 0; + int ret; =20 if (access_type =3D=3D MMU_INST_FETCH) { /* code access */ type =3D ACCESS_CODE; - } else { + } else if (guest_visible) { /* data access */ type =3D env->access_type; + } else { + type =3D ACCESS_INT; } - ret =3D get_physical_address_wtlb(env, &ctx, address, access_type, + + ret =3D get_physical_address_wtlb(env, &ctx, eaddr, access_type, type, mmu_idx); if (ret =3D=3D 0) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - ctx.raddr & TARGET_PAGE_MASK, ctx.prot, - mmu_idx, TARGET_PAGE_SIZE); - ret =3D 0; - } else if (ret < 0) { + *raddrp =3D ctx.raddr; + *protp =3D ctx.prot; + *psizep =3D TARGET_PAGE_BITS; + return true; + } + + if (guest_visible) { LOG_MMU_STATE(cs); if (type =3D=3D ACCESS_CODE) { switch (ret) { @@ -1565,7 +1531,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,= target_ulong address, case POWERPC_MMU_SOFT_6xx: cs->exception_index =3D POWERPC_EXCP_IFTLB; env->error_code =3D 1 << 18; - env->spr[SPR_IMISS] =3D address; + env->spr[SPR_IMISS] =3D eaddr; env->spr[SPR_ICMP] =3D 0x80000000 | ctx.ptem; goto tlb_miss; case POWERPC_MMU_SOFT_74xx: @@ -1575,29 +1541,25 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *en= v, target_ulong address, case POWERPC_MMU_SOFT_4xx_Z: cs->exception_index =3D POWERPC_EXCP_ITLB; env->error_code =3D 0; - env->spr[SPR_40x_DEAR] =3D address; + env->spr[SPR_40x_DEAR] =3D eaddr; env->spr[SPR_40x_ESR] =3D 0x00000000; break; case POWERPC_MMU_BOOKE206: - booke206_update_mas_tlb_miss(env, address, 2, mmu_idx); + booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx); /* fall through */ case POWERPC_MMU_BOOKE: cs->exception_index =3D POWERPC_EXCP_ITLB; env->error_code =3D 0; - env->spr[SPR_BOOKE_DEAR] =3D address; + env->spr[SPR_BOOKE_DEAR] =3D eaddr; env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, M= MU_DATA_LOAD); - return -1; + break; case POWERPC_MMU_MPC8xx: - /* XXX: TODO */ cpu_abort(cs, "MPC8xx MMU model is not implemented\n"); - break; case POWERPC_MMU_REAL: cpu_abort(cs, "PowerPC in real mode should never raise= " "any MMU exceptions\n"); - return -1; default: cpu_abort(cs, "Unknown or invalid MMU model\n"); - return -1; } break; case -2: @@ -1634,7 +1596,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,= target_ulong address, cs->exception_index =3D POWERPC_EXCP_DLTLB; env->error_code =3D 0; } - env->spr[SPR_DMISS] =3D address; + env->spr[SPR_DMISS] =3D eaddr; env->spr[SPR_DCMP] =3D 0x80000000 | ctx.ptem; tlb_miss: env->error_code |=3D ctx.key << 19; @@ -1652,7 +1614,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,= target_ulong address, tlb_miss_74xx: /* Implement LRU algorithm */ env->error_code =3D ctx.key << 19; - env->spr[SPR_TLBMISS] =3D (address & ~((target_ulong)0= x3)) | + env->spr[SPR_TLBMISS] =3D (eaddr & ~((target_ulong)0x3= )) | ((env->last_way + 1) & (env->nb_ways - 1)); env->spr[SPR_PTEHI] =3D 0x80000000 | ctx.ptem; break; @@ -1660,7 +1622,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,= target_ulong address, case POWERPC_MMU_SOFT_4xx_Z: cs->exception_index =3D POWERPC_EXCP_DTLB; env->error_code =3D 0; - env->spr[SPR_40x_DEAR] =3D address; + env->spr[SPR_40x_DEAR] =3D eaddr; if (access_type =3D=3D MMU_DATA_STORE) { env->spr[SPR_40x_ESR] =3D 0x00800000; } else { @@ -1670,23 +1632,20 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *en= v, target_ulong address, case POWERPC_MMU_MPC8xx: /* XXX: TODO */ cpu_abort(cs, "MPC8xx MMU model is not implemented\n"); - break; case POWERPC_MMU_BOOKE206: - booke206_update_mas_tlb_miss(env, address, access_type= , mmu_idx); + booke206_update_mas_tlb_miss(env, eaddr, access_type, = mmu_idx); /* fall through */ case POWERPC_MMU_BOOKE: cs->exception_index =3D POWERPC_EXCP_DTLB; env->error_code =3D 0; - env->spr[SPR_BOOKE_DEAR] =3D address; + env->spr[SPR_BOOKE_DEAR] =3D eaddr; env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, a= ccess_type); - return -1; + break; case POWERPC_MMU_REAL: cpu_abort(cs, "PowerPC in real mode should never raise= " "any MMU exceptions\n"); - return -1; default: cpu_abort(cs, "Unknown or invalid MMU model\n"); - return -1; } break; case -2: @@ -1695,16 +1654,16 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *en= v, target_ulong address, env->error_code =3D 0; if (env->mmu_model =3D=3D POWERPC_MMU_SOFT_4xx || env->mmu_model =3D=3D POWERPC_MMU_SOFT_4xx_Z) { - env->spr[SPR_40x_DEAR] =3D address; + env->spr[SPR_40x_DEAR] =3D eaddr; if (access_type =3D=3D MMU_DATA_STORE) { env->spr[SPR_40x_ESR] |=3D 0x00800000; } } else if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { - env->spr[SPR_BOOKE_DEAR] =3D address; + env->spr[SPR_BOOKE_DEAR] =3D eaddr; env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, a= ccess_type); } else { - env->spr[SPR_DAR] =3D address; + env->spr[SPR_DAR] =3D eaddr; if (access_type =3D=3D MMU_DATA_STORE) { env->spr[SPR_DSISR] =3D 0x0A000000; } else { @@ -1719,13 +1678,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *en= v, target_ulong address, /* Floating point load/store */ cs->exception_index =3D POWERPC_EXCP_ALIGN; env->error_code =3D POWERPC_EXCP_ALIGN_FP; - env->spr[SPR_DAR] =3D address; + env->spr[SPR_DAR] =3D eaddr; break; case ACCESS_RES: /* lwarx, ldarx or stwcx. */ cs->exception_index =3D POWERPC_EXCP_DSI; env->error_code =3D 0; - env->spr[SPR_DAR] =3D address; + env->spr[SPR_DAR] =3D eaddr; if (access_type =3D=3D MMU_DATA_STORE) { env->spr[SPR_DSISR] =3D 0x06000000; } else { @@ -1736,7 +1695,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,= target_ulong address, /* eciwx or ecowx */ cs->exception_index =3D POWERPC_EXCP_DSI; env->error_code =3D 0; - env->spr[SPR_DAR] =3D address; + env->spr[SPR_DAR] =3D eaddr; if (access_type =3D=3D MMU_DATA_STORE) { env->spr[SPR_DSISR] =3D 0x06100000; } else { @@ -1748,16 +1707,14 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *en= v, target_ulong address, cs->exception_index =3D POWERPC_EXCP_PROGRAM; env->error_code =3D POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; - env->spr[SPR_DAR] =3D address; + env->spr[SPR_DAR] =3D eaddr; break; } break; } } - ret =3D 1; } - - return ret; + return false; } =20 #ifdef CONFIG_TCG @@ -2942,6 +2899,62 @@ void helper_check_tlb_flush_global(CPUPPCState *env) =20 /*************************************************************************= ****/ =20 +static int cpu_ppc_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx) +{ + CPUState *cs =3D CPU(cpu); + int page_size, prot; + hwaddr raddr; + + if (!ppc_jumbo_xlate(cpu, eaddr, access_type, &raddr, + &page_size, &prot, mmu_idx, true)) { + return 1; + } + + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + prot, mmu_idx, 1UL << page_size); + return 0; +} + +hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + hwaddr raddr; + int s, p; + + switch (env->mmu_model) { +#if defined(TARGET_PPC64) + case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: + case POWERPC_MMU_2_06: + case POWERPC_MMU_2_07: + return ppc_hash64_get_phys_page_debug(cpu, addr); + case POWERPC_MMU_3_00: + return ppc64_v3_get_phys_page_debug(cpu, addr); +#endif + + case POWERPC_MMU_32B: + case POWERPC_MMU_601: + return ppc_hash32_get_phys_page_debug(cpu, addr); + + default: + ; + } + + /* + * Some MMUs have separate TLBs for code and data. If we only + * try an MMU_DATA_LOAD, we may not be able to read instructions + * mapped by code TLBs, so we also try a MMU_INST_FETCH. + */ + if (ppc_jumbo_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, 0, false= ) || + ppc_jumbo_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, 0, fals= e)) { + return raddr & TARGET_PAGE_MASK; + } + return -1; +} + + bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -2969,7 +2982,7 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, break; =20 default: - ret =3D cpu_ppc_handle_mmu_fault(env, addr, access_type, mmu_idx); + ret =3D cpu_ppc_handle_mmu_fault(cpu, addr, access_type, mmu_idx); break; } if (unlikely(ret !=3D 0)) { --=20 2.17.1 From nobody Sat May 4 18:24:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624280713721239.95388433881794; Mon, 21 Jun 2021 06:05:13 -0700 (PDT) Received: from localhost ([::1]:37466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJc0-0005f4-7T for importer2@patchew.org; Mon, 21 Jun 2021 09:05:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvJQP-0008MT-Oz; Mon, 21 Jun 2021 08:53:13 -0400 Received: from [201.28.113.2] (port=47857 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJQM-0004nA-1L; Mon, 21 Jun 2021 08:53:13 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 21 Jun 2021 09:51:40 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id A3CAF800055; Mon, 21 Jun 2021 09:51:40 -0300 (-03) From: "Bruno Larsen (billionai)" To: qemu-devel@nongnu.org Subject: [PATCH v2 08/10] target/ppc: Introduce ppc_xlate Date: Mon, 21 Jun 2021 09:51:13 -0300 Message-Id: <20210621125115.67717-9-bruno.larsen@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> References: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> X-OriginalArrivalTime: 21 Jun 2021 12:51:40.0820 (UTC) FILETIME=[2E493540:01D7669C] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=bruno.larsen@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: farosas@linux.ibm.com, Richard Henderson , luis.pires@eldorado.org.br, Greg Kurz , lucas.araujo@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Create one common dispatch for all of the ppc_*_xlate functions. Use ppc64_v3_radix to directly dispatch between ppc_radix64_xlate and ppc_hash64_xlate. Remove the separate *_handle_mmu_fault and *_get_phys_page_debug functions, using common code for ppc_cpu_tlb_fill and ppc_cpu_get_phys_page_debug. Signed-off-by: Richard Henderson --- target/ppc/mmu-book3s-v3.c | 19 ------- target/ppc/mmu-book3s-v3.h | 5 -- target/ppc/mmu-hash32.c | 38 ++------------ target/ppc/mmu-hash32.h | 6 +-- target/ppc/mmu-hash64.c | 37 ++------------ target/ppc/mmu-hash64.h | 6 +-- target/ppc/mmu-radix64.c | 38 ++------------ target/ppc/mmu-radix64.h | 6 +-- target/ppc/mmu_helper.c | 100 ++++++++++++++----------------------- 9 files changed, 55 insertions(+), 200 deletions(-) diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c index c78fd8dc0e..f4985bae78 100644 --- a/target/ppc/mmu-book3s-v3.c +++ b/target/ppc/mmu-book3s-v3.c @@ -23,25 +23,6 @@ #include "mmu-book3s-v3.h" #include "mmu-radix64.h" =20 -int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, - int mmu_idx) -{ - if (ppc64_v3_radix(cpu)) { /* Guest uses radix */ - return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx); - } else { /* Guest uses hash */ - return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx); - } -} - -hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr eaddr) -{ - if (ppc64_v3_radix(cpu)) { - return ppc_radix64_get_phys_page_debug(cpu, eaddr); - } else { - return ppc_hash64_get_phys_page_debug(cpu, eaddr); - } -} - bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *= entry) { uint64_t patb =3D cpu->env.spr[SPR_PTCR] & PTCR_PATB; diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h index 7b89be54b8..a1326df969 100644 --- a/target/ppc/mmu-book3s-v3.h +++ b/target/ppc/mmu-book3s-v3.h @@ -67,11 +67,6 @@ static inline bool ppc64_v3_radix(PowerPCCPU *cpu) return !!(cpu->env.spr[SPR_LPCR] & LPCR_HR); } =20 -hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr eaddr); - -int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, - int mmu_idx); - static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu) { uint64_t base; diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index ad22372c07..6a07c345e4 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -424,10 +424,9 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, pp= c_hash_pte32_t pte, return (rpn & ~mask) | (eaddr & mask); } =20 -static bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, - hwaddr *raddrp, int *psizep, int *protp, - bool guest_visible) +bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_t= ype, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; @@ -569,34 +568,3 @@ static bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr ea= ddr, *protp =3D prot; return true; } - -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) -{ - CPUState *cs =3D CPU(cpu); - int page_size, prot; - hwaddr raddr; - - /* Translate eaddr to raddr (where raddr is addr qemu needs for access= ) */ - if (!ppc_hash32_xlate(cpu, eaddr, access_type, &raddr, - &page_size, &prot, true)) { - return 1; - } - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, 1UL << page_size); - return 0; -} - -hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) -{ - int psize, prot; - hwaddr raddr; - - if (!ppc_hash32_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, - &psize, &prot, false)) { - return -1; - } - - return raddr & TARGET_PAGE_MASK; -} diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h index 30e35718a7..8694eccabd 100644 --- a/target/ppc/mmu-hash32.h +++ b/target/ppc/mmu-hash32.h @@ -4,9 +4,9 @@ #ifndef CONFIG_USER_ONLY =20 hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash); -hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, - MMUAccessType access_type, int mmu_idx); +bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_t= ype, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible); =20 /* * Segment register definitions diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index c6b167b4dc..c1b98a97e9 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -873,10 +873,9 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t = *slb) return -1; } =20 -static bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, - hwaddr *raddrp, int *psizep, int *protp, - bool guest_visible) +bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_t= ype, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; @@ -1094,36 +1093,6 @@ static bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr = eaddr, return true; } =20 -int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) -{ - CPUState *cs =3D CPU(cpu); - int page_size, prot; - hwaddr raddr; - - if (!ppc_hash64_xlate(cpu, eaddr, access_type, &raddr, - &page_size, &prot, true)) { - return 1; - } - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, 1UL << page_size); - return 0; -} - -hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) -{ - int psize, prot; - hwaddr raddr; - - if (!ppc_hash64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, - &psize, &prot, false)) { - return -1; - } - - return raddr & TARGET_PAGE_MASK; -} - void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, target_ulong pte0, target_ulong pte1) { diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 3e8a8eec1f..9f338e1fe9 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -7,9 +7,9 @@ void dump_slb(PowerPCCPU *cpu); int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, target_ulong esid, target_ulong vsid); -hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); -int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, - MMUAccessType access_type, int mmu_idx); +bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_t= ype, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible); void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong pte_index, target_ulong pte0, target_ulong pte1); diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 2d5f0850c9..cbd404bfa4 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -463,10 +463,9 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU= *cpu, * | =3D On | Process Scoped | Scoped | * +-------------+----------------+---------------+ */ -static bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, - hwaddr *raddr, int *psizep, int *protp, - bool guest_visible) +bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_= type, + hwaddr *raddr, int *psizep, int *protp, + bool guest_visible) { CPUPPCState *env =3D &cpu->env; uint64_t lpid, pid; @@ -584,34 +583,3 @@ static bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr e= addr, =20 return true; } - -int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) -{ - CPUState *cs =3D CPU(cpu); - int page_size, prot; - hwaddr raddr; - - /* Translate eaddr to raddr (where raddr is addr qemu needs for access= ) */ - if (!ppc_radix64_xlate(cpu, eaddr, access_type, &raddr, - &page_size, &prot, true)) { - return 1; - } - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, 1UL << page_size); - return 0; -} - -hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) -{ - int psize, prot; - hwaddr raddr; - - if (!ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, - &psize, &prot, false)) { - return -1; - } - - return raddr & TARGET_PAGE_MASK; -} diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h index 94bd72cb38..6b13b89b64 100644 --- a/target/ppc/mmu-radix64.h +++ b/target/ppc/mmu-radix64.h @@ -44,9 +44,9 @@ =20 #ifdef TARGET_PPC64 =20 -int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx); -hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); +bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_= type, + hwaddr *raddr, int *psizep, int *protp, + bool guest_visible); =20 static inline int ppc_radix64_get_prot_eaa(uint64_t pte) { diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 2e92deb105..a0e4e027d3 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -2899,98 +2899,72 @@ void helper_check_tlb_flush_global(CPUPPCState *env) =20 /*************************************************************************= ****/ =20 -static int cpu_ppc_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) +static bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_t= ype, + hwaddr *raddrp, int *psizep, int *protp, + int mmu_idx, bool guest_visible) { - CPUState *cs =3D CPU(cpu); - int page_size, prot; - hwaddr raddr; - - if (!ppc_jumbo_xlate(cpu, eaddr, access_type, &raddr, - &page_size, &prot, mmu_idx, true)) { - return 1; - } - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, 1UL << page_size); - return 0; -} - -hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; - hwaddr raddr; - int s, p; - - switch (env->mmu_model) { + switch (cpu->env.mmu_model) { #if defined(TARGET_PPC64) + case POWERPC_MMU_3_00: + if (ppc64_v3_radix(cpu)) { + return ppc_radix64_xlate(cpu, eaddr, access_type, + raddrp, psizep, protp, guest_visible); + } + /* fall through */ case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: case POWERPC_MMU_2_07: - return ppc_hash64_get_phys_page_debug(cpu, addr); - case POWERPC_MMU_3_00: - return ppc64_v3_get_phys_page_debug(cpu, addr); + return ppc_hash64_xlate(cpu, eaddr, access_type, + raddrp, psizep, protp, guest_visible); #endif =20 case POWERPC_MMU_32B: case POWERPC_MMU_601: - return ppc_hash32_get_phys_page_debug(cpu, addr); + return ppc_hash32_xlate(cpu, eaddr, access_type, + raddrp, psizep, protp, guest_visible); =20 default: - ; + return ppc_jumbo_xlate(cpu, eaddr, access_type, raddrp, + psizep, protp, mmu_idx, guest_visible); } +} + +hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + hwaddr raddr; + int s, p; =20 /* * Some MMUs have separate TLBs for code and data. If we only * try an MMU_DATA_LOAD, we may not be able to read instructions * mapped by code TLBs, so we also try a MMU_INST_FETCH. */ - if (ppc_jumbo_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, 0, false= ) || - ppc_jumbo_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, 0, fals= e)) { + if (ppc_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, 0, false) || + ppc_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, 0, false)) { return raddr & TARGET_PAGE_MASK; } return -1; } =20 - -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; - int ret; - - switch (env->mmu_model) { -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_07: - ret =3D ppc_hash64_handle_mmu_fault(cpu, addr, access_type, mmu_id= x); - break; - case POWERPC_MMU_3_00: - ret =3D ppc64_v3_handle_mmu_fault(cpu, addr, access_type, mmu_idx); - break; -#endif - - case POWERPC_MMU_32B: - case POWERPC_MMU_601: - ret =3D ppc_hash32_handle_mmu_fault(cpu, addr, access_type, mmu_id= x); - break; + hwaddr raddr; + int page_size, prot; =20 - default: - ret =3D cpu_ppc_handle_mmu_fault(cpu, addr, access_type, mmu_idx); - break; + if (ppc_xlate(cpu, eaddr, access_type, &raddr, + &page_size, &prot, mmu_idx, !probe)) { + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, + prot, mmu_idx, 1UL << page_size); + return true; } - if (unlikely(ret !=3D 0)) { - if (probe) { - return false; - } - raise_exception_err_ra(env, cs->exception_index, env->error_code, - retaddr); + if (probe) { + return false; } - return true; + raise_exception_err_ra(&cpu->env, cs->exception_index, + cpu->env.error_code, retaddr); } --=20 2.17.1 From nobody Sat May 4 18:24:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624280793828693.122061888831; Mon, 21 Jun 2021 06:06:33 -0700 (PDT) Received: from localhost ([::1]:40590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJdI-0007md-JU for importer2@patchew.org; Mon, 21 Jun 2021 09:06:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvJQS-0008Pm-6T; Mon, 21 Jun 2021 08:53:17 -0400 Received: from [201.28.113.2] (port=47857 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJQQ-0004nA-Qk; Mon, 21 Jun 2021 08:53:15 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 21 Jun 2021 09:51:40 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id CE64280005E; Mon, 21 Jun 2021 09:51:40 -0300 (-03) From: "Bruno Larsen (billionai)" To: qemu-devel@nongnu.org Subject: [PATCH v2 09/10] target/ppc: Restrict ppc_cpu_tlb_fill to TCG Date: Mon, 21 Jun 2021 09:51:14 -0300 Message-Id: <20210621125115.67717-10-bruno.larsen@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> References: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> X-OriginalArrivalTime: 21 Jun 2021 12:51:40.0992 (UTC) FILETIME=[2E637400:01D7669C] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=bruno.larsen@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: farosas@linux.ibm.com, Richard Henderson , luis.pires@eldorado.org.br, Greg Kurz , lucas.araujo@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This function is used by TCGCPUOps, and is thus TCG specific. Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index a0e4e027d3..ba1952c77d 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -2948,6 +2948,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) return -1; } =20 +#ifdef CONFIG_TCG bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -2968,3 +2969,4 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int = size, raise_exception_err_ra(&cpu->env, cs->exception_index, cpu->env.error_code, retaddr); } +#endif --=20 2.17.1 From nobody Sat May 4 18:24:25 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624280744338330.59814562580414; Mon, 21 Jun 2021 06:05:44 -0700 (PDT) Received: from localhost ([::1]:38348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJcV-0006Fp-6n for importer2@patchew.org; Mon, 21 Jun 2021 09:05:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42142) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvJQV-0008R6-Ah; Mon, 21 Jun 2021 08:53:23 -0400 Received: from [201.28.113.2] (port=47857 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJQT-0004nA-Ei; Mon, 21 Jun 2021 08:53:19 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 21 Jun 2021 09:51:41 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id 1222B800055; Mon, 21 Jun 2021 09:51:41 -0300 (-03) From: "Bruno Larsen (billionai)" To: qemu-devel@nongnu.org Subject: [PATCH v2 10/10] target/ppc: fix address translation bug for radix mmus Date: Mon, 21 Jun 2021 09:51:15 -0300 Message-Id: <20210621125115.67717-11-bruno.larsen@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> References: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> X-OriginalArrivalTime: 21 Jun 2021 12:51:41.0242 (UTC) FILETIME=[2E8999A0:01D7669C] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=bruno.larsen@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: farosas@linux.ibm.com, richard.henderson@linaro.org, luis.pires@eldorado.org.br, Greg Kurz , lucas.araujo@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This commit attempts to fix the first bug mentioned by Richard Henderson in https://lists.nongnu.org/archive/html/qemu-devel/2021-05/msg06247.html To sumarize the bug here, when radix-style mmus are translating an address, they might need to call a second level of translation, with hypervisor privileges. However, the way it was being done up until this point meant that the second level translation had the same privileges as the first level.=20 This patch attempts to correct that by making radix64_*_xlate functions receive the mmu_idx, and passing one with the correct permission for the second level translation. The mmuidx macros added by this patch are only correct for non-bookE mmus, because BookE style set the IS and DS bits inverted and there might be other subtle differences. However, there doesn't seem to be BookE cpus that have radix-style mmus, so we left a comment there to document the issue, in case a machine does have that and was missed. As part of this cleanup, we now need to send the correct mmmu_idx when calling get_phys_page_debug, otherwise we might not be able to see the memory that the CPU could Suggested-by: Richard Henderson Signed-off-by: Bruno Larsen (billionai) Reviewed-by: Richard Henderson --- target/ppc/internal.h | 13 +++++++++++++ target/ppc/mmu-radix64.c | 37 +++++++++++++++++++++---------------- target/ppc/mmu-radix64.h | 2 +- target/ppc/mmu_helper.c | 8 +++++--- 4 files changed, 40 insertions(+), 20 deletions(-) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index f1fd3c8d04..11a0e22cc9 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -245,4 +245,17 @@ static inline int prot_for_access_type(MMUAccessType a= ccess_type) g_assert_not_reached(); } =20 +/* + * These correspond to the mmu_idx values computed in + * hreg_compute_hflags_value. See the tables therein + */ +static inline bool mmuidx_pr(int idx) { return !(idx & 1); } +/* + * This macro is only correct for non Book-E MMUs. We can add an if clause + * to check for mmu model, but since those don't have the bug, we decided = to + * keep the code clean. + */ +static inline bool mmuidx_real(int idx) { return idx & 2; } +static inline bool mmuidx_hv(int idx) { return idx & 4; } + #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index cbd404bfa4..5b0e62e676 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -155,7 +155,7 @@ static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, MMUA= ccessType access_type, =20 static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access_t= ype, uint64_t pte, int *fault_cause, int *pr= ot, - bool partition_scoped) + int mmu_idx, bool partition_scoped) { CPUPPCState *env =3D &cpu->env; int need_prot; @@ -173,7 +173,8 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMU= AccessType access_type, /* Determine permissions allowed by Encoded Access Authority */ if (!partition_scoped && (pte & R_PTE_EAA_PRIV) && msr_pr) { *prot =3D 0; - } else if (msr_pr || (pte & R_PTE_EAA_PRIV) || partition_scoped) { + } else if (mmuidx_pr(mmu_idx) || (pte & R_PTE_EAA_PRIV) || + partition_scoped) { *prot =3D ppc_radix64_get_prot_eaa(pte); } else { /* !msr_pr && !(pte & R_PTE_EAA_PRIV) && !partition_scoped */ *prot =3D ppc_radix64_get_prot_eaa(pte); @@ -299,7 +300,7 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCP= U *cpu, ppc_v3_pate_t pate, hwaddr *h_raddr, int *h_prot, int *h_page_size, bool pde_a= ddr, - bool guest_visible) + int mmu_idx, bool guest_visi= ble) { int fault_cause =3D 0; hwaddr pte_addr; @@ -310,7 +311,8 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCP= U *cpu, if (ppc_radix64_walk_tree(CPU(cpu)->as, g_raddr, pate.dw0 & PRTBE_R_RP= DB, pate.dw0 & PRTBE_R_RPDS, h_raddr, h_page_siz= e, &pte, &fault_cause, &pte_addr) || - ppc_radix64_check_prot(cpu, access_type, pte, &fault_cause, h_prot= , true)) { + ppc_radix64_check_prot(cpu, access_type, pte, + &fault_cause, h_prot, mmu_idx, true)) { if (pde_addr) { /* address being translated was that of a guest pd= e */ fault_cause |=3D DSISR_PRTABLE_FAULT; } @@ -332,7 +334,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU = *cpu, vaddr eaddr, uint64_t pid, ppc_v3_pate_t pate, hwaddr *g_= raddr, int *g_prot, int *g_page_size, - bool guest_visible) + int mmu_idx, bool guest_visibl= e) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; @@ -367,7 +369,8 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU = *cpu, ret =3D ppc_radix64_partition_scoped_xlate(cpu, 0, eaddr, prtbe_ad= dr, pate, &h_raddr, &h_prot, &h_page_size, true, - guest_visible); + /* mmu_idx is 5 because we're translating from hypervisor scop= e */ + 5, guest_visible); if (ret) { return ret; } @@ -407,7 +410,8 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU = *cpu, ret =3D ppc_radix64_partition_scoped_xlate(cpu, 0, eaddr, pte_= addr, pate, &h_raddr, &h_pr= ot, &h_page_size, true, - guest_visible); + /* mmu_idx is 5 because we're translating from hypervisor scop= e */ + 5, guest_visible); if (ret) { return ret; } @@ -431,7 +435,8 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU = *cpu, *g_raddr =3D (rpn & ~mask) | (eaddr & mask); } =20 - if (ppc_radix64_check_prot(cpu, access_type, pte, &fault_cause, g_prot= , false)) { + if (ppc_radix64_check_prot(cpu, access_type, pte, &fault_cause, + g_prot, mmu_idx, false)) { /* Access denied due to protection */ if (guest_visible) { ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause); @@ -464,7 +469,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU = *cpu, * +-------------+----------------+---------------+ */ bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_= type, - hwaddr *raddr, int *psizep, int *protp, + hwaddr *raddr, int *psizep, int *protp, int mmu_idx, bool guest_visible) { CPUPPCState *env =3D &cpu->env; @@ -474,17 +479,17 @@ bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, = MMUAccessType access_type, hwaddr g_raddr; bool relocation; =20 - assert(!(msr_hv && cpu->vhyp)); + assert(!(mmuidx_hv(mmu_idx) && cpu->vhyp)); =20 - relocation =3D (access_type =3D=3D MMU_INST_FETCH ? msr_ir : msr_dr); + relocation =3D !mmuidx_real(mmu_idx); =20 /* HV or virtual hypervisor Real Mode Access */ - if (!relocation && (msr_hv || cpu->vhyp)) { + if (!relocation && (mmuidx_hv(mmu_idx) || cpu->vhyp)) { /* In real mode top 4 effective addr bits (mostly) ignored */ *raddr =3D eaddr & 0x0FFFFFFFFFFFFFFFULL; =20 /* In HV mode, add HRMOR if top EA bit is clear */ - if (msr_hv || !env->has_hv_mode) { + if (mmuidx_hv(mmu_idx) || !env->has_hv_mode) { if (!(eaddr >> 63)) { *raddr |=3D env->spr[SPR_HRMOR]; } @@ -546,7 +551,7 @@ bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MM= UAccessType access_type, if (relocation) { int ret =3D ppc_radix64_process_scoped_xlate(cpu, access_type, ead= dr, pid, pate, &g_raddr, &prot, - &psize, guest_visible); + &psize, mmu_idx, guest_= visible); if (ret) { return false; } @@ -564,13 +569,13 @@ bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, = MMUAccessType access_type, * quadrants 1 or 2. Translates a guest real address to a host * real address. */ - if (lpid || !msr_hv) { + if (lpid || !mmuidx_hv(mmu_idx)) { int ret; =20 ret =3D ppc_radix64_partition_scoped_xlate(cpu, access_type, e= addr, g_raddr, pate, raddr, &prot, &psize, false, - guest_visible); + mmu_idx, guest_visibl= e); if (ret) { return false; } diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h index 6b13b89b64..b70357cf34 100644 --- a/target/ppc/mmu-radix64.h +++ b/target/ppc/mmu-radix64.h @@ -45,7 +45,7 @@ #ifdef TARGET_PPC64 =20 bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_= type, - hwaddr *raddr, int *psizep, int *protp, + hwaddr *raddr, int *psizep, int *protp, int mmu_idx, bool guest_visible); =20 static inline int ppc_radix64_get_prot_eaa(uint64_t pte) diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index ba1952c77d..9dcdf88597 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -2908,7 +2908,7 @@ static bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, M= MUAccessType access_type, case POWERPC_MMU_3_00: if (ppc64_v3_radix(cpu)) { return ppc_radix64_xlate(cpu, eaddr, access_type, - raddrp, psizep, protp, guest_visible); + raddrp, psizep, protp, mmu_idx, guest= _visible); } /* fall through */ case POWERPC_MMU_64B: @@ -2941,8 +2941,10 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vad= dr addr) * try an MMU_DATA_LOAD, we may not be able to read instructions * mapped by code TLBs, so we also try a MMU_INST_FETCH. */ - if (ppc_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, 0, false) || - ppc_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, 0, false)) { + if (ppc_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, + cpu_mmu_index(&cpu->env, false), false) || + ppc_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, + cpu_mmu_index(&cpu->env, true), false)) { return raddr & TARGET_PAGE_MASK; } return -1; --=20 2.17.1