From nobody Wed Feb 11 03:26:16 2026 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162428086887979.59957143873521; Mon, 21 Jun 2021 06:07:48 -0700 (PDT) Received: from localhost ([::1]:42472 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJeV-0000c9-Gv for importer2@patchew.org; Mon, 21 Jun 2021 09:07:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42014) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvJQH-00085v-Kn; Mon, 21 Jun 2021 08:53:05 -0400 Received: from [201.28.113.2] (port=47857 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvJQF-0004nA-Ii; Mon, 21 Jun 2021 08:53:05 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 21 Jun 2021 09:51:40 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id 1FC3F800055; Mon, 21 Jun 2021 09:51:40 -0300 (-03) From: "Bruno Larsen (billionai)" To: qemu-devel@nongnu.org Subject: [PATCH v2 06/10] target/ppc: Split out ppc_hash32_xlate Date: Mon, 21 Jun 2021 09:51:11 -0300 Message-Id: <20210621125115.67717-7-bruno.larsen@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> References: <20210621125115.67717-1-bruno.larsen@eldorado.org.br> X-OriginalArrivalTime: 21 Jun 2021 12:51:40.0398 (UTC) FILETIME=[2E08D0E0:01D7669C] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=bruno.larsen@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: farosas@linux.ibm.com, Richard Henderson , luis.pires@eldorado.org.br, Greg Kurz , lucas.araujo@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Mirror the interface of ppc_radix64_xlate, putting all of the logic for hash32 translation into a single entry point. Signed-off-by: Richard Henderson --- target/ppc/mmu-hash32.c | 224 ++++++++++++++++++++-------------------- 1 file changed, 113 insertions(+), 111 deletions(-) diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 8f19b43e47..ad22372c07 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -218,10 +218,11 @@ static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, = target_ulong ea, return -1; } =20 -static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, - target_ulong eaddr, - MMUAccessType access_type, - hwaddr *raddr, int *prot) +static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, + target_ulong eaddr, + MMUAccessType access_type, + hwaddr *raddr, int *prot, + bool guest_visible) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; @@ -238,17 +239,23 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, t= arget_ulong sr, */ *raddr =3D ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF); *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return 0; + return true; } =20 if (access_type =3D=3D MMU_INST_FETCH) { /* No code fetch is allowed in direct-store areas */ - cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x10000000; - return 1; + if (guest_visible) { + cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0x10000000; + } + return false; } =20 - switch (env->access_type) { + /* + * From ppc_cpu_get_phys_page_debug, env->access_type is not set. + * Assume ACCESS_INT for that case. + */ + switch (guest_visible ? env->access_type : ACCESS_INT) { case ACCESS_INT: /* Integer load/store : only access allowed */ break; @@ -257,7 +264,7 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, tar= get_ulong sr, cs->exception_index =3D POWERPC_EXCP_ALIGN; env->error_code =3D POWERPC_EXCP_ALIGN_FP; env->spr[SPR_DAR] =3D eaddr; - return 1; + return false; case ACCESS_RES: /* lwarx, ldarx or srwcx. */ env->error_code =3D 0; @@ -267,7 +274,7 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, tar= get_ulong sr, } else { env->spr[SPR_DSISR] =3D 0x04000000; } - return 1; + return false; case ACCESS_CACHE: /* * dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi @@ -276,7 +283,7 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, tar= get_ulong sr, * no-op, it's quite easy :-) */ *raddr =3D eaddr; - return 0; + return true; case ACCESS_EXT: /* eciwx or ecowx */ cs->exception_index =3D POWERPC_EXCP_DSI; @@ -287,16 +294,18 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, t= arget_ulong sr, } else { env->spr[SPR_DSISR] =3D 0x04100000; } - return 1; + return false; default: - cpu_abort(cs, "ERROR: instruction should not need " - "address translation\n"); + cpu_abort(cs, "ERROR: insn should not need address translation\n"); } - if ((access_type =3D=3D MMU_DATA_STORE || key !=3D 1) && - (access_type =3D=3D MMU_DATA_LOAD || key !=3D 0)) { + + *prot =3D key ? PAGE_READ | PAGE_WRITE : PAGE_READ; + if (*prot & prot_for_access_type(access_type)) { *raddr =3D eaddr; - return 0; - } else { + return true; + } + + if (guest_visible) { cs->exception_index =3D POWERPC_EXCP_DSI; env->error_code =3D 0; env->spr[SPR_DAR] =3D eaddr; @@ -305,8 +314,8 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, tar= get_ulong sr, } else { env->spr[SPR_DSISR] =3D 0x08000000; } - return 1; } + return false; } =20 hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash) @@ -415,8 +424,10 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, pp= c_hash_pte32_t pte, return (rpn & ~mask) | (eaddr & mask); } =20 -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) +static bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; @@ -427,43 +438,43 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, int need_prot; hwaddr raddr; =20 - need_prot =3D prot_for_access_type(access_type); + /* There are no hash32 large pages. */ + *psizep =3D TARGET_PAGE_BITS; =20 /* 1. Handle real mode accesses */ if (access_type =3D=3D MMU_INST_FETCH ? !msr_ir : !msr_dr) { /* Translation is off */ - raddr =3D eaddr; - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, - PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, - TARGET_PAGE_SIZE); - return 0; + *raddrp =3D eaddr; + *protp =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return true; } =20 + need_prot =3D prot_for_access_type(access_type); + /* 2. Check Block Address Translation entries (BATs) */ if (env->nb_BATs !=3D 0) { - raddr =3D ppc_hash32_bat_lookup(cpu, eaddr, access_type, &prot); + raddr =3D ppc_hash32_bat_lookup(cpu, eaddr, access_type, protp); if (raddr !=3D -1) { - if (need_prot & ~prot) { - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x08000000; - } else { - cs->exception_index =3D POWERPC_EXCP_DSI; - env->error_code =3D 0; - env->spr[SPR_DAR] =3D eaddr; - if (access_type =3D=3D MMU_DATA_STORE) { - env->spr[SPR_DSISR] =3D 0x0a000000; + if (need_prot & ~*protp) { + if (guest_visible) { + if (access_type =3D=3D MMU_INST_FETCH) { + cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0x08000000; } else { - env->spr[SPR_DSISR] =3D 0x08000000; + cs->exception_index =3D POWERPC_EXCP_DSI; + env->error_code =3D 0; + env->spr[SPR_DAR] =3D eaddr; + if (access_type =3D=3D MMU_DATA_STORE) { + env->spr[SPR_DSISR] =3D 0x0a000000; + } else { + env->spr[SPR_DSISR] =3D 0x08000000; + } } } - return 1; + return false; } - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, - raddr & TARGET_PAGE_MASK, prot, mmu_idx, - TARGET_PAGE_SIZE); - return 0; + *raddrp =3D raddr; + return true; } } =20 @@ -472,42 +483,38 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, =20 /* 4. Handle direct store segments */ if (sr & SR32_T) { - if (ppc_hash32_direct_store(cpu, sr, eaddr, access_type, - &raddr, &prot) =3D=3D 0) { - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, - raddr & TARGET_PAGE_MASK, prot, mmu_idx, - TARGET_PAGE_SIZE); - return 0; - } else { - return 1; - } + return ppc_hash32_direct_store(cpu, sr, eaddr, access_type, + raddrp, protp, guest_visible); } =20 /* 5. Check for segment level no-execute violation */ if (access_type =3D=3D MMU_INST_FETCH && (sr & SR32_NX)) { - cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x10000000; - return 1; + if (guest_visible) { + cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0x10000000; + } + return false; } =20 /* 6. Locate the PTE in the hash table */ pte_offset =3D ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte); if (pte_offset =3D=3D -1) { - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x40000000; - } else { - cs->exception_index =3D POWERPC_EXCP_DSI; - env->error_code =3D 0; - env->spr[SPR_DAR] =3D eaddr; - if (access_type =3D=3D MMU_DATA_STORE) { - env->spr[SPR_DSISR] =3D 0x42000000; + if (guest_visible) { + if (access_type =3D=3D MMU_INST_FETCH) { + cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0x40000000; } else { - env->spr[SPR_DSISR] =3D 0x40000000; + cs->exception_index =3D POWERPC_EXCP_DSI; + env->error_code =3D 0; + env->spr[SPR_DAR] =3D eaddr; + if (access_type =3D=3D MMU_DATA_STORE) { + env->spr[SPR_DSISR] =3D 0x42000000; + } else { + env->spr[SPR_DSISR] =3D 0x40000000; + } } } - - return 1; + return false; } qemu_log_mask(CPU_LOG_MMU, "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); @@ -519,20 +526,22 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, if (need_prot & ~prot) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x08000000; - } else { - cs->exception_index =3D POWERPC_EXCP_DSI; - env->error_code =3D 0; - env->spr[SPR_DAR] =3D eaddr; - if (access_type =3D=3D MMU_DATA_STORE) { - env->spr[SPR_DSISR] =3D 0x0a000000; + if (guest_visible) { + if (access_type =3D=3D MMU_INST_FETCH) { + cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0x08000000; } else { - env->spr[SPR_DSISR] =3D 0x08000000; + cs->exception_index =3D POWERPC_EXCP_DSI; + env->error_code =3D 0; + env->spr[SPR_DAR] =3D eaddr; + if (access_type =3D=3D MMU_DATA_STORE) { + env->spr[SPR_DSISR] =3D 0x0a000000; + } else { + env->spr[SPR_DSISR] =3D 0x08000000; + } } } - return 1; + return false; } =20 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); @@ -556,45 +565,38 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, =20 /* 9. Determine the real address from the PTE */ =20 - raddr =3D ppc_hash32_pte_raddr(sr, pte, eaddr); - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); - - return 0; + *raddrp =3D ppc_hash32_pte_raddr(sr, pte, eaddr); + *protp =3D prot; + return true; } =20 -hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx) { - CPUPPCState *env =3D &cpu->env; - target_ulong sr; - hwaddr pte_offset; - ppc_hash_pte32_t pte; - int prot; - - if (msr_dr =3D=3D 0) { - /* Translation is off */ - return eaddr; - } + CPUState *cs =3D CPU(cpu); + int page_size, prot; + hwaddr raddr; =20 - if (env->nb_BATs !=3D 0) { - hwaddr raddr =3D ppc_hash32_bat_lookup(cpu, eaddr, 0, &prot); - if (raddr !=3D -1) { - return raddr; - } + /* Translate eaddr to raddr (where raddr is addr qemu needs for access= ) */ + if (!ppc_hash32_xlate(cpu, eaddr, access_type, &raddr, + &page_size, &prot, true)) { + return 1; } =20 - sr =3D env->sr[eaddr >> 28]; + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + prot, mmu_idx, 1UL << page_size); + return 0; +} =20 - if (sr & SR32_T) { - /* FIXME: Add suitable debug support for Direct Store segments */ - return -1; - } +hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) +{ + int psize, prot; + hwaddr raddr; =20 - pte_offset =3D ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte); - if (pte_offset =3D=3D -1) { + if (!ppc_hash32_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, + &psize, &prot, false)) { return -1; } =20 - return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK; + return raddr & TARGET_PAGE_MASK; } --=20 2.17.1