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Date: Thu, 21 Apr 2022 16:36:04 +1000 Message-Id: <20220421063630.1033608-6-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650524354807100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra To allow/disallow the CSR access based on the privilege spec, a new field in the csr_ops is introduced. It also adds the privileged specification version (v1.12) for the CSRs introduced in the v1.12. This includes the new ratified extensions such as Vector, Hypervisor and secconfig CSR. However, it doesn't enforce the privilege version in this commit. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220303185440.512391-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 103 ++++++++++++++++++++++++++++++--------------- 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0f3ed88f04..7a92892cd6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -658,6 +658,8 @@ typedef struct { riscv_csr_op_fn op; riscv_csr_read128_fn read128; riscv_csr_write128_fn write128; + /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0)= */ + uint32_t min_priv_ver; } riscv_csr_operations; =20 /* CSR function table constants */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 341c2e6f23..1400027158 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3070,13 +3070,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_FRM] =3D { "frm", fs, read_frm, write_frm }, [CSR_FCSR] =3D { "fcsr", fs, read_fcsr, write_fcsr }, /* Vector CSRs */ - [CSR_VSTART] =3D { "vstart", vs, read_vstart, write_vstart }, - [CSR_VXSAT] =3D { "vxsat", vs, read_vxsat, write_vxsat }, - [CSR_VXRM] =3D { "vxrm", vs, read_vxrm, write_vxrm }, - [CSR_VCSR] =3D { "vcsr", vs, read_vcsr, write_vcsr }, - [CSR_VL] =3D { "vl", vs, read_vl }, - [CSR_VTYPE] =3D { "vtype", vs, read_vtype }, - [CSR_VLENB] =3D { "vlenb", vs, read_vlenb }, + [CSR_VSTART] =3D { "vstart", vs, read_vstart, write_vstart, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VXSAT] =3D { "vxsat", vs, read_vxsat, write_vxsat, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VXRM] =3D { "vxrm", vs, read_vxrm, write_vxrm, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VCSR] =3D { "vcsr", vs, read_vcsr, write_vcsr, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VL] =3D { "vl", vs, read_vl, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VTYPE] =3D { "vtype", vs, read_vtype, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VLENB] =3D { "vlenb", vs, read_vlenb, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, /* User Timers and Counters */ [CSR_CYCLE] =3D { "cycle", ctr, read_instret }, [CSR_INSTRET] =3D { "instret", ctr, read_instret }, @@ -3185,33 +3192,58 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SIEH] =3D { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, [CSR_SIPH] =3D { "siph", aia_smode32, NULL, NULL, rmw_siph }, =20 - [CSR_HSTATUS] =3D { "hstatus", hmode, read_hstatus, writ= e_hstatus }, - [CSR_HEDELEG] =3D { "hedeleg", hmode, read_hedeleg, writ= e_hedeleg }, - [CSR_HIDELEG] =3D { "hideleg", hmode, NULL, NULL, rmw_= hideleg }, - [CSR_HVIP] =3D { "hvip", hmode, NULL, NULL, rmw_= hvip }, - [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_= hip }, - [CSR_HIE] =3D { "hie", hmode, NULL, NULL, rmw_= hie }, - [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, writ= e_hcounteren }, - [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, writ= e_hgeie }, - [CSR_HTVAL] =3D { "htval", hmode, read_htval, writ= e_htval }, - [CSR_HTINST] =3D { "htinst", hmode, read_htinst, writ= e_htinst }, - [CSR_HGEIP] =3D { "hgeip", hmode, read_hgeip, NULL= }, - [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, writ= e_hgatp }, - [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, writ= e_htimedelta }, - [CSR_HTIMEDELTAH] =3D { "htimedeltah", hmode32, read_htimedeltah, writ= e_htimedeltah }, - - [CSR_VSSTATUS] =3D { "vsstatus", hmode, read_vsstatus, writ= e_vsstatus }, - [CSR_VSIP] =3D { "vsip", hmode, NULL, NULL, rmw_= vsip }, - [CSR_VSIE] =3D { "vsie", hmode, NULL, NULL, rmw_= vsie }, - [CSR_VSTVEC] =3D { "vstvec", hmode, read_vstvec, writ= e_vstvec }, - [CSR_VSSCRATCH] =3D { "vsscratch", hmode, read_vsscratch, writ= e_vsscratch }, - [CSR_VSEPC] =3D { "vsepc", hmode, read_vsepc, writ= e_vsepc }, - [CSR_VSCAUSE] =3D { "vscause", hmode, read_vscause, writ= e_vscause }, - [CSR_VSTVAL] =3D { "vstval", hmode, read_vstval, writ= e_vstval }, - [CSR_VSATP] =3D { "vsatp", hmode, read_vsatp, writ= e_vsatp }, - - [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, writ= e_mtval2 }, - [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, writ= e_mtinst }, + [CSR_HSTATUS] =3D { "hstatus", hmode, read_hstatus, write_= hstatus, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HEDELEG] =3D { "hedeleg", hmode, read_hedeleg, write_= hedeleg, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HIDELEG] =3D { "hideleg", hmode, NULL, NULL, rmw_hide= leg, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HVIP] =3D { "hvip", hmode, NULL, NULL, rmw_hv= ip, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_hi= p, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HIE] =3D { "hie", hmode, NULL, NULL, rmw_h= ie, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, write= _hcounteren, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, writ= e_hgeie, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HTVAL] =3D { "htval", hmode, read_htval, write_= htval, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HTINST] =3D { "htinst", hmode, read_htinst, write_= htinst, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HGEIP] =3D { "hgeip", hmode, read_hgeip, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, write_= hgatp, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, write= _htimedelta, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HTIMEDELTAH] =3D { "htimedeltah", hmode32, read_htimedeltah, writ= e_htimedeltah, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + + [CSR_VSSTATUS] =3D { "vsstatus", hmode, read_vsstatus, write_= vsstatus, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSIP] =3D { "vsip", hmode, NULL, NULL, rmw_vs= ip, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSIE] =3D { "vsie", hmode, NULL, NULL, rmw_= vsie , + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSTVEC] =3D { "vstvec", hmode, read_vstvec, write_= vstvec, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSSCRATCH] =3D { "vsscratch", hmode, read_vsscratch, write_= vsscratch, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSEPC] =3D { "vsepc", hmode, read_vsepc, write_= vsepc, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSCAUSE] =3D { "vscause", hmode, read_vscause, write_= vscause, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSTVAL] =3D { "vstval", hmode, read_vstval, write_= vstval, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSATP] =3D { "vsatp", hmode, read_vsatp, write_= vsatp, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + + [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, write_= mtval2, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, write_= mtinst, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, =20 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) = */ [CSR_HVIEN] =3D { "hvien", aia_hmode, read_zero, write_ign= ore }, @@ -3245,7 +3277,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VSIPH] =3D { "vsiph", aia_hmode32, NULL, NULL, rmw_vs= iph }, =20 /* Physical Memory Protection */ - [CSR_MSECCFG] =3D { "mseccfg", epmp, read_mseccfg, write_mseccfg }, + [CSR_MSECCFG] =3D { "mseccfg", epmp, read_mseccfg, write_mseccfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0= }, [CSR_PMPCFG0] =3D { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] =3D { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] =3D { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, --=20 2.35.1