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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650524108966100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220303185440.512391-6-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_bits.h | 39 +++++++++++++++ target/riscv/csr.c | 107 ++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 23 +++++++++ 4 files changed, 174 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7a92892cd6..1ef1b9162f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -304,6 +304,11 @@ struct CPUArchState { target_ulong spmbase; target_ulong upmmask; target_ulong upmbase; + + /* CSRs for execution enviornment configuration */ + uint64_t menvcfg; + target_ulong senvcfg; + uint64_t henvcfg; #endif target_ulong cur_pmmask; target_ulong cur_pmbase; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 48d92a81c3..bb47cf7e77 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -202,6 +202,9 @@ #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 =20 +/* Supervisor Configuration CSRs */ +#define CSR_SENVCFG 0x10A + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -247,6 +250,10 @@ #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 =20 +/* Hypervisor Configuration CSRs */ +#define CSR_HENVCFG 0x60A +#define CSR_HENVCFGH 0x61A + /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 @@ -290,6 +297,10 @@ #define CSR_VSIEH 0x214 #define CSR_VSIPH 0x254 =20 +/* Machine Configuration CSRs */ +#define CSR_MENVCFG 0x30A +#define CSR_MENVCFGH 0x31A + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 @@ -663,6 +674,34 @@ typedef enum RISCVException { #define PM_EXT_CLEAN 0x00000002ULL #define PM_EXT_DIRTY 0x00000003ULL =20 +/* Execution enviornment configuration bits */ +#define MENVCFG_FIOM BIT(0) +#define MENVCFG_CBIE (3UL << 4) +#define MENVCFG_CBCFE BIT(6) +#define MENVCFG_CBZE BIT(7) +#define MENVCFG_PBMTE BIT(62) +#define MENVCFG_STCE BIT(63) + +/* For RV32 */ +#define MENVCFGH_PBMTE BIT(30) +#define MENVCFGH_STCE BIT(31) + +#define SENVCFG_FIOM MENVCFG_FIOM +#define SENVCFG_CBIE MENVCFG_CBIE +#define SENVCFG_CBCFE MENVCFG_CBCFE +#define SENVCFG_CBZE MENVCFG_CBZE + +#define HENVCFG_FIOM MENVCFG_FIOM +#define HENVCFG_CBIE MENVCFG_CBIE +#define HENVCFG_CBCFE MENVCFG_CBCFE +#define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_PBMTE MENVCFG_PBMTE +#define HENVCFG_STCE MENVCFG_STCE + +/* For RV32 */ +#define HENVCFGH_PBMTE MENVCFGH_PBMTE +#define HENVCFGH_STCE MENVCFGH_STCE + /* Offsets for every pair of control bits per each priv level */ #define XS_OFFSET 0ULL #define U_OFFSET 2ULL diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6590cc8aa7..84a398b205 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1398,6 +1398,101 @@ static RISCVException write_mtval(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +/* Execution environment configuration setup */ +static RISCVException read_menvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->menvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_menvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask =3D MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCF= G_CBZE; + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { + mask |=3D MENVCFG_PBMTE | MENVCFG_STCE; + } + env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->menvcfg >> 32; + return RISCV_EXCP_NONE; +} + +static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask =3D MENVCFG_PBMTE | MENVCFG_STCE; + uint64_t valh =3D (uint64_t)val << 32; + + env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_senvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->senvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_senvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask =3D SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCF= G_CBZE; + + env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_henvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->henvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask =3D HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCF= G_CBZE; + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { + mask |=3D HENVCFG_PBMTE | HENVCFG_STCE; + } + + env->henvcfg =3D (env->henvcfg & ~mask) | (val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->henvcfg >> 32; + return RISCV_EXCP_NONE; +} + +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask =3D HENVCFG_PBMTE | HENVCFG_STCE; + uint64_t valh =3D (uint64_t)val << 32; + + env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); + + return RISCV_EXCP_NONE; +} + static RISCVException rmw_mip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -3158,6 +3253,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MVIPH] =3D { "mviph", aia_any32, read_zero, write_ignore }, [CSR_MIPH] =3D { "miph", aia_any32, NULL, NULL, rmw_miph }, =20 + /* Execution environment configuration */ + [CSR_MENVCFG] =3D { "menvcfg", any, read_menvcfg, write_menvcfg, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_MENVCFGH] =3D { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_SENVCFG] =3D { "senvcfg", smode, read_senvcfg, write_senvcfg, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_HENVCFG] =3D { "henvcfg", hmode, read_henvcfg, write_henvcfg, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_HENVCFGH] =3D { "henvcfgh", hmode32, read_henvcfgh, write_henvcfg= h, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 5178b3fec9..243f567949 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -231,6 +231,28 @@ static int riscv_cpu_post_load(void *opaque, int versi= on_id) return 0; } =20 +static bool envcfg_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + + return (env->priv_ver >=3D PRIV_VERSION_1_12_0 ? 1 : 0); +} + +static const VMStateDescription vmstate_envcfg =3D { + .name =3D "cpu/envcfg", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D envcfg_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.menvcfg, RISCVCPU), + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), + VMSTATE_UINT64(env.henvcfg, RISCVCPU), + + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 3, @@ -292,6 +314,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_pointermasking, &vmstate_rv128, &vmstate_kvmtimer, + &vmstate_envcfg, NULL } }; --=20 2.35.1