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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id g13-20020a62520d000000b0050a923a7754sm636877pfb.119.2022.04.21.21.04.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 21:04:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=TgdHAxqucwcWuUdvW2Ct2lWgjV0L5B12+Jl2GPsSxa8=; b=bmqmuHnaKdmtyNbcoPfoAtOT+J+VT371GUH5EYj+/h2SBm0In4BZwgagfMurZy5UIc 8VKwqPIf+vSixW0YnDEWjaOO1Vt4CEF3c+wi0LSoo89c4rhd0lC221ayNZJ99saW14zo JvmNuoQjLg776YtvEYzl477Wz02SZIGICh+cAtRknM8p1eEbafvi2e9z/LABw3lAWF3Q 8pm0uOVoFHaCayTzhxIWnyBGydK5WfU3w8pJhc9m+tGHt3iqt0RX7UC6vaSvLrGlwaLu OKRFlELJZEzb5mv0WP482Wnx1BO+0xIM4QxFpWvnbilF77IxSe8yChN34tamnGPqWPaC 7EyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=TgdHAxqucwcWuUdvW2Ct2lWgjV0L5B12+Jl2GPsSxa8=; b=LOoTM94lGT26XQEekl8b6xIsYqTyh/uRltb6Kf26GyW25hQieCKcXV0Yuku44jZg/4 8uw2psrrrPwk4FmgkWnNhuEjvCngWnxqer1DiBv0rpcRoK5M4T2zzrJSvjl8/ExYKiYL YSzD00jW3NfJOaYcz03MX2JqdWc+kg5e7BlFi+BHfsRnygokB6Mwn7NH+IvIzSZUwGpM rxxOjN1iOt9zL44P0N9qno9eBhiPPi5lUX/OaK1gr7Gsj5cXT+9PGgxKrsQ+uEacoMEa bU3BXS7Twz32Zai23HFPFuKnYUPZgQJ/Bt55ubmMq0aSW+IsW/M+/ZKla21Cem7VdUa0 Vk0w== X-Gm-Message-State: AOAM532YINjX9FCVAEkb4WDNiIJ5uZBZhxfMejVH1qemawn2CoWknP76 wWzBHYOaQ7w0cgz2QzlyFDkUAB7wclyMn04+ X-Google-Smtp-Source: ABdhPJxXqbUIsbhmuVWPaYutBUkLTP8rHCDIwPSwYhPxteSMA59GxOuWwZrzqR5TXP0/hEcL/PxfjQ== X-Received: by 2002:a17:90b:3903:b0:1d2:c8ea:4c9c with SMTP id ob3-20020a17090b390300b001d2c8ea4c9cmr3143436pjb.210.1650600281948; Thu, 21 Apr 2022 21:04:41 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v3] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values Date: Fri, 22 Apr 2022 12:04:34 +0800 Message-Id: <20220422040436.2233-1-frank.chang@sifive.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Jim Shu , Alistair Francis , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650600364091100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang Allow user to set core's marchid, mvendorid, mipid CSRs through -cpu command line option. The default values of marchid and mipid are built with QEMU's version numbers. Signed-off-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 9 +++++++++ target/riscv/cpu.h | 4 ++++ target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++---- 3 files changed, 47 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0c774056c5..ace68ed855 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,6 +34,11 @@ =20 /* RISC-V CPU definitions */ =20 +#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ + (QEMU_VERSION_MINOR << 8) | \ + (QEMU_VERSION_MICRO)) +#define RISCV_CPU_MIPID RISCV_CPU_MARCHID + static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; =20 struct isa_ext_data { @@ -810,6 +815,10 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 + DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), + DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID= ), + DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID), + DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 34c22d5d3b..46c66fbf8e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -393,6 +393,10 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; =20 + uint32_t mvendorid; + uint64_t marchid; + uint64_t mipid; + /* Vendor-specific custom extensions */ bool ext_XVentanaCondOps; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6ba85e7b5d..1c2d3f7193 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -612,6 +612,36 @@ static RISCVException write_ignore(CPURISCVState *env,= int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mvendorid(CPURISCVState *env, int csrno, + target_ulong *val) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + *val =3D cpu->cfg.mvendorid; + return RISCV_EXCP_NONE; +} + +static RISCVException read_marchid(CPURISCVState *env, int csrno, + target_ulong *val) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + *val =3D cpu->cfg.marchid; + return RISCV_EXCP_NONE; +} + +static RISCVException read_mipid(CPURISCVState *env, int csrno, + target_ulong *val) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + *val =3D cpu->cfg.mipid; + return RISCV_EXCP_NONE; +} + static RISCVException read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) { @@ -3260,10 +3290,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MINSTRETH] =3D { "minstreth", any32, read_instreth }, =20 /* Machine Information Registers */ - [CSR_MVENDORID] =3D { "mvendorid", any, read_zero }, - [CSR_MARCHID] =3D { "marchid", any, read_zero }, - [CSR_MIMPID] =3D { "mimpid", any, read_zero }, - [CSR_MHARTID] =3D { "mhartid", any, read_mhartid }, + [CSR_MVENDORID] =3D { "mvendorid", any, read_mvendorid }, + [CSR_MARCHID] =3D { "marchid", any, read_marchid }, + [CSR_MIMPID] =3D { "mimpid", any, read_mipid }, + [CSR_MHARTID] =3D { "mhartid", any, read_mhartid }, =20 [CSR_MCONFIGPTR] =3D { "mconfigptr", any, read_zero, .min_priv_ver =3D PRIV_VERSION_1_1= 2_0 }, --=20 2.35.1