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[2a09:80c0:38::1092]) by smtp.googlemail.com with ESMTPSA id 3-20020a5d47a3000000b0020aa79d55b5sm19071560wrb.35.2022.04.28.04.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 04:32:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Bfbc8Hiy9yEGQ64oseWOsvJ/Y0B8UdcjSFOpcy2VPOI=; b=aMlvXcDQ5ETStW+x5Bqvn1BqBcffwyexgQwzWlIqyTIwmZDTVaQkj+9zYDhIyei2Wa PWRgJ8rvn1EBGZoqL7cNVWhhTpro4q6vzUSxbAgHswSZwhwpzbbxr4gnjYwBe9HVOEdX /WtGfMcwtw3Rt9qG7BMR6zInnw571SuX4L+vICd5Y1kgnX7mn+Moj5cRJarAw0hknJiQ rIz9jN93+PRwPcAEVaZWPjuh+bVZ9sj86QDlIuQiQh3YteYaI5GqV2zY5KPOgrceL9Dv OwYQgen4C+sWpBKp1i/X1VH2a/cxEAs6isUIbZh9z6GQocPSsLqEhjZcLpbOyoYUkFmc fg3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Bfbc8Hiy9yEGQ64oseWOsvJ/Y0B8UdcjSFOpcy2VPOI=; b=ezVRUKfWOHww4qJK7nFUryNke+dQdlQKejLcLRc5y62P9OrYLyakv13/p5aX9C1tEc WKEqRTFlPN8d3EVqLfWBH3ralUJnvttNHefgTXuPwhB7wPFLcKQ/6yDErny26DygYUNn nFwBs/EHIvIZ91WIcGkJoTDQ48L+1YG5N4f7sGxKGVAOHuuicgBsU5b8Erh2JgnsLkZo Bc4UjYKPzQXNc8/JWTLsQ9T9yf9ZiMWi28RdAiUDqqeTm2y0dnt8xuOgPlEuvK7MOXDr 3G0QtEP5gd2cGVstc6s5kOyIw9WJwq2v2NSLF7s0cACCso/PO+ZH44LoiBNlB4IRpD8X GQmQ== X-Gm-Message-State: AOAM530ez8C1wSF06f+fei3WGj780tSu4sn64Z3en23SDVxvQM6t8Mjh 5NRoNNorse1CdZaQRlIdXSs= X-Google-Smtp-Source: ABdhPJwHFBPd7YZwrPw95gh7uAgxVDM3ZVlkA68x9ADzgwxCGbmE66/EhHh+MghNm4U1EJRSCmx6pA== X-Received: by 2002:a5d:648a:0:b0:20a:e3ab:4350 with SMTP id o10-20020a5d648a000000b0020ae3ab4350mr11536623wri.130.1651145580411; Thu, 28 Apr 2022 04:33:00 -0700 (PDT) From: Redha Gouicem To: Richard Henderson , Peter Maydell , Michael Rolnik , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Bin Meng , David Hildenbrand , Cornelia Huck , Thomas Huth , Max Filippov Subject: [PATCH] tcg: fix guest memory ordering enforcement Date: Thu, 28 Apr 2022 13:32:35 +0200 Message-Id: <20220428113234.37953-1-redha.gouicem@gmail.com> X-Mailer: git-send-email 2.36.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=redha.gouicem@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 28 Apr 2022 09:19:48 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Redha Gouicem , qemu-devel@nongnu.org, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651152093696100001 Content-Type: text/plain; charset="utf-8" This commit allows memory ordering enforcement to be performed more precisely. The previous scheme with fences always inserted before the memory access made it impossible to correctly enforce the x86 model on weakly orde= red architectures such as arm. With this change, the memory models of guests ca= n be defined more precisely, with a fence before and a fence after the access. T= his allows for a precise mapping of the ordering, that relies less on what type= of fences the host architecture provides. Signed-off-by: Redha Gouicem --- target/alpha/cpu.h | 4 ++++ target/arm/cpu.h | 4 ++++ target/avr/cpu.h | 4 ++++ target/hppa/cpu.h | 4 ++++ target/i386/cpu.h | 4 ++++ target/mips/cpu.h | 4 ++++ target/ppc/cpu.h | 4 ++++ target/riscv/cpu.h | 4 ++++ target/s390x/cpu.h | 4 ++++ target/xtensa/cpu.h | 4 ++++ tcg/tcg-op.c | 19 ++++++++++++------- 11 files changed, 52 insertions(+), 7 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index d0abc949a8..00220c66c8 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -26,6 +26,10 @@ =20 /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) +#define TCG_GUEST_MO_BEF_LD (0) +#define TCG_GUEST_MO_AFT_LD (0) +#define TCG_GUEST_MO_BEF_ST (0) +#define TCG_GUEST_MO_AFT_ST (0) =20 #define ICACHE_LINE_SIZE 32 #define DCACHE_LINE_SIZE 32 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index db8ff04449..ec1407dc43 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -29,6 +29,10 @@ =20 /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) +#define TCG_GUEST_MO_BEF_LD (0) +#define TCG_GUEST_MO_AFT_LD (0) +#define TCG_GUEST_MO_BEF_ST (0) +#define TCG_GUEST_MO_AFT_ST (0) =20 #ifdef TARGET_AARCH64 #define KVM_HAVE_MCE_INJECTION 1 diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 55497f851d..adcab7c88b 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -33,6 +33,10 @@ #define CPU_RESOLVING_TYPE TYPE_AVR_CPU =20 #define TCG_GUEST_DEFAULT_MO 0 +#define TCG_GUEST_MO_BEF_LD 0 +#define TCG_GUEST_MO_AFT_LD 0 +#define TCG_GUEST_MO_BEF_ST 0 +#define TCG_GUEST_MO_AFT_ST 0 =20 /* * AVR has two memory spaces, data & code. diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6f3b6beecf..a1236548cf 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -29,6 +29,10 @@ a weak memory model, but with TLB bits that force ordering on a per-page basis. It's probably easier to fall back to a strong memory model. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL +#define TCG_GUEST_MO_BEF_LD (TCG_MO_LD_LD | TCG_MO_ST_LD) +#define TCG_GUEST_MO_AFT_LD (0) +#define TCG_GUEST_MO_BEF_ST (TCG_MO_ST_ST | TCG_MO_LD_ST) +#define TCG_GUEST_MO_AFT_ST (0) =20 #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 3 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9661f9fbd1..c6a7052d58 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -29,6 +29,10 @@ =20 /* The x86 has a strong memory model with some store-after-load re-orderin= g */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) +#define TCG_GUEST_MO_BEF_LD (0) +#define TCG_GUEST_MO_AFT_LD (TCG_MO_LD_ST | TCG_MO_LD_LD) +#define TCG_GUEST_MO_BEF_ST (TCG_MO_ST_ST) +#define TCG_GUEST_MO_AFT_ST (0) =20 #define KVM_HAVE_MCE_INJECTION 1 =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5335ac10a3..c2c0ca9c4a 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -8,6 +8,10 @@ #include "mips-defs.h" =20 #define TCG_GUEST_DEFAULT_MO (0) +#define TCG_GUEST_MO_BEF_LD (0) +#define TCG_GUEST_MO_AFT_LD (0) +#define TCG_GUEST_MO_BEF_ST (0) +#define TCG_GUEST_MO_AFT_ST (0) =20 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c2b6c987c0..2763ba465a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -27,6 +27,10 @@ #include "qom/object.h" =20 #define TCG_GUEST_DEFAULT_MO 0 +#define TCG_GUEST_MO_BEF_LD 0 +#define TCG_GUEST_MO_AFT_LD 0 +#define TCG_GUEST_MO_BEF_ST 0 +#define TCG_GUEST_MO_AFT_ST 0 =20 #define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 34c22d5d3b..5f3a9dd463 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -29,6 +29,10 @@ #include "cpu_bits.h" =20 #define TCG_GUEST_DEFAULT_MO 0 +#define TCG_GUEST_MO_BEF_LD 0 +#define TCG_GUEST_MO_AFT_LD 0 +#define TCG_GUEST_MO_BEF_ST 0 +#define TCG_GUEST_MO_AFT_ST 0 =20 #define TYPE_RISCV_CPU "riscv-cpu" =20 diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 7d6d01325b..59684809cd 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -34,6 +34,10 @@ =20 /* The z/Architecture has a strong memory model with some store-after-load= re-ordering */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) +#define TCG_GUEST_MO_BEF_LD (0) +#define TCG_GUEST_MO_AFT_LD (TCG_MO_LD_ST | TCG_MO_LD_LD) +#define TCG_GUEST_MO_BEF_ST (TCG_MO_ST_ST) +#define TCG_GUEST_MO_AFT_ST (0) =20 #define TARGET_INSN_START_EXTRA_WORDS 2 =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d4b8268146..29ef6ec5b7 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -35,6 +35,10 @@ =20 /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) +#define TCG_GUEST_MO_BEF_LD (0) +#define TCG_GUEST_MO_AFT_LD (0) +#define TCG_GUEST_MO_BEF_ST (0) +#define TCG_GUEST_MO_AFT_ST (0) =20 enum { /* Additional instructions */ diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 5d48537927..d9b43bc38a 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2834,9 +2834,6 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val,= TCGv addr, =20 static void tcg_gen_req_mo(TCGBar type) { -#ifdef TCG_GUEST_DEFAULT_MO - type &=3D TCG_GUEST_DEFAULT_MO; -#endif type &=3D ~TCG_TARGET_DEFAULT_MO; if (type) { tcg_gen_mb(type | TCG_BAR_SC); @@ -2873,7 +2870,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) MemOp orig_memop; MemOpIdx oi; =20 - tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + tcg_gen_req_mo(TCG_GUEST_MO_BEF_LD); memop =3D tcg_canonicalize_memop(memop, 0, 0); oi =3D make_memop_idx(memop, idx); =20 @@ -2904,6 +2901,8 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) g_assert_not_reached(); } } + + tcg_gen_req_mo(TCG_GUEST_MO_AFT_LD); } =20 void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) @@ -2911,7 +2910,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) TCGv_i32 swap =3D NULL; MemOpIdx oi; =20 - tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + tcg_gen_req_mo(TCG_GUEST_MO_BEF_ST); memop =3D tcg_canonicalize_memop(memop, 0, 1); oi =3D make_memop_idx(memop, idx); =20 @@ -2942,6 +2941,8 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) if (swap) { tcg_temp_free_i32(swap); } + + tcg_gen_req_mo(TCG_GUEST_MO_AFT_ST); } =20 void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) @@ -2959,7 +2960,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) return; } =20 - tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + tcg_gen_req_mo(TCG_GUEST_MO_BEF_LD); memop =3D tcg_canonicalize_memop(memop, 1, 0); oi =3D make_memop_idx(memop, idx); =20 @@ -2994,6 +2995,8 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) g_assert_not_reached(); } } + + tcg_gen_req_mo(TCG_GUEST_MO_AFT_LD); } =20 void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) @@ -3006,7 +3009,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) return; } =20 - tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + tcg_gen_req_mo(TCG_GUEST_MO_BEF_ST); memop =3D tcg_canonicalize_memop(memop, 1, 1); oi =3D make_memop_idx(memop, idx); =20 @@ -3036,6 +3039,8 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) if (swap) { tcg_temp_free_i64(swap); } + + tcg_gen_req_mo(TCG_GUEST_MO_AFT_ST); } =20 static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) --=20 2.36.0