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s=facebook; bh=KC391Ze2nm6dEQKOMd/z/MuerJqxDPcaEuPSZpfPu3w=; b=aGQK9UqTQ1k/snRuaNHJ24Gx+o8YdimVjhJjaL8b8IuBz9UwnWgWGTKk/epGs11HckrU UlGesr6dzObk/AyJKEF9iU3EUkqd/giJMLiJjk/QtK0nOSLTp9afnnsIAJhaReV25PzL z5iBvny6Ad99z0U7nwkDY7buJyLiT4i6FyY= From: Peter Delevoryas To: CC: , , , , , , , , , , Subject: [PATCH 1/2] hw: aspeed: Add missing UART's Date: Thu, 12 May 2022 21:02:19 -0700 Message-ID: <20220513040220.3657135-2-pdel@fb.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220513040220.3657135-1-pdel@fb.com> References: <20220513040220.3657135-1-pdel@fb.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-FB-Internal: Safe X-Proofpoint-GUID: bosZyMAP_kdEh2-BCiXKrVJBnflGMorJ X-Proofpoint-ORIG-GUID: bosZyMAP_kdEh2-BCiXKrVJBnflGMorJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-12_19,2022-05-12_01,2022-02-23_01 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=67.231.145.42; envelope-from=prvs=613212e35b=pdel@fb.com; helo=mx0a-00082601.pphosted.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @fb.com) X-ZM-MESSAGEID: 1652415059979100001 Content-Type: text/plain; charset="utf-8" This adds the missing UART memory and IRQ mappings for the AST2400, AST2500, AST2600, and AST1030. This also includes the new UART interfaces added in the AST2600 and AST1030 from UART6 to UART13. The addresses and interrupt numbers for these two later chips are identical. Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Tested-by: Zev Weiss --- hw/arm/aspeed_ast10x0.c | 24 ++++++++++++++++++++++++ hw/arm/aspeed_ast2600.c | 19 +++++++++++++++++++ hw/arm/aspeed_soc.c | 6 ++++++ include/hw/arm/aspeed_soc.h | 8 ++++++++ 4 files changed, 57 insertions(+) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 4271549282..f65dc139da 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -33,14 +33,38 @@ static const hwaddr aspeed_soc_ast1030_memmap[] =3D { [ASPEED_DEV_SBC] =3D 0x7E6F2000, [ASPEED_DEV_GPIO] =3D 0x7E780000, [ASPEED_DEV_TIMER1] =3D 0x7E782000, + [ASPEED_DEV_UART1] =3D 0x7E783000, + [ASPEED_DEV_UART2] =3D 0x7E78D000, + [ASPEED_DEV_UART3] =3D 0x7E78E000, + [ASPEED_DEV_UART4] =3D 0x7E78F000, [ASPEED_DEV_UART5] =3D 0x7E784000, + [ASPEED_DEV_UART6] =3D 0x7E790000, + [ASPEED_DEV_UART7] =3D 0x7E790100, + [ASPEED_DEV_UART8] =3D 0x7E790200, + [ASPEED_DEV_UART9] =3D 0x7E790300, + [ASPEED_DEV_UART10] =3D 0x7E790400, + [ASPEED_DEV_UART11] =3D 0x7E790500, + [ASPEED_DEV_UART12] =3D 0x7E790600, + [ASPEED_DEV_UART13] =3D 0x7E790700, [ASPEED_DEV_WDT] =3D 0x7E785000, [ASPEED_DEV_LPC] =3D 0x7E789000, [ASPEED_DEV_I2C] =3D 0x7E7B0000, }; =20 static const int aspeed_soc_ast1030_irqmap[] =3D { + [ASPEED_DEV_UART1] =3D 47, + [ASPEED_DEV_UART2] =3D 48, + [ASPEED_DEV_UART3] =3D 49, + [ASPEED_DEV_UART4] =3D 50, [ASPEED_DEV_UART5] =3D 8, + [ASPEED_DEV_UART6] =3D 57, + [ASPEED_DEV_UART7] =3D 58, + [ASPEED_DEV_UART8] =3D 59, + [ASPEED_DEV_UART9] =3D 60, + [ASPEED_DEV_UART10] =3D 61, + [ASPEED_DEV_UART11] =3D 62, + [ASPEED_DEV_UART12] =3D 63, + [ASPEED_DEV_UART13] =3D 64, [ASPEED_DEV_GPIO] =3D 11, [ASPEED_DEV_TIMER1] =3D 16, [ASPEED_DEV_TIMER2] =3D 17, diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index eedda7badc..1b72800682 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -61,7 +61,18 @@ static const hwaddr aspeed_soc_ast2600_memmap[] =3D { [ASPEED_DEV_IBT] =3D 0x1E789140, [ASPEED_DEV_I2C] =3D 0x1E78A000, [ASPEED_DEV_UART1] =3D 0x1E783000, + [ASPEED_DEV_UART2] =3D 0x1E78D000, + [ASPEED_DEV_UART3] =3D 0x1E78E000, + [ASPEED_DEV_UART4] =3D 0x1E78F000, [ASPEED_DEV_UART5] =3D 0x1E784000, + [ASPEED_DEV_UART6] =3D 0x1E790000, + [ASPEED_DEV_UART7] =3D 0x1E790100, + [ASPEED_DEV_UART8] =3D 0x1E790200, + [ASPEED_DEV_UART9] =3D 0x1E790300, + [ASPEED_DEV_UART10] =3D 0x1E790400, + [ASPEED_DEV_UART11] =3D 0x1E790500, + [ASPEED_DEV_UART12] =3D 0x1E790600, + [ASPEED_DEV_UART13] =3D 0x1E790700, [ASPEED_DEV_VUART] =3D 0x1E787000, [ASPEED_DEV_I3C] =3D 0x1E7A0000, [ASPEED_DEV_SDRAM] =3D 0x80000000, @@ -78,6 +89,14 @@ static const int aspeed_soc_ast2600_irqmap[] =3D { [ASPEED_DEV_UART3] =3D 49, [ASPEED_DEV_UART4] =3D 50, [ASPEED_DEV_UART5] =3D 8, + [ASPEED_DEV_UART6] =3D 57, + [ASPEED_DEV_UART7] =3D 58, + [ASPEED_DEV_UART8] =3D 59, + [ASPEED_DEV_UART9] =3D 60, + [ASPEED_DEV_UART10] =3D 61, + [ASPEED_DEV_UART11] =3D 62, + [ASPEED_DEV_UART12] =3D 63, + [ASPEED_DEV_UART13] =3D 64, [ASPEED_DEV_VUART] =3D 8, [ASPEED_DEV_FMC] =3D 39, [ASPEED_DEV_SDMC] =3D 0, diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 58714cb2a0..2cd03d49da 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -48,6 +48,9 @@ static const hwaddr aspeed_soc_ast2400_memmap[] =3D { [ASPEED_DEV_ETH1] =3D 0x1E660000, [ASPEED_DEV_ETH2] =3D 0x1E680000, [ASPEED_DEV_UART1] =3D 0x1E783000, + [ASPEED_DEV_UART2] =3D 0x1E78D000, + [ASPEED_DEV_UART3] =3D 0x1E78E000, + [ASPEED_DEV_UART4] =3D 0x1E78F000, [ASPEED_DEV_UART5] =3D 0x1E784000, [ASPEED_DEV_VUART] =3D 0x1E787000, [ASPEED_DEV_SDRAM] =3D 0x40000000, @@ -80,6 +83,9 @@ static const hwaddr aspeed_soc_ast2500_memmap[] =3D { [ASPEED_DEV_ETH1] =3D 0x1E660000, [ASPEED_DEV_ETH2] =3D 0x1E680000, [ASPEED_DEV_UART1] =3D 0x1E783000, + [ASPEED_DEV_UART2] =3D 0x1E78D000, + [ASPEED_DEV_UART3] =3D 0x1E78E000, + [ASPEED_DEV_UART4] =3D 0x1E78F000, [ASPEED_DEV_UART5] =3D 0x1E784000, [ASPEED_DEV_VUART] =3D 0x1E787000, [ASPEED_DEV_SDRAM] =3D 0x80000000, diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index e13af374b9..3f7f815275 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -104,6 +104,14 @@ enum { ASPEED_DEV_UART3, ASPEED_DEV_UART4, ASPEED_DEV_UART5, + ASPEED_DEV_UART6, + ASPEED_DEV_UART7, + ASPEED_DEV_UART8, + ASPEED_DEV_UART9, + ASPEED_DEV_UART10, + ASPEED_DEV_UART11, + ASPEED_DEV_UART12, + ASPEED_DEV_UART13, ASPEED_DEV_VUART, ASPEED_DEV_FMC, ASPEED_DEV_SPI1, --=20 2.30.2 From nobody Fri Apr 19 00:55:15 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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s=facebook; bh=unxFmsA21oO88hQqz1WTAO4u7MbdUrcf6MsuDEBoRA8=; b=E9GA4CCrHcLIOEdbwMe7xFGCI+4qCei0QvMo+iG1hNuQExupItMRVsXyo8C1leTd2a+w 168NbHtUYAndVjD+Lmfrp6mYjOGLESeutQ+DLUIpqF7ERf23xE93boplo7TsrYcB1NaQ EoAHu4uvbFCK7lSjyVsnWzQgIW9O6ALoXpY= From: Peter Delevoryas To: CC: , , , , , , , , , , Subject: [PATCH 2/2] hw: aspeed: Init all UART's with serial devices Date: Thu, 12 May 2022 21:02:20 -0700 Message-ID: <20220513040220.3657135-3-pdel@fb.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220513040220.3657135-1-pdel@fb.com> References: <20220513040220.3657135-1-pdel@fb.com> X-FB-Internal: Safe X-Proofpoint-GUID: RP7Y77_k3BBWPKVkmmQ1Kd-fswIcHSpv X-Proofpoint-ORIG-GUID: RP7Y77_k3BBWPKVkmmQ1Kd-fswIcHSpv Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-12_19,2022-05-12_01,2022-02-23_01 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=67.231.145.42; envelope-from=prvs=613212e35b=pdel@fb.com; helo=mx0a-00082601.pphosted.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @fb.com) X-ZM-MESSAGEID: 1652414897626100002 Content-Type: text/plain; charset="utf-8" Usually, QEMU users just provide one serial device on the command line, either through "-nographic" or "-serial stdio -display none", or just using VNC and popping up a window. We try to match what the user expects, which is to connect the first (and usually only) serial device to the UART a board is using as serial0. Most Aspeed machines in hw/arm/aspeed.c use UART5 for serial0 in their device tree, so we connect UART5 to the first serial device. Some machines use UART1 though, or UART3, so the uart_default property lets us specify that in a board definition. In order to specify a nonstandard serial0 UART, a user basically *must* add a new board definition in hw/arm/aspeed.c. There's no way to do this without recompiling QEMU, besides constructing the machine completely from scratch on the command line. To provide more flexibility, we can also support the user specifying more serial devices, and connect them to the UART memory regions if possible. Even if a user doesn't specify any extra serial devices, it's useful to initialize these memory regions as UART's, so that they respond to the guest OS more naturally. At the moment, they will just always return zero's for everything, and some UART registers have a default non-zero state. With this change, if a new OpenBMC image uses UART3 or some other nonstandard UART for serial0, you can still use it with the EVB without recompiling QEMU, even though uart-default=3DUART5 for the EVB. For example, Facebook's Wedge100 BMC uses UART3: you can fetch an image from Github[1] and get the serial console output even while running the palmetto machine type, because we explicitly specify that we want UART3 to be connected to stdio. qemu-system-arm -machine palmetto-bmc \ -drive file=3Dwedge100.mtd,format=3Draw,if=3Dmtd \ -serial null -serial null -serial null -serial stdio -display none Similarly, you can boot a Fuji BMC image[2], which uses UART1, using the AST2600 EVB machine: qemu-system-arm -machine ast2600-evb \ -drive file=3Dfuji.mtd,format=3Draw,if=3Dmtd \ -serial null -serial stdio -display none This is kind of complicated, of course: it might be more natural to get rid of the uart_default attribute completely, and initialize UART's sequentially. But, keeping backward compatibility and the way most users know how to use QEMU in mind, this seems to make the most sense. [1] https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge1= 00.mtd [2] https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.m= td Signed-off-by: Peter Delevoryas Tested-by: Zev Weiss --- hw/arm/aspeed_ast10x0.c | 14 +++++++++++--- hw/arm/aspeed_ast2600.c | 10 +++++++++- hw/arm/aspeed_soc.c | 10 +++++++++- 3 files changed, 29 insertions(+), 5 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index f65dc139da..5e6f3a8fed 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -215,10 +215,18 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); =20 - /* UART5 - attach an 8250 to the IO space as our UART */ - serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2, - aspeed_soc_get_irq(s, ASPEED_DEV_UART5), + /* UART - attach 8250's to the IO space for each UART */ + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, + aspeed_soc_get_irq(s, s->uart_default), 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); + for (int i =3D 1, uart =3D ASPEED_DEV_UART1; i < 13; i++, uart++) { + if (uart =3D=3D s->uart_default) { + uart++; + } + serial_mm_init(get_system_memory(), sc->memmap[uart], 2, + aspeed_soc_get_irq(s, uart), 38400, serial_hd(i), + DEVICE_LITTLE_ENDIAN); + } =20 /* Timer */ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 1b72800682..cbeca7f655 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -372,10 +372,18 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 - /* UART - attach an 8250 to the IO space as our UART */ + /* UART - attach 8250's to the IO space for each UART */ serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, aspeed_soc_get_irq(s, s->uart_default), 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); + for (int i =3D 1, uart =3D ASPEED_DEV_UART1; i < 13; i++, uart++) { + if (uart =3D=3D s->uart_default) { + uart++; + } + serial_mm_init(get_system_memory(), sc->memmap[uart], 2, + aspeed_soc_get_irq(s, uart), 38400, serial_hd(i), + DEVICE_LITTLE_ENDIAN); + } =20 /* I2C */ object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 2cd03d49da..1fc1ed808d 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -303,10 +303,18 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 - /* UART - attach an 8250 to the IO space as our UART */ + /* UART - attach 8250's to the IO space for each UART */ serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, aspeed_soc_get_irq(s, s->uart_default), 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); + for (int i =3D 1, uart =3D ASPEED_DEV_UART1; i < 5; i++, uart++) { + if (uart =3D=3D s->uart_default) { + uart++; + } + serial_mm_init(get_system_memory(), sc->memmap[uart], 2, + aspeed_soc_get_irq(s, uart), 38400, serial_hd(i), + DEVICE_LITTLE_ENDIAN); + } =20 /* I2C */ object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), --=20 2.30.2