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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=mchitale@ventanamicro.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1652432127611100003 Content-Type: text/plain; charset="utf-8" Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 4 + target/riscv/cpu_bits.h | 36 +++++++ target/riscv/csr.c | 210 ++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 21 ++++ 5 files changed, 273 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 25a4ba3e22..3be2c644f9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -870,6 +870,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), =20 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), @@ -1062,6 +1063,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char = **isa_str, int max_str_len) ISA_EDATA_ENTRY(svinval, ext_svinval), ISA_EDATA_ENTRY(svnapot, ext_svnapot), ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), + ISA_EDATA_ENTRY(smstateen, ext_smstateen), }; =20 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a55c918274..d6fdc63ff2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -327,6 +327,9 @@ struct CPUArchState { =20 /* CSRs for execution enviornment configuration */ uint64_t menvcfg; + uint64_t mstateen[SMSTATEEN_MAX_COUNT]; + uint64_t hstateen[SMSTATEEN_MAX_COUNT]; + uint64_t sstateen[SMSTATEEN_MAX_COUNT]; target_ulong senvcfg; uint64_t henvcfg; #endif @@ -411,6 +414,7 @@ struct RISCVCPUConfig { bool ext_zhinxmin; bool ext_zve32f; bool ext_zve64f; + bool ext_smstateen; =20 uint32_t mvendorid; uint64_t marchid; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4a55c6a709..2a3ef26d21 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -208,6 +208,12 @@ /* Supervisor Configuration CSRs */ #define CSR_SENVCFG 0x10A =20 +/* Supervisor state CSRs */ +#define CSR_SSTATEEN0 0x10C +#define CSR_SSTATEEN1 0x10D +#define CSR_SSTATEEN2 0x10E +#define CSR_SSTATEEN3 0x10F + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -257,6 +263,16 @@ #define CSR_HENVCFG 0x60A #define CSR_HENVCFGH 0x61A =20 +/* Hypervisor state CSRs */ +#define CSR_HSTATEEN0 0x60C +#define CSR_HSTATEEN0H 0x61C +#define CSR_HSTATEEN1 0x60D +#define CSR_HSTATEEN1H 0x61D +#define CSR_HSTATEEN2 0x60E +#define CSR_HSTATEEN2H 0x61E +#define CSR_HSTATEEN3 0x60F +#define CSR_HSTATEEN3H 0x61F + /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 @@ -304,6 +320,26 @@ #define CSR_MENVCFG 0x30A #define CSR_MENVCFGH 0x31A =20 +/* Machine state CSRs */ +#define CSR_MSTATEEN0 0x30C +#define CSR_MSTATEEN0H 0x31C +#define CSR_MSTATEEN1 0x30D +#define CSR_MSTATEEN1H 0x31D +#define CSR_MSTATEEN2 0x30E +#define CSR_MSTATEEN2H 0x31E +#define CSR_MSTATEEN3 0x30F +#define CSR_MSTATEEN3H 0x31F + +/* Common defines for all smstateen */ +#define SMSTATEEN_MAX_COUNT 4 +#define SMSTATEEN0_CS 0 +#define SMSTATEEN0_FCSR 0 +#define SMSTATEEN0_IMSIC 58 +#define SMSTATEEN0_AIA 59 +#define SMSTATEEN0_SVSLCT 60 +#define SMSTATEEN0_HSENVCFG 62 +#define SMSTATEEN_STATEN 63 + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e144ce7135..fea5cdd178 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -247,6 +247,42 @@ static RISCVException hmode32(CPURISCVState *env, int = csrno) =20 } =20 +static RISCVException mstateen(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return any(env, csrno); +} + +static RISCVException hstateen(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + +static RISCVException sstateen(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode(env, csrno); +} + /* Checks if PointerMasking registers could be accessed */ static RISCVException pointer_masking(CPURISCVState *env, int csrno) { @@ -1574,6 +1610,129 @@ static RISCVException write_henvcfgh(CPURISCVState = *env, int csrno, return RISCV_EXCP_NONE; } =20 +static inline void write_smstateen(CPURISCVState *env, uint64_t *reg, + uint64_t wr_mask, uint64_t new_val) +{ + *reg =3D (*reg & ~wr_mask) | (new_val & wr_mask); +} + +static RISCVException read_mstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mstateen[csrno - CSR_MSTATEEN0]; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateen(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t *reg; + uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; + + reg =3D &env->mstateen[csrno - CSR_MSTATEEN0]; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_mstateenh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateenh(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t *reg; + uint64_t val; + uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; + + reg =3D &env->mstateen[csrno - CSR_MSTATEEN0H]; + val =3D (uint64_t)new_val << 32; + val |=3D *reg & 0xFFFFFFFF; + write_smstateen(env, reg, wr_mask, val); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_hstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->hstateen[csrno - CSR_HSTATEEN0]; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateen(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t *reg; + uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; + int index =3D csrno - CSR_HSTATEEN0; + + reg =3D &env->hstateen[index]; + wr_mask &=3D env->mstateen[index]; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_hstateenh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->hstateen[csrno - CSR_HSTATEEN0H] >> 32; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateenh(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t *reg; + uint64_t val; + uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; + int index =3D csrno - CSR_HSTATEEN0H; + + reg =3D &env->hstateen[index]; + val =3D (uint64_t)new_val << 32; + val |=3D *reg & 0xFFFFFFFF; + wr_mask &=3D env->mstateen[index]; + + write_smstateen(env, reg, wr_mask, val); + return RISCV_EXCP_NONE; +} + +static RISCVException read_sstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->sstateen[csrno - CSR_SSTATEEN0]; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_sstateen(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t *reg; + uint64_t wr_mask =3D 0; + int index =3D csrno - CSR_SSTATEEN0; + bool virt =3D riscv_cpu_virt_enabled(env); + + reg =3D &env->sstateen[index]; + if (virt) { + wr_mask &=3D env->mstateen[index]; + } else { + wr_mask &=3D env->hstateen[index]; + } + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + static RISCVException rmw_mip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -3441,6 +3600,57 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HENVCFGH] =3D { "henvcfgh", hmode32, read_henvcfgh, write_henvcfg= h, .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, =20 + /* Smstateen extension CSRs */ + [CSR_MSTATEEN0] =3D { "mstateen0", mstateen, read_mstateen, write_msta= teen, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN0H] =3D { "mstateen0h", mstateen, read_mstateenh, + write_mstateenh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN1] =3D { "mstateen1", mstateen, read_mstateen, write_msta= teen, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN1H] =3D { "mstateen1h", mstateen, read_mstateenh, + write_mstateenh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN2] =3D { "mstateen2", mstateen, read_mstateen, write_msta= teen, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN2H] =3D { "mstateen2h", mstateen, read_mstateenh, + write_mstateenh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN3] =3D { "mstateen3", mstateen, read_mstateen, write_msta= teen, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN3H] =3D { "mstateen3h", mstateen, read_mstateenh, + write_mstateenh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + + [CSR_HSTATEEN0] =3D { "hstateen0", hstateen, read_hstateen, write_hsta= teen, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN0H] =3D { "hstateen0h", hstateen, read_hstateenh, + write_hstateenh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN1] =3D { "hstateen1", hstateen, read_hstateen, write_hsta= teen, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN1H] =3D { "hstateen1h", hstateen, read_hstateenh, + write_hstateenh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN2] =3D { "hstateen2", hstateen, read_hstateen, write_hsta= teen, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN2H] =3D { "hstateen2h", hstateen, read_hstateenh, + write_hstateenh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN3] =3D { "hstateen3", hstateen, read_hstateen, write_hsta= teen, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN3H] =3D { "hstateen3h", hstateen, read_hstateenh, + write_hstateenh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + + [CSR_SSTATEEN0] =3D { "sstateen0", sstateen, read_sstateen, write_ssta= teen, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN1] =3D { "sstateen1", sstateen, read_sstateen, write_ssta= teen, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN2] =3D { "sstateen2", sstateen, read_sstateen, write_ssta= teen, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN3] =3D { "sstateen3", sstateen, read_sstateen, write_ssta= teen, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 2a437b29a1..84a75dbb08 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -262,6 +262,26 @@ static int riscv_cpu_post_load(void *opaque, int versi= on_id) return 0; } =20 +static bool smstateen_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + + return cpu->cfg.ext_smstateen; +} + +static const VMStateDescription vmstate_smstateen =3D { + .name =3D "cpu/smtateen", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D smstateen_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4), + VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4), + VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4), + VMSTATE_END_OF_LIST() + } +}; + static bool envcfg_needed(void *opaque) { RISCVCPU *cpu =3D opaque; @@ -347,6 +367,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_kvmtimer, &vmstate_envcfg, &vmstate_debug, + &vmstate_smstateen, NULL } }; --=20 2.25.1 From nobody Wed Apr 24 20:46:24 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; 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Fri, 13 May 2022 01:51:45 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Mayuresh Chitale , alistair.francis@wdc.com Subject: [RFC PATCH v4 2/4] target/riscv: smstateen check for h/senvcfg Date: Fri, 13 May 2022 14:21:23 +0530 Message-Id: <20220513085125.403037-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220513085125.403037-1-mchitale@ventanamicro.com> References: <20220513085125.403037-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=mchitale@ventanamicro.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1652432391825100001 Content-Type: text/plain; charset="utf-8" Accesses to henvcfg, henvcfgh and senvcfg are allowed only if corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 84 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 78 insertions(+), 6 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fea5cdd178..d4920b3fa4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -39,6 +39,37 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *= ops) } =20 /* Predicates */ +static RISCVException smstateen_acc_ok(CPURISCVState *env, int mode, int b= it) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + bool virt =3D riscv_cpu_virt_enabled(env); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_NONE; + } + +#if !defined(CONFIG_USER_ONLY) + if (!(env->mstateen[0] & 1UL << bit)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (virt) { + if (!(env->hstateen[0] & 1UL << bit)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + } + + if (mode =3D=3D PRV_U) { + if (!(env->sstateen[0] & 1UL << bit)) { + return RISCV_EXCP_ILLEGAL_INST; + } + } +#endif + + return RISCV_EXCP_NONE; +} + static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -1557,6 +1588,13 @@ static RISCVException write_menvcfgh(CPURISCVState *= env, int csrno, static RISCVException read_senvcfg(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->senvcfg; return RISCV_EXCP_NONE; } @@ -1565,15 +1603,27 @@ static RISCVException write_senvcfg(CPURISCVState *= env, int csrno, target_ulong val) { uint64_t mask =3D SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCF= G_CBZE; + RISCVException ret; =20 - env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 + env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); return RISCV_EXCP_NONE; } =20 static RISCVException read_henvcfg(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->henvcfg; return RISCV_EXCP_NONE; } @@ -1582,6 +1632,12 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, target_ulong val) { uint64_t mask =3D HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCF= G_CBZE; + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D HENVCFG_PBMTE | HENVCFG_STCE; @@ -1595,6 +1651,13 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->henvcfg >> 32; return RISCV_EXCP_NONE; } @@ -1604,9 +1667,14 @@ static RISCVException write_henvcfgh(CPURISCVState *= env, int csrno, { uint64_t mask =3D HENVCFG_PBMTE | HENVCFG_STCE; uint64_t valh =3D (uint64_t)val << 32; + RISCVException ret; =20 - env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 + env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); return RISCV_EXCP_NONE; } =20 @@ -1628,7 +1696,8 @@ static RISCVException write_mstateen(CPURISCVState *e= nv, int csrno, target_ulong new_val) { uint64_t *reg; - uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; + uint64_t wr_mask =3D (1UL << SMSTATEEN_STATEN) | + (1UL << SMSTATEEN0_HSENVCFG); =20 reg =3D &env->mstateen[csrno - CSR_MSTATEEN0]; write_smstateen(env, reg, wr_mask, new_val); @@ -1649,7 +1718,8 @@ static RISCVException write_mstateenh(CPURISCVState *= env, int csrno, { uint64_t *reg; uint64_t val; - uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; + uint64_t wr_mask =3D (1UL << SMSTATEEN_STATEN) | + (1UL << SMSTATEEN0_HSENVCFG); =20 reg =3D &env->mstateen[csrno - CSR_MSTATEEN0H]; val =3D (uint64_t)new_val << 32; @@ -1671,7 +1741,8 @@ static RISCVException write_hstateen(CPURISCVState *e= nv, int csrno, target_ulong new_val) { uint64_t *reg; - uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; + uint64_t wr_mask =3D (1UL << SMSTATEEN_STATEN) | + (1UL << SMSTATEEN0_HSENVCFG); int index =3D csrno - CSR_HSTATEEN0; =20 reg =3D &env->hstateen[index]; @@ -1694,8 +1765,9 @@ static RISCVException write_hstateenh(CPURISCVState *= env, int csrno, { uint64_t *reg; uint64_t val; - uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; int index =3D csrno - CSR_HSTATEEN0H; + uint64_t wr_mask =3D (1UL << SMSTATEEN_STATEN) | + (1UL << SMSTATEEN0_HSENVCFG); =20 reg =3D &env->hstateen[index]; val =3D (uint64_t)new_val << 32; --=20 2.25.1 From nobody Wed Apr 24 20:46:24 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; 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Fri, 13 May 2022 01:51:49 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Mayuresh Chitale , alistair.francis@wdc.com Subject: [RFC PATCH v4 3/4] target/riscv: smstateen check for fcsr Date: Fri, 13 May 2022 14:21:24 +0530 Message-Id: <20220513085125.403037-4-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220513085125.403037-1-mchitale@ventanamicro.com> References: <20220513085125.403037-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=mchitale@ventanamicro.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1652432131634100001 Content-Type: text/plain; charset="utf-8" If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d4920b3fa4..5032e48517 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -77,6 +77,10 @@ static RISCVException fs(CPURISCVState *env, int csrno) !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { return RISCV_EXCP_ILLEGAL_INST; } + + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { + return smstateen_acc_ok(env, PRV_U, SMSTATEEN0_FCSR); + } #endif return RISCV_EXCP_NONE; } @@ -1700,6 +1704,10 @@ static RISCVException write_mstateen(CPURISCVState *= env, int csrno, (1UL << SMSTATEEN0_HSENVCFG); =20 reg =3D &env->mstateen[csrno - CSR_MSTATEEN0]; + if (riscv_has_ext(env, RVF)) { + wr_mask |=3D 1UL << SMSTATEEN0_FCSR; + } + write_smstateen(env, reg, wr_mask, new_val); =20 return RISCV_EXCP_NONE; @@ -1724,6 +1732,10 @@ static RISCVException write_mstateenh(CPURISCVState = *env, int csrno, reg =3D &env->mstateen[csrno - CSR_MSTATEEN0H]; val =3D (uint64_t)new_val << 32; val |=3D *reg & 0xFFFFFFFF; + if (riscv_has_ext(env, RVF)) { + wr_mask |=3D 1UL << SMSTATEEN0_FCSR; + } + write_smstateen(env, reg, wr_mask, val); =20 return RISCV_EXCP_NONE; @@ -1745,6 +1757,10 @@ static RISCVException write_hstateen(CPURISCVState *= env, int csrno, (1UL << SMSTATEEN0_HSENVCFG); int index =3D csrno - CSR_HSTATEEN0; =20 + if (riscv_has_ext(env, RVF)) { + wr_mask |=3D 1UL << SMSTATEEN0_FCSR; + } + reg =3D &env->hstateen[index]; wr_mask &=3D env->mstateen[index]; write_smstateen(env, reg, wr_mask, new_val); @@ -1769,6 +1785,10 @@ static RISCVException write_hstateenh(CPURISCVState = *env, int csrno, uint64_t wr_mask =3D (1UL << SMSTATEEN_STATEN) | (1UL << SMSTATEEN0_HSENVCFG); =20 + if (riscv_has_ext(env, RVF)) { + wr_mask |=3D 1UL << SMSTATEEN0_FCSR; + } + reg =3D &env->hstateen[index]; val =3D (uint64_t)new_val << 32; val |=3D *reg & 0xFFFFFFFF; @@ -1794,6 +1814,10 @@ static RISCVException write_sstateen(CPURISCVState *= env, int csrno, int index =3D csrno - CSR_SSTATEEN0; bool virt =3D riscv_cpu_virt_enabled(env); =20 + if (riscv_has_ext(env, RVF)) { + wr_mask |=3D 1UL << SMSTATEEN0_FCSR; + } + reg =3D &env->sstateen[index]; if (virt) { wr_mask &=3D env->mstateen[index]; --=20 2.25.1 From nobody Wed Apr 24 20:46:24 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1652432402; cv=none; d=zohomail.com; s=zohoarc; b=hnYxTA+CI2qqhQAFyDtqZCtaqiYD7Yc8vzkBlCFf65Rixpfb18zL10ZQA8V1JoYWVCw1S+NtUqeqUqNgzgrskITbFxgVJ5iIgze21Hc3cRvNTirNzl+blJMC0AAtbIV8WJ3s/+H/V5db+MszyNDel1ktB57YaLkwE/zQmCuCD+8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652432402; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=mchitale@ventanamicro.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1652432403671100001 Content-Type: text/plain; charset="utf-8" If smstateen is implemented then accesses to AIA registers CSRS, IMSIC CSRs and other IMSIC registers is controlled by setting of corresponding bits in mstateen/hstateen registers. Otherwise an illegal instruction trap or virtual instruction trap is generated. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 253 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 248 insertions(+), 5 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5032e48517..e73b93cd12 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -39,6 +39,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *o= ps) } =20 /* Predicates */ +#if !defined(CONFIG_USER_ONLY) static RISCVException smstateen_acc_ok(CPURISCVState *env, int mode, int b= it) { CPUState *cs =3D env_cpu(env); @@ -49,7 +50,6 @@ static RISCVException smstateen_acc_ok(CPURISCVState *env= , int mode, int bit) return RISCV_EXCP_NONE; } =20 -#if !defined(CONFIG_USER_ONLY) if (!(env->mstateen[0] & 1UL << bit)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -65,11 +65,57 @@ static RISCVException smstateen_acc_ok(CPURISCVState *e= nv, int mode, int bit) return RISCV_EXCP_ILLEGAL_INST; } } -#endif - return RISCV_EXCP_NONE; } =20 +static RISCVException smstateen_aia_acc_ok(CPURISCVState *env, int csrno) +{ + int bit, mode; + + switch (csrno) { + case CSR_SSETEIPNUM: + case CSR_SCLREIPNUM: + case CSR_SSETEIENUM: + case CSR_SCLREIENUM: + case CSR_STOPEI: + case CSR_VSSETEIPNUM: + case CSR_VSCLREIPNUM: + case CSR_VSSETEIENUM: + case CSR_VSCLREIENUM: + case CSR_VSTOPEI: + case CSR_HSTATUS: + mode =3D PRV_S; + bit =3D SMSTATEEN0_IMSIC; + break; + + case CSR_SIEH: + case CSR_SIPH: + case CSR_HVIPH: + case CSR_HVICTL: + case CSR_HVIPRIO1: + case CSR_HVIPRIO2: + case CSR_HVIPRIO1H: + case CSR_HVIPRIO2H: + case CSR_VSIEH: + case CSR_VSIPH: + mode =3D PRV_S; + bit =3D SMSTATEEN0_AIA; + break; + + case CSR_SISELECT: + case CSR_VSISELECT: + mode =3D PRV_S; + bit =3D SMSTATEEN0_SVSLCT; + break; + + default: + return RISCV_EXCP_NONE; + } + + return smstateen_acc_ok(env, mode, bit); +} +#endif + static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -1130,6 +1176,13 @@ static int rmw_xiselect(CPURISCVState *env, int csrn= o, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { target_ulong *iselect; + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -1212,7 +1265,9 @@ static int rmw_xireg(CPURISCVState *env, int csrno, t= arget_ulong *val, bool virt; uint8_t *iprio; int ret =3D -EINVAL; - target_ulong priv, isel, vgein; + target_ulong priv, isel, vgein =3D 0; + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -1241,11 +1296,20 @@ static int rmw_xireg(CPURISCVState *env, int csrno,= target_ulong *val, }; =20 /* Find the selected guest interrupt file */ - vgein =3D (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; + if (virt) { + if (!cpu->cfg.ext_smstateen || + (env->hstateen[0] & 1UL << SMSTATEEN0_IMSIC)) { + vgein =3D get_field(env->hstatus, HSTATUS_VGEIN); + } + } =20 if (ISELECT_IPRIO0 <=3D isel && isel <=3D ISELECT_IPRIO15) { /* Local interrupt priority registers not available for VS-mode */ if (!virt) { + if (priv =3D=3D PRV_S && cpu->cfg.ext_smstateen && + !(env->hstateen[0] & 1UL << SMSTATEEN0_AIA)) { + goto done; + } ret =3D rmw_iprio(riscv_cpu_mxl_bits(env), isel, iprio, val, new_val, wr_mask, (priv =3D=3D PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); @@ -1279,6 +1343,13 @@ static int rmw_xsetclreinum(CPURISCVState *env, int = csrno, target_ulong *val, int ret =3D -EINVAL; bool set, pend, virt; target_ulong priv, isel, vgein, xlen, nval, wmask; + RISCVException excp; + + /* Check if smstateen is enabled and this access is allowed */ + excp =3D smstateen_aia_acc_ok(env, csrno); + if (excp !=3D RISCV_EXCP_NONE) { + return excp; + } =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -1397,6 +1468,13 @@ static int rmw_xtopei(CPURISCVState *env, int csrno,= target_ulong *val, bool virt; int ret =3D -EINVAL; target_ulong priv, vgein; + RISCVException excp; + + /* Check if smstateen is enabled and this access is allowed */ + excp =3D smstateen_aia_acc_ok(env, csrno); + if (excp !=3D RISCV_EXCP_NONE) { + return excp; + } =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -1708,6 +1786,12 @@ static RISCVException write_mstateen(CPURISCVState *= env, int csrno, wr_mask |=3D 1UL << SMSTATEEN0_FCSR; } =20 + if (riscv_feature(env, RISCV_FEATURE_AIA)) { + wr_mask |=3D (1UL << SMSTATEEN0_IMSIC) + | (1UL << SMSTATEEN0_AIA) + | (1UL << SMSTATEEN0_SVSLCT); + } + write_smstateen(env, reg, wr_mask, new_val); =20 return RISCV_EXCP_NONE; @@ -1736,6 +1820,12 @@ static RISCVException write_mstateenh(CPURISCVState = *env, int csrno, wr_mask |=3D 1UL << SMSTATEEN0_FCSR; } =20 + if (riscv_feature(env, RISCV_FEATURE_AIA)) { + wr_mask |=3D (1UL << SMSTATEEN0_IMSIC) + | (1UL << SMSTATEEN0_AIA) + | (1UL << SMSTATEEN0_SVSLCT); + } + write_smstateen(env, reg, wr_mask, val); =20 return RISCV_EXCP_NONE; @@ -1761,6 +1851,12 @@ static RISCVException write_hstateen(CPURISCVState *= env, int csrno, wr_mask |=3D 1UL << SMSTATEEN0_FCSR; } =20 + if (riscv_feature(env, RISCV_FEATURE_AIA)) { + wr_mask |=3D (1UL << SMSTATEEN0_IMSIC) + | (1UL << SMSTATEEN0_AIA) + | (1UL << SMSTATEEN0_SVSLCT); + } + reg =3D &env->hstateen[index]; wr_mask &=3D env->mstateen[index]; write_smstateen(env, reg, wr_mask, new_val); @@ -1789,6 +1885,12 @@ static RISCVException write_hstateenh(CPURISCVState = *env, int csrno, wr_mask |=3D 1UL << SMSTATEEN0_FCSR; } =20 + if (riscv_feature(env, RISCV_FEATURE_AIA)) { + wr_mask |=3D (1UL << SMSTATEEN0_IMSIC) + | (1UL << SMSTATEEN0_AIA) + | (1UL << SMSTATEEN0_SVSLCT); + } + reg =3D &env->hstateen[index]; val =3D (uint64_t)new_val << 32; val |=3D *reg & 0xFFFFFFFF; @@ -1979,6 +2081,12 @@ static RISCVException rmw_vsieh(CPURISCVState *env, = int csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_vsie64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2033,6 +2141,12 @@ static RISCVException rmw_sieh(CPURISCVState *env, i= nt csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_sie64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2195,6 +2309,12 @@ static RISCVException rmw_vsiph(CPURISCVState *env, = int csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_vsip64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2249,6 +2369,12 @@ static RISCVException rmw_siph(CPURISCVState *env, i= nt csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_sip64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2441,6 +2567,10 @@ static RISCVException read_hstatus(CPURISCVState *en= v, int csrno, static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { + if (smstateen_aia_acc_ok(env, csrno) !=3D RISCV_EXCP_NONE) { + val &=3D ~HSTATUS_VGEIN; + } + env->hstatus =3D val; if (riscv_cpu_mxl(env) !=3D MXL_RV32 && get_field(val, HSTATUS_VSXL) != =3D 2) { qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN optio= ns."); @@ -2501,6 +2631,12 @@ static RISCVException rmw_hidelegh(CPURISCVState *en= v, int csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_hideleg64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2547,6 +2683,12 @@ static RISCVException rmw_hviph(CPURISCVState *env, = int csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_hvip64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2601,6 +2743,13 @@ static RISCVException write_hcounteren(CPURISCVState= *env, int csrno, static RISCVException read_hgeie(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_IMSIC); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + if (val) { *val =3D env->hgeie; } @@ -2610,6 +2759,13 @@ static RISCVException read_hgeie(CPURISCVState *env,= int csrno, static RISCVException write_hgeie(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_IMSIC); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ val &=3D ((((target_ulong)1) << env->geilen) - 1) << 1; env->hgeie =3D val; @@ -2649,6 +2805,13 @@ static RISCVException write_htinst(CPURISCVState *en= v, int csrno, static RISCVException read_hgeip(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_IMSIC); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + if (val) { *val =3D env->hgeip; } @@ -2719,12 +2882,28 @@ static RISCVException write_htimedeltah(CPURISCVSta= te *env, int csrno, =20 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->hvictl; return RISCV_EXCP_NONE; } =20 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret =3D RISCV_EXCP_NONE; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + env->hvictl =3D val & HVICTL_VALID_MASK; return RISCV_EXCP_NONE; } @@ -2783,41 +2962,105 @@ static int write_hvipriox(CPURISCVState *env, int = first_index, =20 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return read_hvipriox(env, 0, env->hviprio, val); } =20 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return write_hvipriox(env, 0, env->hviprio, val); } =20 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return read_hvipriox(env, 4, env->hviprio, val); } =20 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return write_hvipriox(env, 4, env->hviprio, val); } =20 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return read_hvipriox(env, 8, env->hviprio, val); } =20 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return write_hvipriox(env, 8, env->hviprio, val); } =20 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return read_hvipriox(env, 12, env->hviprio, val); } =20 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return write_hvipriox(env, 12, env->hviprio, val); } =20 --=20 2.25.1