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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1652760673; x=1655352674; bh=hsvHkGB8EwizdqQZCo f6yo+LXe/ZYyzfi4QeSTZ9b7k=; b=uGU0MjYZusp0n1L4eYRBvLzeDmybAfG8Up pkuAzlKS/k1AUeVkLy5aTZagDxdrvnvveQ5WX8JKA1/0g06p8CHVahZTlXFxR5O6 zlMgHdsEHzI9QBshp1/r7ZdHJsAMY1nSAGypZacn4aBwcBaZ1MOVPa+8Rdhij9Ik +DX7pF2MAJ4lffzywX1eX3r3hfZCfwI0mYQ6z/pZT12MWDv4XXgpwQ0/K7t4jB3y mpmoT5HFb/FAB2YUdKyVcLevbbMi579C6dKW6foVUfJm+s6Y/Opu8PUN4Ie8mTcp e1ZWBA1SOps8CVdO7grIWI9LUasvqTBIo/8wyjAZWtGzrb0aHZuw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Subject: [PATCH 1/2] target/riscv: Don't expose the CPU properties on names CPUs Date: Tue, 17 May 2022 14:10:59 +1000 Message-Id: <20220517041100.93045-2-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220517041100.93045-1-alistair.francis@opensource.wdc.com> References: <20220517041100.93045-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=129fa4c84=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1652760779397100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis There are currently two types of RISC-V CPUs: - Generic CPUs (base or any) that allow complete custimisation - "Named" CPUs that match existing hardware Users can use the base CPUs to custimise the extensions that they want, for example -cpu rv64,v=3Dtrue. We originally exposed these as part of the named CPUs as well, but that was by accident. Exposing the CPU properties to named CPUs means that we accidently enable extensinos that don't exist on the CPUs by default. For example the SiFive E CPU currently support the zba extension, which is a bug. This patch instead only expose the CPU extensions to the generic CPUs. Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 56 +++++++++++++++++++++++++++++++++++++--------- 1 file changed, 45 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6d01569cad..49b844535a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -118,6 +118,8 @@ static const char * const riscv_intr_names[] =3D { "reserved" }; =20 +static void register_cpu_props(DeviceState *dev); + const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { if (async) { @@ -161,6 +163,7 @@ static void riscv_any_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_12_0); + register_cpu_props(DEVICE(obj)); } =20 #if defined(TARGET_RISCV64) @@ -169,6 +172,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); + register_cpu_props(DEVICE(obj)); } =20 static void rv64_sifive_u_cpu_init(Object *obj) @@ -181,9 +185,11 @@ static void rv64_sifive_u_cpu_init(Object *obj) static void rv64_sifive_e_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); + cpu->cfg.mmu =3D false; } =20 static void rv128_base_cpu_init(Object *obj) @@ -197,6 +203,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); + register_cpu_props(DEVICE(obj)); } #else static void rv32_base_cpu_init(Object *obj) @@ -204,6 +211,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); + register_cpu_props(DEVICE(obj)); } =20 static void rv32_sifive_u_cpu_init(Object *obj) @@ -216,27 +224,33 @@ static void rv32_sifive_u_cpu_init(Object *obj) static void rv32_sifive_e_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); + cpu->cfg.mmu =3D false; } =20 static void rv32_ibex_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); - qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); + cpu->cfg.mmu =3D false; + cpu->cfg.epmp =3D true; } =20 static void rv32_imafcu_nommu_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); + cpu->cfg.mmu =3D false; } #endif =20 @@ -829,6 +843,12 @@ static void riscv_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); =20 + cpu->cfg.ext_counters =3D true; + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; + cpu_set_cpustate_pointers(cpu); =20 #ifndef CONFIG_USER_ONLY @@ -837,7 +857,7 @@ static void riscv_cpu_init(Object *obj) #endif /* CONFIG_USER_ONLY */ } =20 -static Property riscv_cpu_properties[] =3D { +static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), @@ -860,17 +880,12 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 - DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), - DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID= ), - DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID), - DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), @@ -907,6 +922,25 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), =20 + DEFINE_PROP_END_OF_LIST(), +}; + +static void register_cpu_props(DeviceState *dev) +{ + Property *prop; + + for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { + qdev_property_add_static(dev, prop); + } +} + +static Property riscv_cpu_properties[] =3D { + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + + DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), + DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID= ), + DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID), + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), =20 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, f= alse), --=20 2.35.1 From nobody Sat May 4 22:57:59 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652760849918682.758753267283; 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s=dkim; t=1652760676; x=1655352677; bh=ztmteRWb8i441NouTF Guv8lt2boGY+fkUWE8ffGyLY0=; b=oh9ZfSWLTsAa7fx4n47TUdWgAVUp8mcL4q n/Ej8YmLhbM/XJJQ3Cuk8Uyzxv/oh2RKPF53y9X0Y0fSQGDz8zKF+XjUe+yetiZY D4vsM1XCjE7ARTK2/QGj2sPykvUsWAKltE2stY3RxtVk1MBREK+UyMmqbDrY9Id3 UoZEWrtdt2SXOjg85Mg7N3V7s1k6/iK/Sos94pEBJ5TPpyBwkMH7s5Bj0EJgS1u3 /8n8NDuWKHFQRdZLB1PCn/WQ4ihqY0N6Gg98GV5pk+nHVZ97f+4xWebC4Gu1N1q/ uqr/1YKKF4aQkwq4deLc8cTb334kBJiwbipBUVQIZ9JbggSqXVPA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Subject: [PATCH 2/2] target/riscv: Run extension checks for all CPUs Date: Tue, 17 May 2022 14:11:00 +1000 Message-Id: <20220517041100.93045-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220517041100.93045-1-alistair.francis@opensource.wdc.com> References: <20220517041100.93045-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=129fa4c84=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1652760851726100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Instead of just running the extension checks for the base CPUs, instead run them for all CPUs. Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 161 ++++++++++++++++++++++----------------------- 1 file changed, 80 insertions(+), 81 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 49b844535a..ee48a18ae4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -593,102 +593,101 @@ static void riscv_cpu_realize(DeviceState *dev, Err= or **errp) } assert(env->misa_mxl_max =3D=3D env->misa_mxl); =20 - /* If only MISA_EXT is unset for misa, then set it from properties */ - if (env->misa_ext =3D=3D 0) { - uint32_t ext =3D 0; + /* Do some ISA extension error checking */ + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } =20 - /* Do some ISA extension error checking */ - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } =20 - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && + cpu->cfg.ext_a && cpu->cfg.ext_f && + cpu->cfg.ext_d && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); + cpu->cfg.ext_i =3D true; + cpu->cfg.ext_m =3D true; + cpu->cfg.ext_a =3D true; + cpu->cfg.ext_f =3D true; + cpu->cfg.ext_d =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.ext_ifencei =3D true; + } =20 - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)= ) { - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_i =3D true; - cpu->cfg.ext_m =3D true; - cpu->cfg.ext_a =3D true; - cpu->cfg.ext_f =3D true; - cpu->cfg.ext_d =3D true; - cpu->cfg.ext_icsr =3D true; - cpu->cfg.ext_ifencei =3D true; - } + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + error_setg(errp, "F extension requires Zicsr"); + return; + } =20 - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { - error_setg(errp, "F extension requires Zicsr"); - return; - } + if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); + return; + } =20 - if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { - error_setg(errp, "Zfh/Zfhmin extensions require F extension"); - return; - } + if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + error_setg(errp, "D extension requires F extension"); + return; + } =20 - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { - error_setg(errp, "D extension requires F extension"); - return; - } + if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { + error_setg(errp, "V extension requires D extension"); + return; + } =20 - if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { - error_setg(errp, "V extension requires D extension"); - return; - } + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); + return; + } + + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || + cpu->cfg.ext_zhinxmin) { + cpu->cfg.ext_zfinx =3D true; + } =20 - if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_= f) { - error_setg(errp, "Zve32f/Zve64f extensions require F extension= "); + if (cpu->cfg.ext_zfinx) { + if (!cpu->cfg.ext_icsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); return; } - - /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || - cpu->cfg.ext_zhinxmin) { - cpu->cfg.ext_zfinx =3D true; + if (cpu->cfg.ext_f) { + error_setg(errp, + "Zfinx cannot be supported together with F extension"); + return; } + } =20 - if (cpu->cfg.ext_zfinx) { - if (!cpu->cfg.ext_icsr) { - error_setg(errp, "Zfinx extension requires Zicsr"); - return; - } - if (cpu->cfg.ext_f) { - error_setg(errp, - "Zfinx cannot be supported together with F extension"); - return; - } - } + if (cpu->cfg.ext_zk) { + cpu->cfg.ext_zkn =3D true; + cpu->cfg.ext_zkr =3D true; + cpu->cfg.ext_zkt =3D true; + } =20 - if (cpu->cfg.ext_zk) { - cpu->cfg.ext_zkn =3D true; - cpu->cfg.ext_zkr =3D true; - cpu->cfg.ext_zkt =3D true; - } + if (cpu->cfg.ext_zkn) { + cpu->cfg.ext_zbkb =3D true; + cpu->cfg.ext_zbkc =3D true; + cpu->cfg.ext_zbkx =3D true; + cpu->cfg.ext_zkne =3D true; + cpu->cfg.ext_zknd =3D true; + cpu->cfg.ext_zknh =3D true; + } =20 - if (cpu->cfg.ext_zkn) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zkne =3D true; - cpu->cfg.ext_zknd =3D true; - cpu->cfg.ext_zknh =3D true; - } + if (cpu->cfg.ext_zks) { + cpu->cfg.ext_zbkb =3D true; + cpu->cfg.ext_zbkc =3D true; + cpu->cfg.ext_zbkx =3D true; + cpu->cfg.ext_zksed =3D true; + cpu->cfg.ext_zksh =3D true; + } =20 - if (cpu->cfg.ext_zks) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zksed =3D true; - cpu->cfg.ext_zksh =3D true; - } + /* If only MISA_EXT is unset for misa, then set it from properties */ + if (env->misa_ext =3D=3D 0) { + uint32_t ext =3D 0; =20 if (cpu->cfg.ext_i) { ext |=3D RVI; --=20 2.35.1