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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id b12-20020a170902d88c00b0015e8d4eb1fasm8146670plz.68.2022.05.16.22.48.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 22:48:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xAd7na+2KxBtPMtY2na7BNVtRH2LfOqAnHHLmai2Ves=; b=iEnGoxrWBBUVFA9N55qcwl85lWxtXGeREh50OFGNEVw7WPltlQ+LpwjgR9LnmLZQ1i bShKbiPcLXXhOgQXEkw6Hq55SXAYlY9w+qT8yiHfYD817ZBceWGXIy6O6g/x+2XZ+4FZ rga9IUYiuQ6GscMoVoKxHkpllYKtwU6s+0KKAyHsOHTxknoVvhx9QBONLoArAo408APM UsWjJhrTZT3bcY+jozvLV3fYculJC7B+qoQ1pAoGxP2KvMzRGuX2yC0PFFEOAoWBKiqg aD13Fec+bspkiCLkdf6kE0yN48iYKCzJFpm7tB4X800lgJpo0VqJBDZsacr9JIsEtcC9 acLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xAd7na+2KxBtPMtY2na7BNVtRH2LfOqAnHHLmai2Ves=; b=VZfwVFg16Xg4BdQxhL1kGbPC0mT+tpu56r/3w0ADVvlLy3utaggxIU9UE02pM4Fg3k kfSJcV1VnaVMgk72/mAsiscNfr366UPGAgzqUWUfrcu0VcPs//L/Tlb5jyFCTuU9yH4e m93Ff09rQgEQfPu+gLsulD5ArloGPI4n1NGOJ4vE7sS8u7zS/h0K1TuODDiPMBlGXRAO 9J+fT+w75+t3pGU9Mgjwt1Uw3hV6Vc1/OHL51o7dZ06AwD14zQZOvyo6SplC7yDCKsqJ mhinPt92pGGa1pVHalUlxIJpVpwozKEomvFfFcIATWFFbXRbizJ+gjHbswAU5Hcsud6V 3tsA== X-Gm-Message-State: AOAM530tJ4rSbyR9iHjCM4h/gFWNRQqMhcLXHGOShMdLzIxUOtBq+VSw UfkRTMNDNhpaMcPiS4WvH8+lFJI0D15kYw== X-Google-Smtp-Source: ABdhPJw6kiW8Qj9pGbcxDn/gmwHcUuBLndyTKfWcdxT1g/oe07NyruTJZ1PZ1AAeyb3r7RQ3HV4i/g== X-Received: by 2002:a63:1c4e:0:b0:3f2:6da7:5d90 with SMTP id c14-20020a631c4e000000b003f26da75d90mr7562874pgm.429.1652766532943; Mon, 16 May 2022 22:48:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 1/7] target/arm: Enable FEAT_HCX for -cpu max Date: Mon, 16 May 2022 22:48:44 -0700 Message-Id: <20220517054850.177016-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220517054850.177016-1-richard.henderson@linaro.org> References: <20220517054850.177016-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652767424508100001 Content-Type: text/plain; charset="utf-8" This feature adds a new register, HCRX_EL2, which controls many of the newer AArch64 features. So far the register is effectively RES0, because none of the new features are done. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 20 ++++++++++++++++++ target/arm/cpu64.c | 1 + target/arm/helper.c | 50 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 18ca61e8e2..b35b117fe7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -362,6 +362,7 @@ typedef struct CPUArchState { uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint64_t hcr_el2; /* Hypervisor configuration register */ + uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ uint64_t scr_el3; /* Secure configuration register. */ union { /* Fault status registers. */ struct { @@ -1543,6 +1544,19 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define HCR_TWEDEN (1ULL << 59) #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) =20 +#define HCRX_ENAS0 (1ULL << 0) +#define HCRX_ENALS (1ULL << 1) +#define HCRX_ENASR (1ULL << 2) +#define HCRX_FNXS (1ULL << 3) +#define HCRX_FGTNXS (1ULL << 4) +#define HCRX_SMPME (1ULL << 5) +#define HCRX_TALLINT (1ULL << 6) +#define HCRX_VINMI (1ULL << 7) +#define HCRX_VFNMI (1ULL << 8) +#define HCRX_CMOW (1ULL << 9) +#define HCRX_MCE2 (1ULL << 10) +#define HCRX_MSCEN (1ULL << 11) + #define HPFAR_NS (1ULL << 63) =20 #define SCR_NS (1U << 0) @@ -2310,6 +2324,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *en= v) * Not included here is HCR_RW. */ uint64_t arm_hcr_el2_eff(CPUARMState *env); +uint64_t arm_hcrx_el2_eff(CPUARMState *env); =20 /* Return true if the specified exception level is running in AArch64 stat= e. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) @@ -3931,6 +3946,11 @@ static inline bool isar_feature_aa64_ats1e1(const AR= MISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 2; } =20 +static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) !=3D 0; +} + static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 04427e073f..4ab1dcf2ef 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -910,6 +910,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ cpu->isar.id_aa64mmfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr2; diff --git a/target/arm/helper.c b/target/arm/helper.c index 432bd81919..93ab552346 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5278,6 +5278,52 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } =20 +static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + /* No features adding bits to HCRX are implemented. */ + + /* Clear RES0 bits. */ + env->cp15.hcrx_el2 =3D value & valid_mask; +} + +static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_HXEN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo hcrx_el2_reginfo =3D { + .name =3D "HCRX_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 2, + .access =3D PL2_RW, .writefn =3D hcrx_write, .accessfn =3D access_hxen, + .fieldoffset =3D offsetof(CPUARMState, cp15.hcrx_el2), +}; + +/* Return the effective value of HCRX_EL2. */ +uint64_t arm_hcrx_el2_eff(CPUARMState *env) +{ + /* + * The bits in this register behave as 0 for all purposes other than + * direct reads of the register if: + * - EL2 is not enabled in the current security state, + * - SCR_EL3.HXEn is 0. + */ + if (!arm_is_el2_enabled(env) + || (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_HXEN))) { + return 0; + } + return env->cp15.hcrx_el2; +} + static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -8384,6 +8430,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, zcr_reginfo); } =20 + if (cpu_isar_feature(aa64_hcx, cpu)) { + define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); + } + #ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); --=20 2.34.1