From nobody Sat Apr 27 12:58:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652786679686516.1402983354658; Tue, 17 May 2022 04:24:39 -0700 (PDT) Received: from localhost ([::1]:35974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nqvJe-0006OE-Iy for importer2@patchew.org; Tue, 17 May 2022 07:24:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nqvBT-0001HP-PQ; Tue, 17 May 2022 07:16:12 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:41563) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nqvBR-0007Ze-Lh; Tue, 17 May 2022 07:16:11 -0400 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.nyi.internal (Postfix) with ESMTP id 9BC405C0183; Tue, 17 May 2022 07:16:08 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Tue, 17 May 2022 07:16:08 -0400 Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 17 May 2022 07:16:07 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irrelevant.dk; h=cc:cc:content-transfer-encoding:date:date:from:from :in-reply-to:message-id:mime-version:reply-to:sender:subject :subject:to:to; s=fm3; t=1652786168; x=1652872568; bh=tklGr3lk/V 9qKxiYDxtUQbQXXJqR9zPUU7yviLlE9+8=; b=ISrzG3j+rSKvDS7MvJs59B7yvL 8GmvZ5KA8EfDubM19WFbENE8aRIT8+3en9W4kBkhqiY6qkN1v2ygmTloljBs+iou TNwhpbnFjrNQwtBTQbBCNZU8sj2oINqNUeXFWJ6jpC/JukF/nFmYntiOypS790Du eiBOq4ZDPjT65rbkiJ3V3TJLwHwptTwrth1BrMGNp4Z6BDlAvA84Qk9VcZRg6vX1 +ofVyU6kLD+0e7LCgfnwCiBMVhzgRXlxth9gXZGScyBwAtmTMRRNE4Tt6lBU/uex dbJUXZen6I1Lr7MwVAt8aEiFrdZ3L0JVCwxhbxgS8FLS1FymV1N5qWKHvE1g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:message-id :mime-version:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1652786168; x=1652872568; bh=tklGr3lk/V9qKxiYDxtUQbQXXJqR9zPUU7y viLlE9+8=; b=m7ohwAeNV3/C7XIMC+HoP9zPu0zsVdzZ+f7S5EuhKtJHhtVa8ZU pHgBYfXL/iY3JTVlYWRUz7T/uD86zFR/JbjtO3Hkdbw4RN5xqpjPzZuAoD8DGydK 1TnZBtEDt/eQcJaH2sOZNMg+AaW9Db6BdFs+5eokh6EIWHfVG1SBeYIMY8TvO5h9 vlCfScRHE//7VHhO2YyhtdUB++7Lv0QOtyN4NJYktVz8dyjmd7M56BRn9EzmmzgB n+8bfPGtNnHv69YiVkVVMXYSq3+NO7ZYIK3nM+3ccJsVh+sdsU6s2QjdJdh2nxdK +hnMXTkw5lBJNrvFj8olzdh67GAznysnA+g== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrheejgdefhecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffoggfgsedtkeertdertddtnecuhfhrohhmpefmlhgruhhsucfl vghnshgvnhcuoehithhssehirhhrvghlvghvrghnthdrughkqeenucggtffrrghtthgvrh hnpedtleduhfegleehleeltdejffefjedtleeuvdfgteevffegtedvveekheeiieekteen ucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehithhsse hirhhrvghlvghvrghnthdrughk X-ME-Proxy: Feedback-ID: idc91472f:Fastmail From: Klaus Jensen To: qemu-devel@nongnu.org Cc: Lukasz Maniak , qemu-block@nongnu.org, Klaus Jensen , Keith Busch , Klaus Jensen Subject: [PATCH] hw/nvme: clean up CC register write logic Date: Tue, 17 May 2022 13:16:05 +0200 Message-Id: <20220517111605.1494647-1-its@irrelevant.dk> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.27; envelope-from=its@irrelevant.dk; helo=out3-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1652786680837100001 Content-Type: text/plain; charset="utf-8" From: Klaus Jensen The SRIOV series exposed an issued with how CC register writes are handled and how CSTS is set in response to that. Specifically, after applying the SRIOV series, the controller could end up in a state with CC.EN set to '1' but with CSTS.RDY cleared to '0', causing drivers to expect CSTS.RDY to transition to '1' but timing out. Clean this up. Signed-off-by: Klaus Jensen --- Note, this applies on top of nvme-next with v8 of Lukasz's sriov series. hw/nvme/ctrl.c | 35 +++++++++++------------------------ 1 file changed, 11 insertions(+), 24 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 658584d417fe..47d971b2404c 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -6190,9 +6190,8 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetTyp= e rst) =20 if (pci_is_vf(pci_dev)) { sctrl =3D nvme_sctrl(n); + stl_le_p(&n->bar.csts, sctrl->scs ? 0 : NVME_CSTS_FAILED); - } else { - stl_le_p(&n->bar.csts, 0); } } =20 @@ -6405,20 +6404,21 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, nvme_irq_check(n); break; case NVME_REG_CC: + stl_le_p(&n->bar.cc, data); + trace_pci_nvme_mmio_cfg(data & 0xffffffff); =20 - /* Windows first sends data, then sends enable bit */ - if (!NVME_CC_EN(data) && !NVME_CC_EN(cc) && - !NVME_CC_SHN(data) && !NVME_CC_SHN(cc)) - { - cc =3D data; + if (NVME_CC_SHN(data) && !(NVME_CC_SHN(cc))) { + trace_pci_nvme_mmio_shutdown_set(); + nvme_ctrl_shutdown(n); + csts &=3D ~(CSTS_SHST_MASK << CSTS_SHST_SHIFT); + csts |=3D NVME_CSTS_SHST_COMPLETE; + } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(cc)) { + trace_pci_nvme_mmio_shutdown_cleared(); + csts &=3D ~(CSTS_SHST_MASK << CSTS_SHST_SHIFT); } =20 if (NVME_CC_EN(data) && !NVME_CC_EN(cc)) { - cc =3D data; - - /* flush CC since nvme_start_ctrl() needs the value */ - stl_le_p(&n->bar.cc, cc); if (unlikely(nvme_start_ctrl(n))) { trace_pci_nvme_err_startfail(); csts =3D NVME_CSTS_FAILED; @@ -6429,22 +6429,9 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offse= t, uint64_t data, } else if (!NVME_CC_EN(data) && NVME_CC_EN(cc)) { trace_pci_nvme_mmio_stopped(); nvme_ctrl_reset(n, NVME_RESET_CONTROLLER); - cc =3D 0; csts &=3D ~NVME_CSTS_READY; } =20 - if (NVME_CC_SHN(data) && !(NVME_CC_SHN(cc))) { - trace_pci_nvme_mmio_shutdown_set(); - nvme_ctrl_shutdown(n); - cc =3D data; - csts |=3D NVME_CSTS_SHST_COMPLETE; - } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(cc)) { - trace_pci_nvme_mmio_shutdown_cleared(); - csts &=3D ~NVME_CSTS_SHST_COMPLETE; - cc =3D data; - } - - stl_le_p(&n->bar.cc, cc); stl_le_p(&n->bar.csts, csts); =20 break; --=20 2.36.1