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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1652969634237100001 Content-Type: text/plain; charset="utf-8" dcache writeback and icache invalidate is not required when icache is coherent, a shorter fixed-length sequence can be used which just has to flush and re-fetch instructions that were in-flight. Signed-off-by: Nicholas Piggin --- I haven't been able to measure a significant performance difference with this, qemu isn't flushing large ranges frequently so the old sequence is not that slow. include/qemu/cacheflush.h | 4 ++++ util/cacheflush.c | 9 +++++++++ util/cacheinfo.c | 16 ++++++++++++++-- 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/include/qemu/cacheflush.h b/include/qemu/cacheflush.h index ae20bcda73..f65349ce3c 100644 --- a/include/qemu/cacheflush.h +++ b/include/qemu/cacheflush.h @@ -28,6 +28,10 @@ static inline void flush_idcache_range(uintptr_t rx, uin= tptr_t rw, size_t len) =20 #else =20 +#if defined(__powerpc__) +extern bool have_coherent_icache; +#endif + void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len); =20 #endif diff --git a/util/cacheflush.c b/util/cacheflush.c index 4b57186d89..15060f78b8 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -108,7 +108,16 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, s= ize_t len) size_t isize =3D qemu_icache_linesize; =20 b =3D rw & ~(dsize - 1); + + if (have_coherent_icache) { + asm volatile ("sync" : : : "memory"); + asm volatile ("icbi 0,%0" : : "r"(b) : "memory"); + asm volatile ("isync" : : : "memory"); + return; + } + e =3D (rw + len + dsize - 1) & ~(dsize - 1); + for (p =3D b; p < e; p +=3D dsize) { asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); } diff --git a/util/cacheinfo.c b/util/cacheinfo.c index ab1644d490..b632ff47ae 100644 --- a/util/cacheinfo.c +++ b/util/cacheinfo.c @@ -133,18 +133,30 @@ static void arch_cache_info(int *isize, int *dsize) } } =20 -#elif defined(_ARCH_PPC) && defined(__linux__) -# include "elf.h" +#elif defined(__powerpc__) =20 +bool have_coherent_icache =3D false; + +# if defined(_ARCH_PPC) && defined(__linux__) +# include "elf.h" static void arch_cache_info(int *isize, int *dsize) { +# ifdef PPC_FEATURE_ICACHE_SNOOP + unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); +# endif + if (*isize =3D=3D 0) { *isize =3D qemu_getauxval(AT_ICACHEBSIZE); } if (*dsize =3D=3D 0) { *dsize =3D qemu_getauxval(AT_DCACHEBSIZE); } + +# ifdef PPC_FEATURE_ICACHE_SNOOP + have_coherent_icache =3D (hwcap & PPC_FEATURE_ICACHE_SNOOP) !=3D 0; +# endif } +# endif =20 #else static void arch_cache_info(int *isize, int *dsize) { } --=20 2.35.1