From nobody Fri May 3 06:36:23 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1653064765; cv=none; d=zohomail.com; s=zohoarc; b=Hjt3vUzbKPoxM9AWzplU5ZSUKt6toU3I0VSA1PrAKxrMW87qS2rac/wXjbTh/yHuulQjjq+3P+uxXtqmCMv7UO2dfITDPzZzlltrZ6pGT5JhtTWbHX4Ab2sn3360Z7xttyNYFOaR0cYAA/7TKiwLlbESyTdoveBxr0WAuxOGwvY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1653064765; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=kdjWn1G/Jdj9xpPW2wafn7bYmHO4hfqIL7dafDtssb0=; b=WpJtvQEMBFv+sC4E1L6Q8pUiV+t3zK13yNWFIUMSINK5Ps/MZRbJHka6kAbvylc2WMhYZ8bVyO23Lc67M43/iB54KS3V7KKLFDaBSmEjSKC9k5xKuugqwcVWLOcagCpedsVzJyDxijVt1qnga78L/9xd5O/WcNIjRZ61a7T5Urw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653064765401499.82374925763145; Fri, 20 May 2022 09:39:25 -0700 (PDT) Received: from localhost ([::1]:57054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ns5et-0006Rb-Jv for importer2@patchew.org; Fri, 20 May 2022 12:39:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49488) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ns5dc-00057P-Vb for qemu-devel@nongnu.org; Fri, 20 May 2022 12:38:04 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]:2569) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ns5da-00088X-Vl for qemu-devel@nongnu.org; Fri, 20 May 2022 12:38:04 -0400 Received: from fraeml702-chm.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4L4XNx1Zgkz67Lmq; Sat, 21 May 2022 00:34:09 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml702-chm.china.huawei.com (10.206.15.51) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2375.24; Fri, 20 May 2022 18:38:01 +0200 Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Fri, 20 May 2022 17:38:00 +0100 To: , Peter Maydell CC: "Michael S . Tsirkin" , Ben Widawsky , , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Subject: [PATCH v11 1/2] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Date: Fri, 20 May 2022 17:37:31 +0100 Message-ID: <20220520163732.27545-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220520163732.27545-1-Jonathan.Cameron@huawei.com> References: <20220520163732.27545-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml737-chm.china.huawei.com (10.201.108.187) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via X-ZM-MESSAGEID: 1653064767087100001 Content-Type: text/plain; charset="utf-8" Code based on i386/pc enablement. The memory layout places space for 16 host bridge register regions after the GIC_REDIST2 in the extended memmap. The CFMWs are placed above the extended memmap. Only create the CEDT table if cxl=3Don set for the machine. Signed-off-by: Jonathan Cameron Signed-off-by: Ben Widawsky --- hw/arm/virt-acpi-build.c | 33 +++++++++++++++++++++++++++++++++ hw/arm/virt.c | 40 +++++++++++++++++++++++++++++++++++++++- include/hw/arm/virt.h | 1 + 3 files changed, 73 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 449fab0080..86a2f40437 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -39,9 +39,11 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/utils.h" #include "hw/acpi/pci.h" +#include "hw/acpi/cxl.h" #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/generic_event_device.h" #include "hw/acpi/tpm.h" +#include "hw/cxl/cxl.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" @@ -157,10 +159,29 @@ static void acpi_dsdt_add_virtio(Aml *scope, } } =20 +/* Uses local definition of AcpiBuildState so can't easily be common code = */ +static void build_acpi0017(Aml *table) +{ + Aml *dev, *scope, *method; + + scope =3D aml_scope("_SB"); + dev =3D aml_device("CXLM"); + aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + + method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x01))); + aml_append(dev, method); + + aml_append(scope, dev); + aml_append(table, scope); +} + static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, uint32_t irq, VirtMachineState *vms) { int ecam_id =3D VIRT_ECAM_ID(vms->highmem_ecam); + bool cxl_present =3D false; + PCIBus *bus =3D vms->bus; struct GPEXConfig cfg =3D { .mmio32 =3D memmap[VIRT_PCIE_MMIO], .pio =3D memmap[VIRT_PCIE_PIO], @@ -174,6 +195,14 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMap= Entry *memmap, } =20 acpi_dsdt_add_gpex(scope, &cfg); + QLIST_FOREACH(bus, &vms->bus->child, sibling) { + if (pci_bus_is_cxl(bus)) { + cxl_present =3D true; + } + } + if (cxl_present) { + build_acpi0017(scope); + } } =20 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, @@ -991,6 +1020,10 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuild= Tables *tables) vms->oem_table_id); } } + if (ms->cxl_devices_state->is_enabled) { + cxl_build_cedt(ms, table_offsets, tables_blob, tables->linker, + vms->oem_id, vms->oem_table_id); + } =20 if (ms->nvdimms_state->is_enabled) { nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e762655fc6..d818131b57 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -78,6 +78,7 @@ #include "hw/virtio/virtio-mem-pci.h" #include "hw/virtio/virtio-iommu.h" #include "hw/char/pl011.h" +#include "hw/cxl/cxl.h" #include "qemu/guest-random.h" =20 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ @@ -178,6 +179,7 @@ static const MemMapEntry base_memmap[] =3D { static MemMapEntry extended_memmap[] =3D { /* Additional 64 MB redist region (can contain up to 512 redistributor= s) */ [VIRT_HIGH_GIC_REDIST2] =3D { 0x0, 64 * MiB }, + [VIRT_CXL_HOST] =3D { 0x0, 64 * KiB * 16 }, /* 16 UID */ [VIRT_HIGH_PCIE_ECAM] =3D { 0x0, 256 * MiB }, /* Second PCIe window */ [VIRT_HIGH_PCIE_MMIO] =3D { 0x0, 512 * GiB }, @@ -1525,6 +1527,17 @@ static void create_pcie(VirtMachineState *vms) } } =20 +static void create_cxl_host_reg_region(VirtMachineState *vms) +{ + MemoryRegion *sysmem =3D get_system_memory(); + MachineState *ms =3D MACHINE(vms); + MemoryRegion *mr =3D &ms->cxl_devices_state->host_mr; + + memory_region_init(mr, OBJECT(ms), "cxl_host_reg", + vms->memmap[VIRT_CXL_HOST].size); + memory_region_add_subregion(sysmem, vms->memmap[VIRT_CXL_HOST].base, m= r); +} + static void create_platform_bus(VirtMachineState *vms) { DeviceState *dev; @@ -1687,7 +1700,7 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState= *vms, int idx) static void virt_set_memmap(VirtMachineState *vms, int pa_bits) { MachineState *ms =3D MACHINE(vms); - hwaddr base, device_memory_base, device_memory_size, memtop; + hwaddr base, device_memory_base, device_memory_size, memtop, cxl_fmw_b= ase; int i; =20 vms->memmap =3D extended_memmap; @@ -1779,6 +1792,20 @@ static void virt_set_memmap(VirtMachineState *vms, i= nt pa_bits) memory_region_init(&ms->device_memory->mr, OBJECT(vms), "device-memory", device_memory_size); } + + if (ms->cxl_devices_state->fixed_windows) { + GList *it; + + cxl_fmw_base =3D ROUND_UP(base, 256 * MiB); + for (it =3D ms->cxl_devices_state->fixed_windows; it; it =3D it->n= ext) { + CXLFixedWindow *fw =3D it->data; + + fw->base =3D cxl_fmw_base; + memory_region_init_io(&fw->mr, OBJECT(vms), &cfmws_ops, fw, + "cxl-fixed-memory-region", fw->size); + cxl_fmw_base +=3D fw->size; + } + } } =20 /* @@ -2215,6 +2242,15 @@ static void machvirt_init(MachineState *machine) memory_region_add_subregion(sysmem, machine->device_memory->base, &machine->device_memory->mr); } + if (machine->cxl_devices_state->fixed_windows) { + GList *it; + for (it =3D machine->cxl_devices_state->fixed_windows; it; + it =3D it->next) { + CXLFixedWindow *fw =3D it->data; + + memory_region_add_subregion(sysmem, fw->base, &fw->mr); + } + } =20 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); =20 @@ -2241,6 +2277,7 @@ static void machvirt_init(MachineState *machine) create_rtc(vms); =20 create_pcie(vms); + create_cxl_host_reg_region(vms); =20 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)= ) { vms->acpi_dev =3D create_acpi_ged(vms); @@ -2924,6 +2961,7 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) hc->unplug =3D virt_machine_device_unplug_cb; mc->nvdimm_supported =3D true; mc->smp_props.clusters_supported =3D true; + mc->cxl_supported =3D true; mc->auto_enable_numa_with_memhp =3D true; mc->auto_enable_numa_with_memdev =3D true; mc->default_ram_id =3D "mach-virt.ram"; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 15feabac63..67c08a62af 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -92,6 +92,7 @@ enum { /* indices of IO regions located after the RAM */ enum { VIRT_HIGH_GIC_REDIST2 =3D VIRT_LOWMEMMAP_LAST, + VIRT_CXL_HOST, VIRT_HIGH_PCIE_ECAM, VIRT_HIGH_PCIE_MMIO, }; --=20 2.32.0 From nobody Fri May 3 06:36:23 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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Tsirkin" , Ben Widawsky , , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Subject: [PATCH v11 2/2] qtest/cxl: Add aarch64 virt test for CXL Date: Fri, 20 May 2022 17:37:32 +0100 Message-ID: <20220520163732.27545-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220520163732.27545-1-Jonathan.Cameron@huawei.com> References: <20220520163732.27545-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml737-chm.china.huawei.com (10.201.108.187) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via X-ZM-MESSAGEID: 1653064920069100001 Content-Type: text/plain; charset="utf-8" Add a single complex case for aarch64 virt machine. Signed-off-by: Jonathan Cameron --- tests/qtest/cxl-test.c | 48 +++++++++++++++++++++++++++++++++-------- tests/qtest/meson.build | 1 + 2 files changed, 40 insertions(+), 9 deletions(-) diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c index 079011af6a..ac7d71fd74 100644 --- a/tests/qtest/cxl-test.c +++ b/tests/qtest/cxl-test.c @@ -17,6 +17,11 @@ "-device pxb-cxl,id=3Dcxl.1,bus=3Dpcie.0,bus_nr=3D53= " \ "-cxl-fixed-memory-window targets.0=3Dcxl.0,targets.= 1=3Dcxl.1,size=3D4G " =20 +#define QEMU_VIRT_2PXB_CMD "-machine virt,cxl=3Don " \ + "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52= " \ + "-device pxb-cxl,id=3Dcxl.1,bus=3Dpcie.0,bus_nr=3D53= " \ + "-cxl-fixed-memory-window targets.0=3Dcxl.0,targets.= 1=3Dcxl.1,size=3D4G " + #define QEMU_RP "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0 " =20 /* Dual ports on first pxb */ @@ -134,18 +139,43 @@ static void cxl_2pxb_4rp_4t3d(void) qtest_end(); } =20 +static void cxl_virt_2pxb_4rp_4t3d(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + char template[] =3D "/tmp/cxl-test-XXXXXX"; + const char *tmpfs; + + tmpfs =3D mkdtemp(template); + + g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D, + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, + tmpfs, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); +} + int main(int argc, char **argv) { + const char *arch =3D qtest_get_arch(); + g_test_init(&argc, &argv, NULL); =20 - qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); - qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); - qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); - qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); - qtest_add_func("/pci/cxl/rp", cxl_root_port); - qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); - qtest_add_func("/pci/cxl/type3_device", cxl_t3d); - qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); - qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4= t3d); + if (strcmp(arch, "i386") =3D=3D 0 || strcmp(arch, "x86_64") =3D=3D 0) { + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); + qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); + qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window= ); + qtest_add_func("/pci/cxl/rp", cxl_root_port); + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); + qtest_add_func("/pci/cxl/type3_device", cxl_t3d); + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", + cxl_2pxb_4rp_4t3d); + } else if (strcmp(arch, "aarch64") =3D=3D 0) { + qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4", + cxl_virt_2pxb_4rp_4t3d); + } + return g_test_run(); } diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 31287a9173..0fa93da13a 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -215,6 +215,7 @@ qtests_aarch64 =3D \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-= test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-= swtpm-test'] : []) + \ (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test'= , 'fuzz-xlnx-dp-test'] : []) + \ + qtests_cxl + = \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', --=20 2.32.0