From nobody Tue Jul 1 10:55:43 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1653066428; cv=none; d=zohomail.com; s=zohoarc; b=deXAlnfCy+ywO1F8UdaUE1Jg6LHOzBcbrta6cjaitjeGiTQU2TJK2Gth+x7mDVyO9c0Hc7miMlWdXyGpwxAIx/m90OehEjP5JUtvbaB8w0CJvPV9JDeulrQJcx8WMdIOLmqmrhSS8xvZkoU+64ptnSs7IC0U9uXYUPPLpEVlQrA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1653066428; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=tGpdVIb3VBDpAAxy+vXykUnOLclDSJxsSmMYB1oSMW0=; b=Wv+o3jlT8BM9Zg0BqC9W1BZ1Rur8vIoBVMujypXHFGEAfusgP8Xbf1kDCwliCmRbCRZ8WCjJhoEz8nqxZfRBwz3jef+unvVVg/QzTU09xcJ2J1x9mx+YomRHqo0TncMfaAZh8WiWjlgcyTpf/uBKz7N7UBmQwrpLUqloFkZ9hmw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653066428090186.0435415503315; Fri, 20 May 2022 10:07:08 -0700 (PDT) Received: from localhost ([::1]:48020 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ns65j-0003tB-3J for importer2@patchew.org; Fri, 20 May 2022 13:07:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ns61I-0000eR-Ic for qemu-devel@nongnu.org; Fri, 20 May 2022 13:02:32 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]:2574) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ns61G-00042l-Hs for qemu-devel@nongnu.org; Fri, 20 May 2022 13:02:32 -0400 Received: from fraeml736-chm.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4L4Y1J2LQ8z6H6r6; Sat, 21 May 2022 01:02:12 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml736-chm.china.huawei.com (10.206.15.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Fri, 20 May 2022 19:02:28 +0200 Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Fri, 20 May 2022 18:02:27 +0100 To: , Klaus Jensen CC: , Corey Minyard , Damien Hedde , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Ben Widawsky , Subject: [RFC PATCH 2/2] arm/virt: Add aspeed-i2c controller and MCTP EP to enable MCTP testing Date: Fri, 20 May 2022 18:01:28 +0100 Message-ID: <20220520170128.4436-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220520170128.4436-1-Jonathan.Cameron@huawei.com> References: <20220520170128.4436-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml737-chm.china.huawei.com (10.201.108.187) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via X-ZM-MESSAGEID: 1653066430738100001 Content-Type: text/plain; charset="utf-8" As the only I2C emulation in QEMU that supports being both a master and a slave, suitable for MCTP over i2c is aspeed-i2c add this controller to the arm virt model and hook up our new i2c_mctp_cxl_fmapi device. The current Linux driver for aspeed-i2c has a hard requirement on a reset controller. Throw down the simplest reset controller I could find so as to avoid need to make any chance to the kernel code. Patch also builds appropriate device tree. Unfortunately for CXL we need to use ACPI (no DT bindings yet defined). Enabling this will either require appropriate support for MCTP on an i2c master that has ACPI bindings, or modifications of the kernel driver to support ACPI with aspeed-i2c (which might be a little controversial ;) Signed-off-by: Jonathan Cameron --- hw/arm/Kconfig | 1 + hw/arm/virt.c | 77 +++++++++++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 2 ++ 3 files changed, 80 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 219262a8da..4a733298cd 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -30,6 +30,7 @@ config ARM_VIRT select ACPI_VIOT select VIRTIO_MEM_SUPPORTED select ACPI_CXL + select I2C_MCTP_CXL_FMAPI =20 config CHEETAH bool diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d818131b57..ea04279515 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -80,6 +80,9 @@ #include "hw/char/pl011.h" #include "hw/cxl/cxl.h" #include "qemu/guest-random.h" +#include "hw/i2c/i2c.h" +#include "hw/i2c/aspeed_i2c.h" +#include "hw/misc/i2c_mctp_cxl_fmapi.h" =20 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ @@ -156,6 +159,8 @@ static const MemMapEntry base_memmap[] =3D { [VIRT_PVTIME] =3D { 0x090a0000, 0x00010000 }, [VIRT_SECURE_GPIO] =3D { 0x090b0000, 0x00001000 }, [VIRT_MMIO] =3D { 0x0a000000, 0x00000200 }, + [VIRT_I2C] =3D { 0x0b000000, 0x00004000 }, + [VIRT_RESET_FAKE] =3D { 0x0b004000, 0x00000010 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that siz= e */ [VIRT_PLATFORM_BUS] =3D { 0x0c000000, 0x02000000 }, [VIRT_SECURE_MEM] =3D { 0x0e000000, 0x01000000 }, @@ -192,6 +197,7 @@ static const int a15irqmap[] =3D { [VIRT_GPIO] =3D 7, [VIRT_SECURE_UART] =3D 8, [VIRT_ACPI_GED] =3D 9, + [VIRT_I2C] =3D 10, [VIRT_MMIO] =3D 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ [VIRT_GIC_V2M] =3D 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ [VIRT_SMMU] =3D 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ @@ -1996,6 +2002,75 @@ static void virt_cpu_post_init(VirtMachineState *vms= , MemoryRegion *sysmem) } } =20 +static void create_mctp_test(MachineState *ms) +{ + VirtMachineState *vms =3D VIRT_MACHINE(ms); + MemoryRegion *sysmem =3D get_system_memory(); + AspeedI2CState *aspeedi2c; + struct DeviceState *dev; + char *nodename_i2c_master; + char *nodename_i2c_sub; + char *nodename_reset; + uint32_t clk_phandle, reset_phandle; + MemoryRegion *sysmem2; + =20 + dev =3D qdev_new("aspeed.i2c-ast2600"); + aspeedi2c =3D ASPEED_I2C(dev); + object_property_set_link(OBJECT(dev), "dram", OBJECT(ms->ram), &error_= fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_I2C].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&aspeedi2c->busses[0]), 0, qdev_get_= gpio_in(vms->gic, vms->irqmap[VIRT_I2C])); + + /* I2C bus DT */ + reset_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); + nodename_reset =3D g_strdup_printf("/reset@%" PRIx64, vms->memmap[VIRT= _RESET_FAKE].base); + qemu_fdt_add_subnode(ms->fdt, nodename_reset); + qemu_fdt_setprop_string(ms->fdt, nodename_reset, "compatible", "snps,d= w-low-reset"); + qemu_fdt_setprop_sized_cells(ms->fdt, nodename_reset, "reg", + 2, vms->memmap[VIRT_RESET_FAKE].base, + 2, vms->memmap[VIRT_RESET_FAKE].size); + qemu_fdt_setprop_cell(ms->fdt, nodename_reset, "#reset-cells", 0x1); + qemu_fdt_setprop_cell(ms->fdt, nodename_reset, "phandle", reset_phandl= e); + sysmem2 =3D g_new(MemoryRegion, 1); + memory_region_init_ram(sysmem2, NULL, "reset", vms->memmap[VIRT_RESET_= FAKE].size, NULL); + memory_region_add_subregion(sysmem, vms->memmap[VIRT_RESET_FAKE].base,= sysmem2); + =20 + clk_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); + =20 + qemu_fdt_add_subnode(ms->fdt, "/mclk"); + qemu_fdt_setprop_string(ms->fdt, "/mclk", "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(ms->fdt, "/mclk", "#clock-cells", 0x0); + qemu_fdt_setprop_cell(ms->fdt, "/mclk", "clock-frequency", 24000); + qemu_fdt_setprop_string(ms->fdt, "/mclk", "clock-output-names", "bobsc= lk"); + qemu_fdt_setprop_cell(ms->fdt, "/mclk", "phandle", clk_phandle); + + nodename_i2c_master =3D g_strdup_printf("/i2c@%" PRIx64, vms->memmap[V= IRT_I2C].base); + qemu_fdt_add_subnode(ms->fdt, nodename_i2c_master); + qemu_fdt_setprop_string(ms->fdt, nodename_i2c_master, "compatible", "= aspeed,ast2600-i2c-bus"); + qemu_fdt_setprop_cells(ms->fdt, nodename_i2c_master, "multi-master"); + qemu_fdt_setprop_cell(ms->fdt, nodename_i2c_master, "#size-cells", 0); + qemu_fdt_setprop_cell(ms->fdt, nodename_i2c_master, "#address-cells", = 1); + qemu_fdt_setprop_cell(ms->fdt, nodename_i2c_master, "clocks", clk_phan= dle); + qemu_fdt_setprop_string(ms->fdt, nodename_i2c_master, "clock-names", "= bobsclk"); + qemu_fdt_setprop(ms->fdt, nodename_i2c_master, "mctp-controller", NULL= , 0); + qemu_fdt_setprop_cells(ms->fdt, nodename_i2c_master, "interrupts", GIC= _FDT_IRQ_TYPE_SPI, + vms->irqmap[VIRT_I2C], GIC_FDT_IRQ_FLAGS_LEVEL_= HI); + /* Offset to the first bus is 0x80, next one at 0x100 etc */ + qemu_fdt_setprop_sized_cells(ms->fdt, nodename_i2c_master, "reg", + 2, vms->memmap[VIRT_I2C].base + 0x80, + 2, 0x80); + qemu_fdt_setprop_cells(ms->fdt, nodename_i2c_master, "resets", reset_p= handle, 0); + + nodename_i2c_sub =3D g_strdup_printf("/i2c@%" PRIx64 "/mctp@%" PRIx64,= vms->memmap[VIRT_I2C].base, 0x50l); + qemu_fdt_add_subnode(ms->fdt, nodename_i2c_sub); + qemu_fdt_setprop_string(ms->fdt, nodename_i2c_sub, "compatible", "mct= p-i2c-controller"); + qemu_fdt_setprop_sized_cells(ms->fdt, nodename_i2c_sub, "reg", 1, 0x50= | 0x40000000); + + =20 + /* Slave device - linux doesn't use the presence of dt node for this s= o don't create one*/ + i2c_slave_create_simple(aspeed_i2c_get_bus(aspeedi2c, 0), "i2c_mctp_cx= l_switch", 0x4d); +} + static void machvirt_init(MachineState *machine) { VirtMachineState *vms =3D VIRT_MACHINE(machine); @@ -2289,6 +2364,8 @@ static void machvirt_init(MachineState *machine) create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); } =20 + create_mctp_test(machine); + /* connect powerdown request */ vms->powerdown_notifier.notify =3D virt_powerdown_req; qemu_register_powerdown_notifier(&vms->powerdown_notifier); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 67c08a62af..abbfac7c48 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -71,6 +71,8 @@ enum { VIRT_SMMU, VIRT_UART, VIRT_MMIO, + VIRT_I2C, + VIRT_RESET_FAKE, VIRT_RTC, VIRT_FW_CFG, VIRT_PCIE, --=20 2.32.0