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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id h8-20020a654808000000b003f9d1c020cbsm306369pgs.51.2022.05.20.17.04.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 May 2022 17:04:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fG9arG1tn4b444K5zf/g1JuzGuQmuRsUj+aiYfge+3E=; b=y4fNrW4mV30VJPIhWQcFoEZ6CNjNEhkQvJKPlw096guIJ6XndmFCod03U8J+mOWE9j 2m0kJ8jRTELGs/Ydev5vrbI1UBjSKOltsDKF/OCkk457C/mbdc3y22XOjOezQTl0nToe 76Q1o/XptqA9F7KQfYBybysTlvsdq77gRFfdwZy1FTACc9OiAQMXqnPN3rXW2+YLB2M+ zZs4+CHCmQHZWjC5s3M6rFmHDKacBpncU/Ib7zMyJACj73aV4p9URTEUauxy9WqG1Em9 F5+0jksT8dhW5qTmYKMXCo7VsU0sbjUniwF1oZY8YLcVd751A1UZ6+hjLJLaOps0d4dv twkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fG9arG1tn4b444K5zf/g1JuzGuQmuRsUj+aiYfge+3E=; b=ItACFJHVSDZtpoE1F7qaSyvJ3l4mNty3DGQ6ORQhct3+7y0buyOfrBxSODhCOqlhEX cXEDoLvDtWvkvtdDA5oqqOnVWmTJI2N5yNzGWzmFRb9luWwwwXO8H3PAv/DKnjwcEoA+ NTPgU3ZQcEUKCWTQS4EhUDdC26knaQLORkgtq9PdR+P5mv5lV6F3/59I4gSE3sx2qlc7 VUjhqzbxs1pEvHLYKKUJ9Vldqix/lwjHFOYC9kKh0UDQB93tSYrY8G5WDr0yQjhF4N6O JXQzRwi8LQto2IE8jTulByQCoyGgorFOcw85BNjwgRs1ehJ0od1X7NTjO65zdH24zU97 TIlA== X-Gm-Message-State: AOAM531tkcfuCHRu62uZJz5Vd+89ZLJZvU+7097/uwdOOOd87ac1bQq1 firlUKIXar7UUFde+WLkbqnONd57a94/sw== X-Google-Smtp-Source: ABdhPJxMdmB92/j1yrlVXY8CBcPW8KZtKAgeuiR7GQjw9HPKD+Rnng+Ocgy/sGoWIydJHHDL9d01vg== X-Received: by 2002:a17:902:e484:b0:161:6657:dc5b with SMTP id i4-20020a170902e48400b001616657dc5bmr12268974ple.2.1653091466679; Fri, 20 May 2022 17:04:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Subject: [PATCH v3 21/49] semihosting: Use env more often in do_common_semihosting Date: Fri, 20 May 2022 17:03:32 -0700 Message-Id: <20220521000400.454525-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220521000400.454525-1-richard.henderson@linaro.org> References: <20220521000400.454525-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1653093923755100001 We've already loaded cs->env_ptr into a local variable; use it. Since env is unconditionally used, we don't need a dummy use. Signed-off-by: Richard Henderson --- target/arm/common-semi-target.h | 62 ++++++++++++++++++ target/riscv/common-semi-target.h | 50 +++++++++++++++ semihosting/arm-compat-semi.c | 101 ++---------------------------- 3 files changed, 116 insertions(+), 97 deletions(-) create mode 100644 target/arm/common-semi-target.h create mode 100644 target/riscv/common-semi-target.h diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-targe= t.h new file mode 100644 index 0000000000..c20e1cca76 --- /dev/null +++ b/target/arm/common-semi-target.h @@ -0,0 +1,62 @@ +/* + * Target-specific parts of semihosting/arm-compat-semi.c. + * + * Copyright (c) 2005, 2007 CodeSourcery. + * Copyright (c) 2019, 2022 Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_ARM_COMMON_SEMI_TARGET_H +#define TARGET_ARM_COMMON_SEMI_TARGET_H + +#ifndef CONFIG_USER_ONLY +#include "hw/arm/boot.h" +#endif + +static inline target_ulong common_semi_arg(CPUState *cs, int argno) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + if (is_a64(env)) { + return env->xregs[argno]; + } else { + return env->regs[argno]; + } +} + +static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + if (is_a64(env)) { + env->xregs[0] =3D ret; + } else { + env->regs[0] =3D ret; + } +} + +static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr) +{ + return (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); +} + +static inline bool is_64bit_semihosting(CPUArchState *env) +{ + return is_a64(env); +} + +static inline target_ulong common_semi_stack_bottom(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + return is_a64(env) ? env->xregs[31] : env->regs[13]; +} + +static inline bool common_semi_has_synccache(CPUArchState *env) +{ + /* Invalid for A32/T32 */ + return !is_a64(env); +} + +#endif diff --git a/target/riscv/common-semi-target.h b/target/riscv/common-semi-t= arget.h new file mode 100644 index 0000000000..7c8a59e0cc --- /dev/null +++ b/target/riscv/common-semi-target.h @@ -0,0 +1,50 @@ +/* + * Target-specific parts of semihosting/arm-compat-semi.c. + * + * Copyright (c) 2005, 2007 CodeSourcery. + * Copyright (c) 2019, 2022 Linaro + * Copyright =C2=A9 2020 by Keith Packard + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H +#define TARGET_RISCV_COMMON_SEMI_TARGET_H + +static inline target_ulong common_semi_arg(CPUState *cs, int argno) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + return env->gpr[xA0 + argno]; +} + +static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + env->gpr[xA0] =3D ret; +} + +static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr) +{ + return (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) =3D= =3D 8); +} + +static inline bool is_64bit_semihosting(CPUArchState *env) +{ + return riscv_cpu_mxl(env) !=3D MXL_RV32; +} + +static inline target_ulong common_semi_stack_bottom(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + return env->gpr[xSP]; +} + +static inline bool common_semi_has_synccache(CPUArchState *env) +{ + return true; +} + +#endif diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index c53cb1891f..9c6fe7ffd7 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -46,9 +46,6 @@ #else #include "qemu/cutils.h" #include "hw/loader.h" -#ifdef TARGET_ARM -#include "hw/arm/boot.h" -#endif #include "hw/boards.h" #endif =20 @@ -182,96 +179,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs) =20 #endif =20 -#ifdef TARGET_ARM -static inline target_ulong -common_semi_arg(CPUState *cs, int argno) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - if (is_a64(env)) { - return env->xregs[argno]; - } else { - return env->regs[argno]; - } -} - -static inline void -common_semi_set_ret(CPUState *cs, target_ulong ret) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - if (is_a64(env)) { - env->xregs[0] =3D ret; - } else { - env->regs[0] =3D ret; - } -} - -static inline bool -common_semi_sys_exit_extended(CPUState *cs, int nr) -{ - return (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); -} - -static inline bool is_64bit_semihosting(CPUArchState *env) -{ - return is_a64(env); -} - -static inline target_ulong common_semi_stack_bottom(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - return is_a64(env) ? env->xregs[31] : env->regs[13]; -} - -static inline bool common_semi_has_synccache(CPUArchState *env) -{ - /* Invalid for A32/T32. */ - return !is_a64(env); -} -#endif /* TARGET_ARM */ - -#ifdef TARGET_RISCV -static inline target_ulong -common_semi_arg(CPUState *cs, int argno) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - return env->gpr[xA0 + argno]; -} - -static inline void -common_semi_set_ret(CPUState *cs, target_ulong ret) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - env->gpr[xA0] =3D ret; -} - -static inline bool -common_semi_sys_exit_extended(CPUState *cs, int nr) -{ - return (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) =3D= =3D 8); -} - -static inline bool is_64bit_semihosting(CPUArchState *env) -{ - return riscv_cpu_mxl(env) !=3D MXL_RV32; -} - -static inline target_ulong common_semi_stack_bottom(CPUState *cs) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - return env->gpr[xSP]; -} - -static inline bool common_semi_has_synccache(CPUArchState *env) -{ - return true; -} -#endif +#include "common-semi-target.h" =20 /* * The semihosting API has no concept of its errno being thread-safe, @@ -645,7 +553,6 @@ void do_common_semihosting(CPUState *cs) GuestFD *gf; int64_t elapsed; =20 - (void) env; /* Used implicitly by arm lock_user macro */ nr =3D common_semi_arg(cs, 0) & 0xffffffffU; args =3D common_semi_arg(cs, 1); =20 @@ -728,12 +635,12 @@ void do_common_semihosting(CPUState *cs) break; =20 case TARGET_SYS_WRITEC: - qemu_semihosting_console_outc(cs->env_ptr, args); + qemu_semihosting_console_outc(env, args); common_semi_set_ret(cs, 0xdeadbeef); break; =20 case TARGET_SYS_WRITE0: - ret =3D qemu_semihosting_console_outs(cs->env_ptr, args); + ret =3D qemu_semihosting_console_outs(env, args); common_semi_set_ret(cs, ret); break; =20 @@ -764,7 +671,7 @@ void do_common_semihosting(CPUState *cs) break; =20 case TARGET_SYS_READC: - ret =3D qemu_semihosting_console_inc(cs->env_ptr); + ret =3D qemu_semihosting_console_inc(env); common_semi_set_ret(cs, ret); break; =20 --=20 2.34.1