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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id s21-20020a639255000000b003f24a2be89asm4959507pgn.8.2022.05.23.08.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 08:31:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=WiJzMuz84xw5wmmABM5sb4kbwcLrYRDhSlSku9cJw0g=; b=kUYPhJtXF5kPrR4H1ahLcjqJNfpZ25m35YPoscLrYZaK8sykNQVo9KGvfEWaR2xKKm loF2esAJd+lt2Nf0SKwSQbLUJBjsasB82Rpqa1Pu93a63NHyF0DZxE92tCxCzg+sNAMk QIVnQHX417ShCPlmehna5W4WyTaHebvBcUqHhvnyaU8GIx3AKPW1q3/ES5ugIo1vWc1B nwVlaAtT1SxNc/bj/pvIjgvPNz4JLRleVftpsGqwhFkQGx8zisNDkupf1XOG8En1mcG6 5v9HuCl5hPECUZTJ5XS2Ox3vz/6ChefteCaJC4RtPW2e6qlFRPDA8VyRrxkohjM+ncYz 678w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=WiJzMuz84xw5wmmABM5sb4kbwcLrYRDhSlSku9cJw0g=; b=lfsUADL0RHOqUdIaUKsjJO8G2TaaUmTHm885X/T3uLaWCEvL979SMmsauwj6CEg2/M 1+l0lWtU1HZZqO6COdTEN+0H8CdDb2vwBXLDvJbFd5/UvRr7+L34OatY4UxKDvqLBvEe TJzxPo5A4iD93LdGggxPbl9GBxSQFeqAzSnd7pgsiyCuJ00yKXC1seQefbbf55E1kaJj KkhS73qZW+sAT/a/mqfoHePdWaDV2k8FWPgiO59bmj0JAHC/6BWvkO70rXR76FV+3B1K PbftTUlqs/eKk0PVlbCzIP8pW1hHRrMYGOdcXiIyw/TP7xCR3GO0z55CFxVhdzzgr35R Armw== X-Gm-Message-State: AOAM5313K6OcPUMAnNg6xwfC9Zksu6jtxPhMf5BheO2oltUll7JfSBpQ A6IOQmZcPOXET3tTkUSyrQIG/Y6NNK3jw/sh X-Google-Smtp-Source: ABdhPJy5KL4hlob/Hhg8wYV9bL05GVSh7ACauPuR3ykheubnat3vb4zgUXRQ3+VgGJS9z0eaCABySw== X-Received: by 2002:a17:90b:3908:b0:1df:56a8:aa with SMTP id ob8-20020a17090b390800b001df56a800aamr26683379pjb.28.1653319912370; Mon, 23 May 2022 08:31:52 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Bin Meng , qemu-riscv@nongnu.org Subject: [RESEND PATCH v2] target/riscv: Fix typo of mimpid cpu option Date: Mon, 23 May 2022 23:31:46 +0800 Message-Id: <20220523153147.15371-1-frank.chang@sifive.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1653320295071100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang "mimpid" cpu option was mistyped to "mipid". Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, m= ipid CSR values") Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 4 ++-- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6d01569cad..a1f847176e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -37,7 +37,7 @@ #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ (QEMU_VERSION_MINOR << 8) | \ (QEMU_VERSION_MICRO)) -#define RISCV_CPU_MIPID RISCV_CPU_MARCHID +#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID =20 static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; =20 @@ -869,7 +869,7 @@ static Property riscv_cpu_properties[] =3D { =20 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID= ), - DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID), + DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), =20 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5ff7294c6..44975e3e5a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -408,7 +408,7 @@ struct RISCVCPUConfig { =20 uint32_t mvendorid; uint64_t marchid; - uint64_t mipid; + uint64_t mimpid; =20 /* Vendor-specific custom extensions */ bool ext_XVentanaCondOps; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4ea7df02c9..0d5bc2f41d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -674,13 +674,13 @@ static RISCVException read_marchid(CPURISCVState *env= , int csrno, return RISCV_EXCP_NONE; } =20 -static RISCVException read_mipid(CPURISCVState *env, int csrno, - target_ulong *val) +static RISCVException read_mimpid(CPURISCVState *env, int csrno, + target_ulong *val) { CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); =20 - *val =3D cpu->cfg.mipid; + *val =3D cpu->cfg.mimpid; return RISCV_EXCP_NONE; } =20 @@ -3372,7 +3372,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Machine Information Registers */ [CSR_MVENDORID] =3D { "mvendorid", any, read_mvendorid }, [CSR_MARCHID] =3D { "marchid", any, read_marchid }, - [CSR_MIMPID] =3D { "mimpid", any, read_mipid }, + [CSR_MIMPID] =3D { "mimpid", any, read_mimpid }, [CSR_MHARTID] =3D { "mhartid", any, read_mhartid }, =20 [CSR_MCONFIGPTR] =3D { "mconfigptr", any, read_zero, --=20 2.35.1