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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YgXeFZJ++svyGxcNWIu+V+WtRKFzNHxuY5DM2JGZ0B0=; b=nOpxxtlZ82NIBSeSHYtbSiGQY+olxw6hPaKO0+mEwOvHxpCCWe/zRQRoQuthEue8Dl 44knTcjYfidnYE//c2UKTBXvuAFdBK9I5RXV/mw3LwiajN+QCYVMCcUBoWiTcJtoYMhQ Rl1NAJ8H+NT4FyRdYo3e183od2LhAqOGNr2rHgmga7dXAyRygb4r7oV2dL7UIjPD+Q7P rFEW/EYPSH0GLqPoQQnC/tLasd+zCuhnnG/rtGTW2LGqvKH+khbC/pJw4hnhgpLRZ9TJ w35iphH/gjHvB1JXJKHWfCfHj25U6ZqTagycRZp3W5wiYJNOp+RLoJB13qwa4ngx8kiE M2ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YgXeFZJ++svyGxcNWIu+V+WtRKFzNHxuY5DM2JGZ0B0=; b=YX7plkLXHQm0fRJoRMeX42fOW28Wt02PYpZj7+0xdZV29Z4JbrRgLdRLqeLj2kgFjA T5ug++B8YceGH72bOmtlfT53286US9nNHbH/p6BHx/2ioYfoyRQOIS7cEJgVmIn0PHg3 oHwPyv+w2GQFD6IjAsgPnDMMrFDNsLoeW2fPSGhsflpCDAdKRUlPtvO3gpgzUUfEtZlM HHPINkg84sdsRycqHsVcN5ak+Ji0TQCy54ddusdjnS261tODdSEssftXVZ8c3N7fykP8 jgpNKZP6KcNxAMSDZhZFjo1IQ/vjOXlsHpXj6OYSWUcboeYprj7xA2TZxfWVnjXzTnSb LSFw== X-Gm-Message-State: AOAM533MCu7QzXcIPXuTGSPJsxtVNlaSARoWSfRRK6BEQVlUWT3ylxy7 KVfuFE/yyBnAbSlBttuS+tV/FNmlUwVT4g== X-Google-Smtp-Source: ABdhPJxaykZi3Yx01upm/1nfWujgepEmiO+0eTyr2nRnUDr+azeN8p7ojn9wLcjpL8UrI8DZhCfOLg== X-Received: by 2002:a17:90b:1e50:b0:1e0:3a08:9b12 with SMTP id pi16-20020a17090b1e5000b001e03a089b12mr826455pjb.119.1653338876559; Mon, 23 May 2022 13:47:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 12/18] target/arm: Create raise_exception_debug Date: Mon, 23 May 2022 13:47:36 -0700 Message-Id: <20220523204742.740932-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1653340096471100001 Content-Type: text/plain; charset="utf-8" Handle EL testing for debug exceptions in a single place. Split out raise_exception_int as a common helper. Signed-off-by: Richard Henderson --- target/arm/internals.h | 8 ++++++++ target/arm/debug_helper.c | 27 ++++-------------------- target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++------- 3 files changed, 48 insertions(+), 30 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 685214503b..6df38db836 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -125,6 +125,14 @@ G_NORETURN void raise_exception_ra(CPUARMState *env, u= int32_t excp, uint32_t syndrome, uint32_t cur_or_target_el, uintptr_t ra= ); =20 +/** + * raise_exception_debug: + * Similarly. If @excp !=3D EXCPBKPT, modify syndrome to indicate + * when origin and target EL are the same. + */ +G_NORETURN void raise_exception_debug(CPUARMState *env, uint32_t excp, + uint32_t syndrome); + /* * For AArch64, map a given EL to an index in the banked_spsr array. * Note that this mapping and the AArch32 mapping defined in bank_number() diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 08d461fd19..181ba7b042 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -417,19 +417,16 @@ void arm_debug_excp_handler(CPUState *cs) if (wp_hit) { if (wp_hit->flags & BP_CPU) { bool wnr =3D (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) !=3D 0; - bool same_el =3D arm_debug_target_el(env) =3D=3D arm_current_e= l(env); =20 cs->watchpoint_hit =3D NULL; =20 env->exception.fsr =3D arm_debug_exception_fsr(env); env->exception.vaddress =3D wp_hit->hitaddr; - raise_exception(env, EXCP_DATA_ABORT, - syn_watchpoint(same_el, 0, wnr), - arm_debug_target_el(env)); + raise_exception_debug(env, EXCP_DATA_ABORT, + syn_watchpoint(0, 0, wnr)); } } else { uint64_t pc =3D is_a64(env) ? env->pc : env->regs[15]; - bool same_el =3D (arm_debug_target_el(env) =3D=3D arm_current_el(e= nv)); =20 /* * (1) GDB breakpoints should be handled first. @@ -449,9 +446,7 @@ void arm_debug_excp_handler(CPUState *cs) * exception/security level. */ env->exception.vaddress =3D 0; - raise_exception(env, EXCP_PREFETCH_ABORT, - syn_breakpoint(same_el), - arm_debug_target_el(env)); + raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0)); } } =20 @@ -461,9 +456,6 @@ void arm_debug_excp_handler(CPUState *cs) */ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) { - int debug_el =3D arm_debug_target_el(env); - int cur_el =3D arm_current_el(env); - /* FSR will only be used if the debug target EL is AArch32. */ env->exception.fsr =3D arm_debug_exception_fsr(env); /* @@ -472,18 +464,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uin= t32_t syndrome) * exception/security level. */ env->exception.vaddress =3D 0; - /* - * Other kinds of architectural debug exception are ignored if - * they target an exception level below the current one (in QEMU - * this is checked by arm_generate_debug_exceptions()). Breakpoint - * instructions are special because they always generate an exception - * to somewhere: if they can't go to the configured debug exception - * level they are taken to the current exception level. - */ - if (debug_el < cur_el) { - debug_el =3D cur_el; - } - raise_exception(env, EXCP_BKPT, syndrome, debug_el); + raise_exception_debug(env, EXCP_BKPT, syndrome); } =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0a50dbf274..c4988b6c41 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -65,15 +65,11 @@ int exception_target_el(CPUARMState *env, int cur_el, u= int32_t *psyn) return 1; } =20 -void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, - uint32_t cur_or_target_el) +G_NORETURN static +void raise_exception_int(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el) { CPUState *cs =3D env_cpu(env); - int target_el =3D cur_or_target_el; - - if (cur_or_target_el <=3D 1) { - target_el =3D exception_target_el(env, cur_or_target_el, &syndrome= ); - } =20 assert(!excp_is_internal(excp)); cs->exception_index =3D excp; @@ -82,6 +78,39 @@ void raise_exception(CPUARMState *env, uint32_t excp, ui= nt32_t syndrome, cpu_loop_exit(cs); } =20 +void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, + uint32_t cur_or_target_el) +{ + int target_el =3D cur_or_target_el; + if (cur_or_target_el <=3D 1) { + target_el =3D exception_target_el(env, cur_or_target_el, &syndrome= ); + } + raise_exception_int(env, excp, syndrome, target_el); +} + +void raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndr= ome) +{ + int cur_el =3D arm_current_el(env); + int debug_el =3D arm_debug_target_el(env); + + /* + * Most kinds of architectural debug exception are ignored if + * they target an exception level below the current (in QEMU + * this is checked by arm_generate_debug_exceptions()). + * Breakpoint instructions are special because they always generate + * an exception to somewhere: if they can't go to the configured + * debug exception level they are taken to the current exception level. + */ + if (excp =3D=3D EXCP_BKPT) { + debug_el =3D MAX(cur_el, debug_el); + } else { + assert(debug_el >=3D cur_el); + syndrome |=3D (debug_el =3D=3D cur_el) << ARM_EL_EC_SHIFT; + } + + raise_exception_int(env, excp, syndrome, debug_el); +} + void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t cur_or_target_el, uintptr_t ra) { --=20 2.34.1