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([223.226.107.19]) by smtp.gmail.com with ESMTPSA id a25-20020aa79719000000b0052551c1a413sm12647618pfg.204.2022.06.29.23.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jun 2022 23:12:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s5A23qnBk4qw918Czdd0JAuAUtWoLa9kDyNXYGcZMrI=; b=T/bfovaKSXUrmxfCogoznxr4tj7qhcmeDfSGVpwTxD69G5SieDJ7WAbDND0GsDlm6R 6S9orR+yXIwMzvr9OnLT/mZ3TJMRDi4LdDwM+mrIi+Iq6XpgTd44/aT13WqbCWU6kUAc /B1ljGwIUiKJb8u+KbD4VVZpJWqvzuiyyp795qsIIL8fPEMJIwwyP9aHKWQoLCGuRhZ0 XlOkcwfJmMRp0JJc6m8mLX8DzOqL/skqiZaIBnwkgeZbPAQrICGp0HJeiOghKMSJ1K+G CHLe2bXCFjo5CPTkwQkzqwVayBeDnEiV1nocnPNYhH+tIK/6fJi4730zrQG+LC+u5BkJ A7ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s5A23qnBk4qw918Czdd0JAuAUtWoLa9kDyNXYGcZMrI=; b=U/Mfq7gDZQuqC1086Rb02nynSHGZYptHXsWpXn0zN/ZGP0OJ+moFggGiE3T02VX8dk 6nbCm61j5VqOeRWmV/C4iPBN7bLov/oxyK1HtAOtD+n6Ddqyfpzk9QpagaoUVQavT048 yIhtYmxPioODckvplOAWhrebmBCnENcpwC2gVP9Uv2psSFoR1N1dvF1do+4QNNS0o8U3 GSLVMbO4BSy0P8Lu02PIHk9LjQSVTIRSGsTYsF6BWELvAt8pkY+3qV1R3y1sKP3c3uiZ HPf+b6H0q+kdxDb0PVa5ay4W1Mlj5PMJMBQnGvXITmme8BffVJdL/OHwTl8HodlodT0u VMPQ== X-Gm-Message-State: AJIora8ncgsEt2mbWRUe0yWEmbHFNs8kr2pZwyRePdJY5TUQNvgDUJga ETD2uPkjukyrSjDG7UkOKJc3kg== X-Google-Smtp-Source: AGRyM1u+AwhZOeEui89TxdN39S9GtPNf0YbEerD9+7R5KiLM4jfmarPB/vnQf025EXQ6GqplLmhBrg== X-Received: by 2002:a63:ef0b:0:b0:40d:287d:71e1 with SMTP id u11-20020a63ef0b000000b0040d287d71e1mr6248752pgh.330.1656569563342; Wed, 29 Jun 2022 23:12:43 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Alistair Francis Subject: [PATCH v9 1/2] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() Date: Thu, 30 Jun 2022 11:41:49 +0530 Message-Id: <20220630061150.905174-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220630061150.905174-1-apatel@ventanamicro.com> References: <20220630061150.905174-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=apatel@ventanamicro.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1656569818135100001 Content-Type: text/plain; charset="utf-8" We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Reviewed-by: Alistair Francis Signed-off-by: Anup Patel Acked-By: dramforever --- target/riscv/cpu.h | 5 + target/riscv/cpu_helper.c | 252 +++++++++++++++++++++++++++++++++++++- target/riscv/instmap.h | 45 +++++++ 3 files changed, 296 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5c7acc055a..ffb1a18873 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -285,6 +285,11 @@ struct CPUArchState { /* Signals whether the current exception occurred with two-stage addre= ss translation active. */ bool two_stage_lookup; + /* + * Signals whether the current exception occurred while doing two-stage + * address translation for the VS-stage page table walk. + */ + bool two_stage_indirect_lookup; =20 target_ulong scounteren; target_ulong mcounteren; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index be28615e23..c59cfddac2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,6 +22,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/exec-all.h" +#include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" @@ -1057,7 +1058,8 @@ restart: =20 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type, bool pmp_violat= ion, - bool first_stage, bool two_stage) + bool first_stage, bool two_stage, + bool two_stage_indirect) { CPUState *cs =3D env_cpu(env); int page_fault_exceptions, vm; @@ -1107,6 +1109,7 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, } env->badaddr =3D address; env->two_stage_lookup =3D two_stage; + env->two_stage_indirect_lookup =3D two_stage_indirect; } =20 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) @@ -1152,6 +1155,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, env->badaddr =3D addr; env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } =20 @@ -1177,6 +1181,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, env->badaddr =3D addr; env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } =20 @@ -1192,6 +1197,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, bool pmp_violation =3D false; bool first_stage_error =3D true; bool two_stage_lookup =3D false; + bool two_stage_indirect_error =3D false; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; /* default TLB page size */ @@ -1229,6 +1235,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, */ if (ret =3D=3D TRANSLATE_G_STAGE_FAIL) { first_stage_error =3D false; + two_stage_indirect_error =3D true; access_type =3D MMU_DATA_LOAD; } =20 @@ -1312,12 +1319,218 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr addres= s, int size, raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error, riscv_cpu_virt_enabled(env) || - riscv_cpu_two_stage_lookup(mmu_idx)); + riscv_cpu_two_stage_lookup(mmu_idx), + two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); } =20 return true; } + +static target_ulong riscv_transformed_insn(CPURISCVState *env, + target_ulong insn, + target_ulong taddr) +{ + target_ulong xinsn =3D 0; + target_ulong access_rs1 =3D 0, access_imm =3D 0, access_size =3D 0; + + /* + * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to + * be uncompressed. The Quadrant 1 of RVC instruction space need + * not be transformed because these instructions won't generate + * any load/store trap. + */ + + if ((insn & 0x3) !=3D 0x3) { + /* Transform 16bit instruction into 32bit instruction */ + switch (GET_C_OP(insn)) { + case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLD_LQ: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FLD (RV32/64) */ + xinsn =3D OPC_RISC_FLD; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_LD_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_LW: /* C.LW */ + xinsn =3D OPC_RISC_LW; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_LW_IMM(insn); + access_size =3D 4; + break; + case OPC_RISC_C_FUNC_FLW_LD: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FLW (RV32) */ + xinsn =3D OPC_RISC_FLW; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_LW_IMM(insn); + access_size =3D 4; + } else { /* C.LD (RV64/RV128) */ + xinsn =3D OPC_RISC_LD; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_LD_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_FSD_SQ: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FSD (RV32/64) */ + xinsn =3D OPC_RISC_FSD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_SD_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_SW: /* C.SW */ + xinsn =3D OPC_RISC_SW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_SW_IMM(insn); + access_size =3D 4; + break; + case OPC_RISC_C_FUNC_FSW_SD: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FSW (RV32) */ + xinsn =3D OPC_RISC_FSW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_SW_IMM(insn); + access_size =3D 4; + } else { /* C.SD (RV64/RV128) */ + xinsn =3D OPC_RISC_SD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_SD_IMM(insn); + access_size =3D 8; + } + break; + default: + break; + } + break; + case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLDSP_LQSP: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FLDSP (RV32/64) */ + xinsn =3D OPC_RISC_FLD; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_LDSP_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ + xinsn =3D OPC_RISC_LW; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_LWSP_IMM(insn); + access_size =3D 4; + break; + case OPC_RISC_C_FUNC_FLWSP_LDSP: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FLWSP (RV32) */ + xinsn =3D OPC_RISC_FLW; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_LWSP_IMM(insn); + access_size =3D 4; + } else { /* C.LDSP (RV64/RV128) */ + xinsn =3D OPC_RISC_LD; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_LDSP_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_FSDSP_SQSP: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FSDSP (RV32/64) */ + xinsn =3D OPC_RISC_FSD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_SDSP_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ + xinsn =3D OPC_RISC_SW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_SWSP_IMM(insn); + access_size =3D 4; + break; + case 7: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FSWSP (RV32) */ + xinsn =3D OPC_RISC_FSW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_SWSP_IMM(insn); + access_size =3D 4; + } else { /* C.SDSP (RV64/RV128) */ + xinsn =3D OPC_RISC_SD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_SDSP_IMM(insn); + access_size =3D 8; + } + break; + default: + break; + } + break; + default: + break; + } + + /* + * Clear Bit1 of transformed instruction to indicate that + * original insruction was a 16bit instruction + */ + xinsn &=3D ~((target_ulong)0x2); + } else { + /* Transform 32bit (or wider) instructions */ + switch (MASK_OP_MAJOR(insn)) { + case OPC_RISC_ATOMIC: + xinsn =3D insn; + access_rs1 =3D GET_RS1(insn); + access_size =3D 1 << GET_FUNCT3(insn); + break; + case OPC_RISC_LOAD: + case OPC_RISC_FP_LOAD: + xinsn =3D SET_I_IMM(insn, 0); + access_rs1 =3D GET_RS1(insn); + access_imm =3D GET_IMM(insn); + access_size =3D 1 << GET_FUNCT3(insn); + break; + case OPC_RISC_STORE: + case OPC_RISC_FP_STORE: + xinsn =3D SET_S_IMM(insn, 0); + access_rs1 =3D GET_RS1(insn); + access_imm =3D GET_STORE_IMM(insn); + access_size =3D 1 << GET_FUNCT3(insn); + break; + case OPC_RISC_SYSTEM: + if (MASK_OP_SYSTEM(insn) =3D=3D OPC_RISC_HLVHSV) { + xinsn =3D insn; + access_rs1 =3D GET_RS1(insn); + access_size =3D 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); + access_size =3D 1 << access_size; + } + break; + default: + break; + } + } + + if (access_size) { + xinsn =3D SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_i= mm)) & + (access_size - 1)); + } + + return xinsn; +} #endif /* !CONFIG_USER_ONLY */ =20 /* @@ -1342,6 +1555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; uint64_t deleg =3D async ? env->mideleg : env->medeleg; target_ulong tval =3D 0; + target_ulong tinst =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; =20 @@ -1357,20 +1571,43 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { - case RISCV_EXCP_INST_GUEST_PAGE_FAULT: case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_ADDR_MIS: - case RISCV_EXCP_INST_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: case RISCV_EXCP_STORE_AMO_ADDR_MIS: case RISCV_EXCP_LOAD_ACCESS_FAULT: case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: write_gva =3D env->two_stage_lookup; tval =3D env->badaddr; + if (env->two_stage_indirect_lookup) { + /* + * special pseudoinstruction for G-stage fault taken while + * doing VS-stage page table walk. + */ + tinst =3D (riscv_cpu_xlen(env) =3D=3D 32) ? 0x00002000 : 0= x00003000; + } else { + /* + * The "Addr. Offset" field in transformed instruction is + * non-zero only for misaligned access. + */ + tinst =3D riscv_transformed_insn(env, env->bins, tval); + } + break; + case RISCV_EXCP_INST_GUEST_PAGE_FAULT: + case RISCV_EXCP_INST_ADDR_MIS: + case RISCV_EXCP_INST_ACCESS_FAULT: + case RISCV_EXCP_INST_PAGE_FAULT: + write_gva =3D env->two_stage_lookup; + tval =3D env->badaddr; + if (env->two_stage_indirect_lookup) { + /* + * special pseudoinstruction for G-stage fault taken while + * doing VS-stage page table walk. + */ + tinst =3D (riscv_cpu_xlen(env) =3D=3D 32) ? 0x00002000 : 0= x00003000; + } break; case RISCV_EXCP_ILLEGAL_INST: case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: @@ -1450,6 +1687,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->sepc =3D env->pc; env->stval =3D tval; env->htval =3D htval; + env->htinst =3D tinst; env->pc =3D (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S); @@ -1480,6 +1718,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mepc =3D env->pc; env->mtval =3D tval; env->mtval2 =3D mtval2; + env->mtinst =3D tinst; env->pc =3D (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); @@ -1492,6 +1731,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) */ =20 env->two_stage_lookup =3D false; + env->two_stage_indirect_lookup =3D false; #endif cs->exception_index =3D RISCV_EXCP_NONE; /* mark handled to qemu */ } diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h index 40b6d2b64d..f877530576 100644 --- a/target/riscv/instmap.h +++ b/target/riscv/instmap.h @@ -184,6 +184,8 @@ enum { OPC_RISC_CSRRWI =3D OPC_RISC_SYSTEM | (0x5 << 12), OPC_RISC_CSRRSI =3D OPC_RISC_SYSTEM | (0x6 << 12), OPC_RISC_CSRRCI =3D OPC_RISC_SYSTEM | (0x7 << 12), + + OPC_RISC_HLVHSV =3D OPC_RISC_SYSTEM | (0x4 << 12), }; =20 #define MASK_OP_FP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) @@ -310,12 +312,20 @@ enum { | (extract32(inst, 12, 8) << 12) \ | (sextract64(inst, 31, 1) << 20)) =20 +#define GET_FUNCT3(inst) extract32(inst, 12, 3) +#define GET_FUNCT7(inst) extract32(inst, 25, 7) #define GET_RM(inst) extract32(inst, 12, 3) #define GET_RS3(inst) extract32(inst, 27, 5) #define GET_RS1(inst) extract32(inst, 15, 5) #define GET_RS2(inst) extract32(inst, 20, 5) #define GET_RD(inst) extract32(inst, 7, 5) #define GET_IMM(inst) sextract64(inst, 20, 12) +#define SET_RS1(inst, val) deposit32(inst, 15, 5, val) +#define SET_RS2(inst, val) deposit32(inst, 20, 5, val) +#define SET_RD(inst, val) deposit32(inst, 7, 5, val) +#define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val) +#define SET_S_IMM(inst, val) \ + deposit32(deposit32(inst, 7, 5, val), 25, 7, (val) >> 5) =20 /* RVC decoding macros */ #define GET_C_IMM(inst) (extract32(inst, 2, 5) \ @@ -346,6 +356,8 @@ enum { | (extract32(inst, 5, 1) << 6)) #define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \ | (extract16(inst, 5, 2) << 6)) +#define GET_C_SW_IMM(inst) GET_C_LW_IMM(inst) +#define GET_C_SD_IMM(inst) GET_C_LD_IMM(inst) #define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \ | (extract32(inst, 11, 1) << 4) \ | (extract32(inst, 2, 1) << 5) \ @@ -366,4 +378,37 @@ enum { #define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3)) #define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3)) =20 +#define GET_C_FUNC(inst) extract32(inst, 13, 3) +#define GET_C_OP(inst) extract32(inst, 0, 2) + +enum { + /* RVC Quadrants */ + OPC_RISC_C_OP_QUAD0 =3D 0x0, + OPC_RISC_C_OP_QUAD1 =3D 0x1, + OPC_RISC_C_OP_QUAD2 =3D 0x2 +}; + +enum { + /* RVC Quadrant 0 */ + OPC_RISC_C_FUNC_ADDI4SPN =3D 0x0, + OPC_RISC_C_FUNC_FLD_LQ =3D 0x1, + OPC_RISC_C_FUNC_LW =3D 0x2, + OPC_RISC_C_FUNC_FLW_LD =3D 0x3, + OPC_RISC_C_FUNC_FSD_SQ =3D 0x5, + OPC_RISC_C_FUNC_SW =3D 0x6, + OPC_RISC_C_FUNC_FSW_SD =3D 0x7 +}; + +enum { + /* RVC Quadrant 2 */ + OPC_RISC_C_FUNC_SLLI_SLLI64 =3D 0x0, + OPC_RISC_C_FUNC_FLDSP_LQSP =3D 0x1, + OPC_RISC_C_FUNC_LWSP =3D 0x2, + OPC_RISC_C_FUNC_FLWSP_LDSP =3D 0x3, + OPC_RISC_C_FUNC_JR_MV_EBREAK_JALR_ADD =3D 0x4, + OPC_RISC_C_FUNC_FSDSP_SQSP =3D 0x5, + OPC_RISC_C_FUNC_SWSP =3D 0x6, + OPC_RISC_C_FUNC_FSWSP_SDSP =3D 0x7 +}; + #endif --=20 2.34.1 From nobody Sat May 18 20:57:41 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1656569873; cv=none; d=zohomail.com; s=zohoarc; b=ABX7rUX+KfOep6Ub1ruIDNXkptPsLogiQg85c3C9eHro7CQfUPUsKFys4dCNW2IlShik5UtREHdJYYHHAunciNZjaTepecPnlqnqQSDWs/d/xe+iK+fy/BhvQiqJMRbCdc0d9TfhlNYaZ7p5JY7nG/aCMVps64SXR67Z9Yfs2VY= ARC-Message-Signature: i=1; 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([223.226.107.19]) by smtp.gmail.com with ESMTPSA id a25-20020aa79719000000b0052551c1a413sm12647618pfg.204.2022.06.29.23.12.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jun 2022 23:12:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jXsfoRJoFy8eowC34vbywLaVEMgoFF/TBBpgUmrTXTM=; b=kFIIxZvqDaWyIaSnXkvA73FodSq7SjheGmhtc36nC8ddv9FBuaFpiyLCIjbDKOd43F oHC2quyHsrl1+T8bsb7sZVrunQ9FQHBZnZAy/vtoYYe+Oc3VWmGlNqi7Je3qn/nc7I3o XYtI22gQO12iBOonpWY+/23ecjWomsDCaEJ3nV2JEuW6TGeAKFXEwFGI33cg8hSpaRSO tdDqAvDajUycVHdeWS2X0/FTCY1+k1fBJ44V04WHUSwaIIfZH0kX/zNsjAur6O5W4tet lUY4O+SOn9ftLN2jK9kGgfmXg5VbFqEoGWXBIhq9cqK5l5P+v0fTXiM9PmSntPrNhNWN JK5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jXsfoRJoFy8eowC34vbywLaVEMgoFF/TBBpgUmrTXTM=; b=p8sWqFsPoyzmygGU5SuhgYChk92R5t7IwM/K25es+UbdMZJDDkoiJv9blNfBj5HJSG H6ajnpsHodvXDdNquRnmRAZMPoCDl26cPwRnWmxnqzObnu9mn0OEBLUi/TpvZuoQCqVV LdS98yk6bX2Cq4pqmZrtoUeLHA9a29bn6uX9Lfc9MP6mMrCb/qBTnyJwRAfD1Q350/f5 H5X1lM5ZywcG/fJa9ZOZYuMv90KBFyqVw/BhtdDVX4/x8RnpB9urpHItHE9cwRdvhwtO CUE7BjDlW+j8EkM/VYGf5MZPOZSW26JTlMOmFZWXRnRXsJjbUXArsNtG5CkTWhNnoQ3Q t5Gg== X-Gm-Message-State: AJIora+F9TMYAfuLpqeN2O8v2eSBKxpkmZceffa2e0iSsyeAQB+jtSLT XUDlusUzirEQ6ov7rx6DZYCZOw== X-Google-Smtp-Source: AGRyM1uXMLgjAWgs6LqnrAEDUN/jaYYBhwCIzVEJvqwYH2Nq1wB/xZb5riRkUnRrg56P31M9eTwukA== X-Received: by 2002:a63:4d57:0:b0:405:1ff6:382a with SMTP id n23-20020a634d57000000b004051ff6382amr6406185pgl.250.1656569568007; Wed, 29 Jun 2022 23:12:48 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Alistair Francis , Rahul Pathak Subject: [PATCH v9 2/2] target/riscv: Force disable extensions if priv spec version does not match Date: Thu, 30 Jun 2022 11:41:50 +0530 Message-Id: <20220630061150.905174-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220630061150.905174-1-apatel@ventanamicro.com> References: <20220630061150.905174-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=apatel@ventanamicro.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1656569874471100001 Content-Type: text/plain; charset="utf-8" We should disable extensions in riscv_cpu_realize() if minimum required priv spec version is not satisfied. This also ensures that machines with priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter extensions. Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to the devic= e tree") Reviewed-by: Alistair Francis Signed-off-by: Anup Patel Signed-off-by: Rahul Pathak --- target/riscv/cpu.c | 150 ++++++++++++++++++++++++++++----------------- 1 file changed, 94 insertions(+), 56 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e7ca6cd4a..9bc4ef0685 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -43,9 +43,82 @@ static const char riscv_single_letter_exts[] =3D "IEMAFD= QCPVH"; =20 struct isa_ext_data { const char *name; - bool enabled; + bool multi_letter; + int min_version; + int ext_enable_offset; }; =20 +#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ +{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} + +/** + * Here are the ordering rules of extension naming defined by RISC-V + * specification : + * 1. All extensions should be separated from other multi-letter extensions + * by an underscore. + * 2. The first letter following the 'Z' conventionally indicates the most + * closely related alphabetical extension category, IMAFDQLCBKJTPVH. + * If multiple 'Z' extensions are named, they should be ordered first + * by category, then alphabetically within a category. + * 3. Standard supervisor-level extensions (starts with 'S') should be + * listed after standard unprivileged extensions. If multiple + * supervisor-level extensions are listed, they should be ordered + * alphabetically. + * 4. Non-standard extensions (starts with 'X') must be listed after all + * standard extensions. They must be separated from other multi-letter + * extensions by an underscore. + */ +static const struct isa_ext_data isa_edata_arr[] =3D { + ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), + ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), + ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), + ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), + ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), + ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), + ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), + ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), + ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), + ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), + ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), + ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), + ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), + ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), + ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), + ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), + ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), + ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), + ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), + ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), + ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), + ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), + ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), + ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), + ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), + ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), + ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), + ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), + ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), +}; + +static bool isa_ext_is_enabled(RISCVCPU *cpu, + const struct isa_ext_data *edata) +{ + bool *ext_enabled =3D (void *)&cpu->cfg + edata->ext_enable_offset; + + return *ext_enabled; +} + +static void isa_ext_update_enabled(RISCVCPU *cpu, + const struct isa_ext_data *edata, bool = en) +{ + bool *ext_enabled =3D (void *)&cpu->cfg + edata->ext_enable_offset; + + *ext_enabled =3D en; +} + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -530,7 +603,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); CPUClass *cc =3D CPU_CLASS(mcc); - int priv_version =3D -1; + int i, priv_version =3D -1; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -558,6 +631,23 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) set_priv_version(env, priv_version); } =20 + /* Force disable extensions if priv spec version does not match */ + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + (env->priv_ver < isa_edata_arr[i].min_version)) { + isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x%lx because " + "privilege spec version does not match", + isa_edata_arr[i].name, (unsigned long)env->mhartid= ); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + isa_edata_arr[i].name); +#endif + } + } + if (cpu->cfg.mmu) { riscv_set_feature(env, RISCV_FEATURE_MMU); } @@ -1049,67 +1139,15 @@ static void riscv_cpu_class_init(ObjectClass *c, vo= id *data) device_class_set_props(dc, riscv_cpu_properties); } =20 -#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop} - static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_st= r_len) { char *old =3D *isa_str; char *new =3D *isa_str; int i; =20 - /** - * Here are the ordering rules of extension naming defined by RISC-V - * specification : - * 1. All extensions should be separated from other multi-letter exten= sions - * by an underscore. - * 2. The first letter following the 'Z' conventionally indicates the = most - * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they should be ordered fir= st - * by category, then alphabetically within a category. - * 3. Standard supervisor-level extensions (starts with 'S') should be - * listed after standard unprivileged extensions. If multiple - * supervisor-level extensions are listed, they should be ordered - * alphabetically. - * 4. Non-standard extensions (starts with 'X') must be listed after a= ll - * standard extensions. They must be separated from other multi-let= ter - * extensions by an underscore. - */ - struct isa_ext_data isa_edata_arr[] =3D { - ISA_EDATA_ENTRY(zicsr, ext_icsr), - ISA_EDATA_ENTRY(zifencei, ext_ifencei), - ISA_EDATA_ENTRY(zmmul, ext_zmmul), - ISA_EDATA_ENTRY(zfh, ext_zfh), - ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), - ISA_EDATA_ENTRY(zfinx, ext_zfinx), - ISA_EDATA_ENTRY(zdinx, ext_zdinx), - ISA_EDATA_ENTRY(zba, ext_zba), - ISA_EDATA_ENTRY(zbb, ext_zbb), - ISA_EDATA_ENTRY(zbc, ext_zbc), - ISA_EDATA_ENTRY(zbkb, ext_zbkb), - ISA_EDATA_ENTRY(zbkc, ext_zbkc), - ISA_EDATA_ENTRY(zbkx, ext_zbkx), - ISA_EDATA_ENTRY(zbs, ext_zbs), - ISA_EDATA_ENTRY(zk, ext_zk), - ISA_EDATA_ENTRY(zkn, ext_zkn), - ISA_EDATA_ENTRY(zknd, ext_zknd), - ISA_EDATA_ENTRY(zkne, ext_zkne), - ISA_EDATA_ENTRY(zknh, ext_zknh), - ISA_EDATA_ENTRY(zkr, ext_zkr), - ISA_EDATA_ENTRY(zks, ext_zks), - ISA_EDATA_ENTRY(zksed, ext_zksed), - ISA_EDATA_ENTRY(zksh, ext_zksh), - ISA_EDATA_ENTRY(zkt, ext_zkt), - ISA_EDATA_ENTRY(zve32f, ext_zve32f), - ISA_EDATA_ENTRY(zve64f, ext_zve64f), - ISA_EDATA_ENTRY(zhinx, ext_zhinx), - ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), - ISA_EDATA_ENTRY(svinval, ext_svinval), - ISA_EDATA_ENTRY(svnapot, ext_svnapot), - ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), - }; - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].enabled) { + if (isa_edata_arr[i].multi_letter && + isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old =3D new; --=20 2.34.1