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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=john@john-millikin.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @john-millikin.com) X-ZM-MESSAGEID: 1660696945433100001 Content-Type: text/plain; charset="utf-8" Per investigation on the linked ticket, SunOS issues a SCSI bus reset to the ESP as part of its boot sequence. If this ESP command doesn't cause devices to assert sense flag UNIT ATTENTION, SunOS will consider the CD-ROM device to be non-compliant with Common Command Set (CCS). In this condition, the SunOS installer's early userspace doesn't set the installation source location to sr0 and the miniroot copy fails. Suggested-by: Bill Paul Buglink: https://gitlab.com/qemu-project/qemu/-/issues/1127 --- hw/scsi/esp.c | 6 ++++++ 1 file changed, 6 insertions(+) With this patch in place, booting the SunOS installation contains the new output line: sr0 at esp0 target 6 lun 0 and the early userspace successfully writes the CD-ROM's device name to the ramdisk, where the installer script expects it: # dd if=3D/dev/rd0a of=3D/tmp.bin bs=3D1 count=3D3 3+0 records in 3+0 records out # cat /tmp.bin; echo '' sr0 # diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 2d3c649567..c799c19bd4 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -939,6 +939,11 @@ static void esp_soft_reset(ESPState *s) esp_hard_reset(s); } =20 +static void esp_bus_reset(ESPState *s) +{ + qbus_reset_all(BUS(&s->bus)); +} + static void parent_esp_reset(ESPState *s, int irq, int level) { if (level) { @@ -1067,6 +1072,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint6= 4_t val) break; case CMD_BUSRESET: trace_esp_mem_writeb_cmd_bus_reset(val); + esp_bus_reset(s); if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { s->rregs[ESP_RINTR] |=3D INTR_RST; esp_raise_irq(s); --=20 2.25.1