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([171.76.80.76]) by smtp.gmail.com with ESMTPSA id c127-20020a4a4f85000000b00425806a20f5sm701003oob.3.2022.08.18.20.09.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 20:09:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc; bh=8r/DVsdQ9Z1jAtpgwSIe7wtgj33LBSoM3OtCS4E6yq4=; b=LmI5CJz2eXeeCQraA+RmXBwE96Czeu8fXnqBZiV5Qu6Up9KA5KTffC5qIrn0J4Kz4s nCWt9dVSideEN9G41gYrHNS0B8LMEWQWc8lJcJsGNDtY/CpcN8b2DN4uM1SrfxnvQyen hPB38MfMzcipZYljNStcqUUVCTEK87KFe6+fcEJrNp48H0ODlCEmC6NSkB98ZacEk6e5 f0gqMgNEEzX01dpYvuH0HlYCVsYsOhBtqawXbs+r09hm0zj113hKCSIZyQh1J1HRSxyx R7dWNLgvhcsq5iHUbagxB7jExjGNJcWqUrwJYC16294v/s6iR4BBV7FAppXPW+7QYRb1 3eHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc; bh=8r/DVsdQ9Z1jAtpgwSIe7wtgj33LBSoM3OtCS4E6yq4=; b=voXGQIRZDDxC6QpyF/T8c9ma7x74D5kDFYlCFHSrXCAglBj/ZIEW+QklcHfZx0k/t7 YjzmjnqI0aF3ntuhE2Iy13qcM4RfArMy586yu6+dBkJHoxtA7bL/QSHvpt8zrOxQDYAg HI58XKGKdkPQVwjcIUxxgLH6LHBXTC47fnkBMsoJ/kjNG6QligPaaOdMx9f14IVbz3r1 UUJFZrx0DgXINY6BauS2GusTJM0sEOKelL6ysNA+MxXLKEmLi0uF59JLR2aCkOOB5CBE EW5KHeibszt8KH+8+cKfpYHmlt0+9XPQ22v+p549LOW/psMf3hAZPELNcQFRb9hUMQt7 3R2Q== X-Gm-Message-State: ACgBeo0sTZx3xfeDtsRWRye/1p91T/vfUbUtAZNR3G8242sQlAlvbBzZ f+XdnolDqZe6v4NTfs9/otvMqQ== X-Google-Smtp-Source: AA6agR74QzP1e3Avd4hHxUb5O3LhC2zpobuU5kASxmqALrogv0JGdtvHnsa+Imk3t6N/cHHODQZj2g== X-Received: by 2002:a05:6808:3098:b0:343:2d83:5978 with SMTP id bl24-20020a056808309800b003432d835978mr2480216oib.35.1660878595422; Thu, 18 Aug 2022 20:09:55 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Andrew Jones Subject: [PATCH] target/riscv: Use official extension names for AIA CSRs Date: Fri, 19 Aug 2022 08:39:38 +0530 Message-Id: <20220819030938.166196-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=apatel@ventanamicro.com; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1660878700939100001 Content-Type: text/plain; charset="utf-8" The arch review of AIA spec is completed and we now have official extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode AIA CSRs). Refer, section 1.6 of the latest AIA v0.3.1 stable specification at https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-i= nterrupts-032.pdf) Based on above, we update QEMU RISC-V to: 1) Have separate config options for Smaia and Ssaia extensions which replace RISCV_FEATURE_AIA in CPU features 2) Not generate AIA INTC compatible string in virt machine Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- hw/intc/riscv_imsic.c | 4 +++- hw/riscv/virt.c | 13 ++----------- target/riscv/cpu.c | 9 ++++----- target/riscv/cpu.h | 4 ++-- target/riscv/cpu_helper.c | 30 ++++++++++++++++++++++-------- target/riscv/csr.c | 30 ++++++++++++++++++++++++------ 6 files changed, 57 insertions(+), 33 deletions(-) diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 8615e4cc1d..4d4d5b50ca 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -344,9 +344,11 @@ static void riscv_imsic_realize(DeviceState *dev, Erro= r **errp) =20 /* Force select AIA feature and setup CSR read-modify-write callback */ if (env) { - riscv_set_feature(env, RISCV_FEATURE_AIA); if (!imsic->mmode) { + rcpu->cfg.ext_ssaia =3D true; riscv_cpu_set_geilen(env, imsic->num_pages - 1); + } else { + rcpu->cfg.ext_smaia =3D true; } riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S, riscv_imsic_rmw, imsic); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e779d399ae..b041b33afc 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -261,17 +261,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, = int socket, qemu_fdt_add_subnode(mc->fdt, intc_name); qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", intc_phandles[cpu]); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_AIA)) { - static const char * const compat[2] =3D { - "riscv,cpu-intc-aia", "riscv,cpu-intc" - }; - qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible", - (char **)&compat, ARRAY_SIZE(compat)= ); - } else { - qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", - "riscv,cpu-intc"); - } + qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", + "riscv,cpu-intc"); qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL,= 0); qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d11113fbaa..3cf0c86661 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -101,6 +101,8 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), @@ -669,10 +671,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) } } =20 - if (cpu->cfg.aia) { - riscv_set_feature(env, RISCV_FEATURE_AIA); - } - if (cpu->cfg.debug) { riscv_set_feature(env, RISCV_FEATURE_DEBUG); } @@ -1058,7 +1056,8 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), - DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), + DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), + DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), =20 DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 42edfa4558..15cad73def 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -85,7 +85,6 @@ enum { RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, RISCV_FEATURE_MISA, - RISCV_FEATURE_AIA, RISCV_FEATURE_DEBUG }; =20 @@ -452,6 +451,8 @@ struct RISCVCPUConfig { bool ext_zve64f; bool ext_zmmul; bool ext_sscofpmf; + bool ext_smaia; + bool ext_ssaia; bool rvv_ta_all_1s; bool rvv_ma_all_1s; =20 @@ -472,7 +473,6 @@ struct RISCVCPUConfig { bool mmu; bool pmp; bool epmp; - bool aia; bool debug; uint64_t resetvec; =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 81948b37dd..92685947d9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -305,7 +305,7 @@ uint8_t riscv_cpu_default_priority(int irq) return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; }; =20 -static int riscv_cpu_pending_to_irq(CPURISCVState *env, +static int riscv_cpu_pending_to_irq(CPURISCVState *env, bool has_aia, int extirq, unsigned int extirq_def_pr= io, uint64_t pending, uint8_t *iprio) { @@ -317,7 +317,7 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, } =20 irq =3D ctz64(pending); - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + if (!has_aia) { return irq; } =20 @@ -354,34 +354,45 @@ uint64_t riscv_cpu_all_pending(CPURISCVState *env) =20 int riscv_cpu_mirq_pending(CPURISCVState *env) { + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); uint64_t irqs =3D riscv_cpu_all_pending(env) & ~env->mideleg & ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); =20 - return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, + return riscv_cpu_pending_to_irq(env, cpu->cfg.ext_smaia, + IRQ_M_EXT, IPRIO_DEFAULT_M, irqs, env->miprio); } =20 int riscv_cpu_sirq_pending(CPURISCVState *env) { + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); =20 - return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + return riscv_cpu_pending_to_irq(env, cpu->cfg.ext_ssaia, + IRQ_S_EXT, IPRIO_DEFAULT_S, irqs, env->siprio); } =20 int riscv_cpu_vsirq_pending(CPURISCVState *env) { + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); =20 - return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + return riscv_cpu_pending_to_irq(env, cpu->cfg.ext_ssaia, + IRQ_S_EXT, IPRIO_DEFAULT_S, irqs >> 1, env->hviprio); } =20 static int riscv_cpu_local_irq_pending(CPURISCVState *env) { int virq; + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); uint64_t irqs, pending, mie, hsie, vsie; =20 /* Determine interrupt enable state of all privilege modes */ @@ -404,21 +415,24 @@ static int riscv_cpu_local_irq_pending(CPURISCVState = *env) /* Check M-mode interrupts */ irqs =3D pending & ~env->mideleg & -mie; if (irqs) { - return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, + return riscv_cpu_pending_to_irq(env, cpu->cfg.ext_smaia, + IRQ_M_EXT, IPRIO_DEFAULT_M, irqs, env->miprio); } =20 /* Check HS-mode interrupts */ irqs =3D pending & env->mideleg & ~env->hideleg & -hsie; if (irqs) { - return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + return riscv_cpu_pending_to_irq(env, cpu->cfg.ext_ssaia, + IRQ_S_EXT, IPRIO_DEFAULT_S, irqs, env->siprio); } =20 /* Check VS-mode interrupts */ irqs =3D pending & env->mideleg & env->hideleg & -vsie; if (irqs) { - virq =3D riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + virq =3D riscv_cpu_pending_to_irq(env, cpu->cfg.ext_ssaia, + IRQ_S_EXT, IPRIO_DEFAULT_S, irqs >> 1, env->hviprio); return (virq <=3D 0) ? virq : virq + 1; } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2dcd4e5b2d..b9bce9821f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -181,7 +181,10 @@ static RISCVException any32(CPURISCVState *env, int cs= rno) =20 static int aia_any(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -190,7 +193,10 @@ static int aia_any(CPURISCVState *env, int csrno) =20 static int aia_any32(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -217,7 +223,10 @@ static int smode32(CPURISCVState *env, int csrno) =20 static int aia_smode(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -226,7 +235,10 @@ static int aia_smode(CPURISCVState *env, int csrno) =20 static int aia_smode32(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -282,7 +294,10 @@ static RISCVException pointer_masking(CPURISCVState *e= nv, int csrno) =20 static int aia_hmode(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -291,7 +306,10 @@ static int aia_hmode(CPURISCVState *env, int csrno) =20 static int aia_hmode32(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 --=20 2.34.1