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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661212341562100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 ++ target/arm/translate.h | 6 ++++ target/arm/cpu.c | 23 +++++++------- target/arm/translate-a64.c | 37 ++++++++++++++++++----- target/arm/translate.c | 62 ++++++++++++++++++++++++++++++-------- 5 files changed, 100 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 68ffb12427..ef62371d8f 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -34,4 +34,6 @@ =20 #define NB_MMU_MODES 15 =20 +#define TARGET_TB_PCREL 1 + #endif diff --git a/target/arm/translate.h b/target/arm/translate.h index d42059aa1d..7717ea3f45 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -12,6 +12,12 @@ typedef struct DisasContext { =20 /* The address of the current instruction being translated. */ target_ulong pc_curr; + /* + * For TARGET_TB_PCREL, the value relative to pc_curr against which + * offsets must be computed for cpu_pc. -1 if unknown due to jump. + */ + target_ulong pc_save; + target_ulong pc_cond_save; target_ulong page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 047bf3f4ab..f5e74b6c3b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -64,17 +64,18 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* - * It's OK to look at env for the current mode here, because it's - * never possible for an AArch64 TB to chain to an AArch32 TB. - */ - if (is_a64(env)) { - env->pc =3D tb_pc(tb); - } else { - env->regs[15] =3D tb_pc(tb); + /* The program counter is always up to date with TARGET_TB_PCREL. */ + if (!TARGET_TB_PCREL) { + CPUARMState *env =3D cs->env_ptr; + /* + * It's OK to look at env for the current mode here, because it's + * never possible for an AArch64 TB to chain to an AArch32 TB. + */ + if (is_a64(env)) { + env->pc =3D tb_pc(tb); + } else { + env->regs[15] =3D tb_pc(tb); + } } } #endif /* CONFIG_TCG */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 322a09c503..a433189722 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -150,12 +150,18 @@ static void reset_btype(DisasContext *s) =20 static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, int diff) { - tcg_gen_movi_i64(dest, s->pc_curr + diff); + assert(s->pc_save !=3D -1); + if (TARGET_TB_PCREL) { + tcg_gen_addi_i64(dest, cpu_pc, (s->pc_curr - s->pc_save) + diff); + } else { + tcg_gen_movi_i64(dest, s->pc_curr + diff); + } } =20 void gen_a64_update_pc(DisasContext *s, int diff) { gen_pc_plus_diff(s, cpu_pc, diff); + s->pc_save =3D s->pc_curr + diff; } =20 /* @@ -209,6 +215,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr= c) * then loading an address into the PC will clear out any tag. */ gen_top_byte_ignore(s, cpu_pc, src, s->tbii); + s->pc_save =3D -1; } =20 /* @@ -347,16 +354,22 @@ static void gen_exception_internal(int excp) =20 static void gen_exception_internal_insn(DisasContext *s, int pc_diff, int = excp) { + target_ulong pc_save =3D s->pc_save; + gen_a64_update_pc(s, pc_diff); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; + s->pc_save =3D pc_save; } =20 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) { + target_ulong pc_save =3D s->pc_save; + gen_a64_update_pc(s, 0); gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome)); s->base.is_jmp =3D DISAS_NORETURN; + s->pc_save =3D pc_save; } =20 static void gen_step_complete_exception(DisasContext *s) @@ -385,11 +398,16 @@ static inline bool use_goto_tb(DisasContext *s, uint6= 4_t dest) =20 static void gen_goto_tb(DisasContext *s, int n, int diff) { - uint64_t dest =3D s->pc_curr + diff; + target_ulong pc_save =3D s->pc_save; =20 - if (use_goto_tb(s, dest)) { - tcg_gen_goto_tb(n); - gen_a64_update_pc(s, diff); + if (use_goto_tb(s, s->pc_curr + diff)) { + if (TARGET_TB_PCREL) { + gen_a64_update_pc(s, diff); + tcg_gen_goto_tb(n); + } else { + tcg_gen_goto_tb(n); + gen_a64_update_pc(s, diff); + } tcg_gen_exit_tb(s->base.tb, n); s->base.is_jmp =3D DISAS_NORETURN; } else { @@ -401,6 +419,7 @@ static void gen_goto_tb(DisasContext *s, int n, int dif= f) s->base.is_jmp =3D DISAS_NORETURN; } } + s->pc_save =3D pc_save; } =20 static void init_tmp_a64_array(DisasContext *s) @@ -14717,7 +14736,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, =20 dc->isar =3D &arm_cpu->isar; dc->condjmp =3D 0; - + dc->pc_save =3D dc->base.pc_first; dc->aarch64 =3D true; dc->thumb =3D false; dc->sctlr_b =3D 0; @@ -14799,8 +14818,12 @@ static void aarch64_tr_tb_start(DisasContextBase *= db, CPUState *cpu) static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong pc_arg =3D dc->base.pc_next; =20 - tcg_gen_insn_start(dc->base.pc_next, 0, 0); + if (TARGET_TB_PCREL) { + pc_arg &=3D ~TARGET_PAGE_MASK; + } + tcg_gen_insn_start(pc_arg, 0, 0); dc->insn_start =3D tcg_last_op(); } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index f01c8df60a..a25ba48e87 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -164,6 +164,7 @@ void arm_gen_condlabel(DisasContext *s) if (!s->condjmp) { s->condlabel =3D gen_new_label(); s->condjmp =3D 1; + s->pc_cond_save =3D s->pc_save; } } =20 @@ -278,7 +279,12 @@ static int jmp_diff(DisasContext *s, int diff) =20 static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, int diff) { - tcg_gen_movi_i32(var, s->pc_curr + diff); + assert(s->pc_save !=3D -1); + if (TARGET_TB_PCREL) { + tcg_gen_addi_i32(var, cpu_R[15], (s->pc_curr - s->pc_save) + diff); + } else { + tcg_gen_movi_i32(var, s->pc_curr + diff); + } } =20 /* Set a variable to the value of a CPU register. */ @@ -321,6 +327,7 @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var) */ tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); s->base.is_jmp =3D DISAS_JUMP; + s->pc_save =3D -1; } else if (reg =3D=3D 13 && arm_dc_feature(s, ARM_FEATURE_M)) { /* For M-profile SP bits [1:0] are always zero */ tcg_gen_andi_i32(var, var, ~3); @@ -786,7 +793,8 @@ void gen_set_condexec(DisasContext *s) =20 void gen_update_pc(DisasContext *s, int diff) { - tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff); + gen_pc_plus_diff(s, cpu_R[15], diff); + s->pc_save =3D s->pc_curr + diff; } =20 /* Set PC and Thumb state from var. var is marked as dead. */ @@ -796,6 +804,7 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var) tcg_gen_andi_i32(cpu_R[15], var, ~1); tcg_gen_andi_i32(var, var, 1); store_cpu_field(var, thumb); + s->pc_save =3D -1; } =20 /* @@ -1118,6 +1127,8 @@ static void gen_exception(int excp, uint32_t syndrome) static void gen_exception_insn_el_v(DisasContext *s, int pc_diff, int excp, uint32_t syn, TCGv_i32 tcg_el) { + target_ulong pc_save =3D s->pc_save; + if (s->aarch64) { gen_a64_update_pc(s, pc_diff); } else { @@ -1126,6 +1137,7 @@ static void gen_exception_insn_el_v(DisasContext *s, = int pc_diff, int excp, } gen_exception_el_v(excp, syn, tcg_el); s->base.is_jmp =3D DISAS_NORETURN; + s->pc_save =3D pc_save; } =20 void gen_exception_insn_el(DisasContext *s, int pc_diff, int excp, @@ -1137,6 +1149,8 @@ void gen_exception_insn_el(DisasContext *s, int pc_di= ff, int excp, =20 void gen_exception_insn(DisasContext *s, int pc_diff, int excp, uint32_t s= yn) { + target_ulong pc_save =3D s->pc_save; + if (s->aarch64) { gen_a64_update_pc(s, pc_diff); } else { @@ -1145,6 +1159,7 @@ void gen_exception_insn(DisasContext *s, int pc_diff,= int excp, uint32_t syn) } gen_exception(excp, syn); s->base.is_jmp =3D DISAS_NORETURN; + s->pc_save =3D pc_save; } =20 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) @@ -2612,11 +2627,14 @@ static void gen_goto_ptr(void) */ static void gen_goto_tb(DisasContext *s, int n, int diff) { - target_ulong dest =3D s->pc_curr + diff; - - if (translator_use_goto_tb(&s->base, dest)) { - tcg_gen_goto_tb(n); - gen_update_pc(s, diff); + if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) { + if (TARGET_TB_PCREL) { + gen_update_pc(s, diff); + tcg_gen_goto_tb(n); + } else { + tcg_gen_goto_tb(n); + gen_update_pc(s, diff); + } tcg_gen_exit_tb(s->base.tb, n); } else { gen_update_pc(s, diff); @@ -2628,10 +2646,13 @@ static void gen_goto_tb(DisasContext *s, int n, int= diff) /* Jump, specifying which TB number to use if we gen_goto_tb() */ static void gen_jmp_tb(DisasContext *s, int diff, int tbno) { + target_ulong pc_save =3D s->pc_save; + if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. = */ gen_update_pc(s, diff); s->base.is_jmp =3D DISAS_JUMP; + s->pc_save =3D pc_save; return; } switch (s->base.is_jmp) { @@ -2667,6 +2688,7 @@ static void gen_jmp_tb(DisasContext *s, int diff, int= tbno) */ g_assert_not_reached(); } + s->pc_save =3D pc_save; } =20 static inline void gen_jmp(DisasContext *s, int diff) @@ -9333,7 +9355,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) =20 dc->isar =3D &cpu->isar; dc->condjmp =3D 0; - + dc->pc_save =3D dc->base.pc_first; dc->aarch64 =3D false; dc->thumb =3D EX_TBFLAG_AM32(tb_flags, THUMB); dc->be_data =3D EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; @@ -9488,13 +9510,17 @@ static void arm_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) * fields here. */ uint32_t condexec_bits; + target_ulong pc_arg =3D dc->base.pc_next; =20 + if (TARGET_TB_PCREL) { + pc_arg &=3D ~TARGET_PAGE_MASK; + } if (dc->eci) { condexec_bits =3D dc->eci << 4; } else { condexec_bits =3D (dc->condexec_cond << 4) | (dc->condexec_mask >>= 1); } - tcg_gen_insn_start(dc->base.pc_next, condexec_bits, 0); + tcg_gen_insn_start(pc_arg, condexec_bits, 0); dc->insn_start =3D tcg_last_op(); } =20 @@ -9537,7 +9563,10 @@ static bool arm_check_ss_active(DisasContext *dc) =20 static void arm_post_translate_insn(DisasContext *dc) { - if (dc->condjmp && !dc->base.is_jmp) { + if (dc->condjmp && dc->base.is_jmp =3D=3D DISAS_NEXT) { + if (dc->pc_save !=3D dc->pc_cond_save) { + gen_update_pc(dc, dc->pc_cond_save - dc->pc_save); + } gen_set_label(dc->condlabel); dc->condjmp =3D 0; } @@ -9867,6 +9896,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) =20 if (dc->condjmp) { /* "Condition failed" instruction codepath for the branch/trap ins= n */ + dc->pc_save =3D dc->pc_cond_save; gen_set_label(dc->condlabel); gen_set_condexec(dc); if (unlikely(dc->ss_active)) { @@ -9929,11 +9959,19 @@ void restore_state_to_opc(CPUARMState *env, Transla= tionBlock *tb, target_ulong *data) { if (is_a64(env)) { - env->pc =3D data[0]; + if (TARGET_TB_PCREL) { + env->pc =3D (env->pc & TARGET_PAGE_MASK) | data[0]; + } else { + env->pc =3D data[0]; + } env->condexec_bits =3D 0; env->exception.syndrome =3D data[2] << ARM_INSN_START_WORD2_SHIFT; } else { - env->regs[15] =3D data[0]; + if (TARGET_TB_PCREL) { + env->regs[15] =3D (env->regs[15] & TARGET_PAGE_MASK) | data[0]; + } else { + env->regs[15] =3D data[0]; + } env->condexec_bits =3D data[1]; env->exception.syndrome =3D data[2] << ARM_INSN_START_WORD2_SHIFT; } --=20 2.34.1