From nobody Mon May 13 13:25:30 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1661379852; cv=none; d=zohomail.com; s=zohoarc; b=VUs+TI441ag/GGD0y0mpHjBNUwKxuRSCe4chTrveUKQsFgTk/m7QgiLqc9rpfmxw3fzWzvhmkXaKVXFPyHkEAXK+bT+hFoS1vewgQf8KNPlqOtOoPndUaMfk6yCEI9hQBtjAzTbmxkdFxXO80wehdtVx1HD53ZX2A1RqHr4QYG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661379852; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aUYOKvvKL+Tdyq9E/RDdPIyvQdebrRAqCm6dW5ivjI0=; b=DGNkStG6MQKW3/SE0s+WuW7WOb/NPaJXJFwxi4k0khm0NzG7xuEF1xhaQu9/bhnhZzVRPGqQAlN+1VqvQVx0TTNC9AMr/E3+z3lMZnyFu8fd5VeWDRXeDG7xthnOG1dG2goNoDi2HSYnEeCyv0yc7CjlNUud9U6f+E5s0ubzxD4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661379852017484.58211240834726; Wed, 24 Aug 2022 15:24:12 -0700 (PDT) Received: from localhost ([::1]:38306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQynC-0004Z6-Pq for importer2@patchew.org; Wed, 24 Aug 2022 18:24:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQyhE-0008QO-89 for qemu-devel@nongnu.org; Wed, 24 Aug 2022 18:18:01 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:38736) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQygy-0006bZ-PR for qemu-devel@nongnu.org; Wed, 24 Aug 2022 18:17:59 -0400 Received: by mail-pj1-x102a.google.com with SMTP id s31-20020a17090a2f2200b001faaf9d92easo3030931pjd.3 for ; Wed, 24 Aug 2022 15:17:44 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id h18-20020a170902f71200b0016909be39e5sm4243031plo.177.2022.08.24.15.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 15:17:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=aUYOKvvKL+Tdyq9E/RDdPIyvQdebrRAqCm6dW5ivjI0=; b=WI3/0UZl2pboAzgFJ6iNHI5UODO/50SRXC2EAjU9hkJWz2VX7NlLtf6wc1aCke40V5 5XA4SVSVgOfcZGek7qsSK2MINqhUW53+jWkN/otuYut3u19I9hYQx6kA9rjRhdPiwAZ3 o2PNVPSqPT3naCJHUmJuSdwset0zQN9xrJBZzFviT0F9NEcXAmjj2k8iV8FPAqdKD7H7 rysfWv5gwt/hABON2trY6N0C3KgI2Xg8z7yUMx1lp7xINbm5nesmASlB7tIH0+A1Lf/X z54fOZBa7X4jxWW3BT+NWPs8DKnL+v5nJBBwEAxxQQy2EArMlWlJQKiYXygLusbnr0fl 5RFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=aUYOKvvKL+Tdyq9E/RDdPIyvQdebrRAqCm6dW5ivjI0=; b=mN0a40OtS0WE1k4tNE0Cif5OfQVuTvmgsBsLpzMNUNg9uFr0Rp8uElQ20n2ZKhWf3I dRQ335n6ujnc1rCgn4fLMaNluNnD5q31iRYP7E7MfQ/eT4Kd+aGZ3CLKoUJMyizZas0N 3G76UbbNABfPdbn2MFWBoRNNbq8rt1jgDN2eFGQ8ruloG74B0wTX5bMVY0zPt98p+qLx WHVPv3f7iSXvOtBtwzgo64r7iRIWeHgsVavg1Bq79mL0RTnrGwglhGWuTqLej+t8WmGl C5YOPyW8btiNVQmCtFTd5cUWaUmGJ/QUvT6/2f4MZ7iaQQA6DNDaCeyQFzKkPh5ZHjOT 46fg== X-Gm-Message-State: ACgBeo3xqeVbQ2cRLeCQbW4mb6a7KvLp65vdu0blqyMJaBPMunDpkK2k 2CBeqcHxMLpME+kKYTU7da4SYl3WAXbddA== X-Google-Smtp-Source: AA6agR5CY9rZVF73VLVBEJKJPrL9+q4KAqstff3NikH8TONjgJc2VZe5Eo77AVA2lE65hGX1E9Tq1g== X-Received: by 2002:a17:90b:3807:b0:1f4:ecf7:5987 with SMTP id mq7-20020a17090b380700b001f4ecf75987mr1177801pjb.13.1661379463001; Wed, 24 Aug 2022 15:17:43 -0700 (PDT) From: Atish Patra To: qemu-devel@nongnu.org Cc: Heiko Stuebner , Alistair Francis , Atish Patra , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v14 1/5] target/riscv: Add sscofpmf extension support Date: Wed, 24 Aug 2022 15:16:57 -0700 Message-Id: <20220824221701.41932-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220824221701.41932-1-atishp@rivosinc.com> References: <20220824221701.41932-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1661379853330100001 Content-Type: text/plain; charset="utf-8" The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) extension allows the perf to handle overflow interrupts and filtering support. This patch provides a framework for programmable counters to leverage the extension. As the extension doesn't have any provision for the overflow bit for fixed counters, the fixed events can also be monitoring using programmable counters. The underlying counters for cycle and instruction counters are always running. Thus, a separate timer device is programmed to handle the overflow. Tested-by: Heiko Stuebner Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 ++++++ target/riscv/csr.c | 166 +++++++++++++++++- target/riscv/machine.c | 1 + target/riscv/pmu.c | 368 +++++++++++++++++++++++++++++++++++++++- target/riscv/pmu.h | 7 + 7 files changed, 623 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8ab36e82e190..aee14a239af8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "cpu.h" +#include "pmu.h" #include "internals.h" #include "time_helper.h" #include "exec/exec-all.h" @@ -102,6 +103,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), + ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), @@ -889,6 +891,15 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) set_misa(env, env->misa_mxl, ext); } =20 +#ifndef CONFIG_USER_ONLY + if (cpu->cfg.pmu_num) { + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + riscv_pmu_timer_cb, cpu); + } + } +#endif + riscv_cpu_register_gdb_regs_for_features(cs); =20 qemu_init_vcpu(cs); @@ -993,6 +1004,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), + DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d895a0af2c6d..06751e1e3e18 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -136,6 +136,8 @@ typedef struct PMUCTRState { /* Snapshort value of a counter in RV32 */ target_ulong mhpmcounterh_prev; bool started; + /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigge= r */ + target_ulong irq_overflow_left; } PMUCTRState; =20 struct CPUArchState { @@ -301,6 +303,9 @@ struct CPUArchState { /* PMU event selector configured values. First three are unused*/ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; =20 + /* PMU event selector configured values for RV32*/ + target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; + target_ulong sscratch; target_ulong mscratch; =20 @@ -447,6 +452,7 @@ struct RISCVCPUConfig { bool ext_zmmul; bool ext_smaia; bool ext_ssaia; + bool ext_sscofpmf; bool rvv_ta_all_1s; bool rvv_ma_all_1s; =20 @@ -493,6 +499,12 @@ struct ArchCPU { =20 /* Configuration Settings */ RISCVCPUConfig cfg; + + QEMUTimer *pmu_timer; + /* A bitmask of Available programmable counters */ + uint32_t pmu_avail_ctrs; + /* Mapping of events to counters */ + GHashTable *pmu_event_ctr_map; }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) @@ -753,6 +765,19 @@ enum { CSR_TABLE_SIZE =3D 0x1000 }; =20 +/** + * The event id are encoded based on the encoding specified in the + * SBI specification v0.3 + */ + +enum riscv_pmu_event_idx { + RISCV_PMU_EVENT_HW_CPU_CYCLES =3D 0x01, + RISCV_PMU_EVENT_HW_INSTRUCTIONS =3D 0x02, + RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS =3D 0x10019, + RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS =3D 0x1001B, + RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, +}; + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 095dab19f512..7be12cac2ee6 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -390,6 +390,37 @@ #define CSR_MHPMEVENT29 0x33d #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f + +#define CSR_MHPMEVENT3H 0x723 +#define CSR_MHPMEVENT4H 0x724 +#define CSR_MHPMEVENT5H 0x725 +#define CSR_MHPMEVENT6H 0x726 +#define CSR_MHPMEVENT7H 0x727 +#define CSR_MHPMEVENT8H 0x728 +#define CSR_MHPMEVENT9H 0x729 +#define CSR_MHPMEVENT10H 0x72a +#define CSR_MHPMEVENT11H 0x72b +#define CSR_MHPMEVENT12H 0x72c +#define CSR_MHPMEVENT13H 0x72d +#define CSR_MHPMEVENT14H 0x72e +#define CSR_MHPMEVENT15H 0x72f +#define CSR_MHPMEVENT16H 0x730 +#define CSR_MHPMEVENT17H 0x731 +#define CSR_MHPMEVENT18H 0x732 +#define CSR_MHPMEVENT19H 0x733 +#define CSR_MHPMEVENT20H 0x734 +#define CSR_MHPMEVENT21H 0x735 +#define CSR_MHPMEVENT22H 0x736 +#define CSR_MHPMEVENT23H 0x737 +#define CSR_MHPMEVENT24H 0x738 +#define CSR_MHPMEVENT25H 0x739 +#define CSR_MHPMEVENT26H 0x73a +#define CSR_MHPMEVENT27H 0x73b +#define CSR_MHPMEVENT28H 0x73c +#define CSR_MHPMEVENT29H 0x73d +#define CSR_MHPMEVENT30H 0x73e +#define CSR_MHPMEVENT31H 0x73f + #define CSR_MHPMCOUNTER3H 0xb83 #define CSR_MHPMCOUNTER4H 0xb84 #define CSR_MHPMCOUNTER5H 0xb85 @@ -451,6 +482,7 @@ #define CSR_VSMTE 0x2c0 #define CSR_VSPMMASK 0x2c1 #define CSR_VSPMBASE 0x2c2 +#define CSR_SCOUNTOVF 0xda0 =20 /* Crypto Extension */ #define CSR_SEED 0x015 @@ -628,6 +660,7 @@ typedef enum RISCVException { #define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 #define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 #define IRQ_LOCAL_MAX 16 #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) =20 @@ -645,11 +678,13 @@ typedef enum RISCVException { #define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) #define MIP_SGEIP (1 << IRQ_S_GEXT) +#define MIP_LCOFIP (1 << IRQ_PMU_OVF) =20 /* sip masks */ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP +#define SIP_LCOFIP MIP_LCOFIP =20 /* MIE masks */ #define MIE_SEIE (1 << IRQ_S_EXT) @@ -803,4 +838,24 @@ typedef enum RISCVException { #define SEED_OPST_WAIT (0b01 << 30) #define SEED_OPST_ES16 (0b10 << 30) #define SEED_OPST_DEAD (0b11 << 30) +/* PMU related bits */ +#define MIE_LCOFIE (1 << IRQ_PMU_OVF) + +#define MHPMEVENT_BIT_OF BIT_ULL(63) +#define MHPMEVENTH_BIT_OF BIT(31) +#define MHPMEVENT_BIT_MINH BIT_ULL(62) +#define MHPMEVENTH_BIT_MINH BIT(30) +#define MHPMEVENT_BIT_SINH BIT_ULL(61) +#define MHPMEVENTH_BIT_SINH BIT(29) +#define MHPMEVENT_BIT_UINH BIT_ULL(60) +#define MHPMEVENTH_BIT_UINH BIT(28) +#define MHPMEVENT_BIT_VSINH BIT_ULL(59) +#define MHPMEVENTH_BIT_VSINH BIT(27) +#define MHPMEVENT_BIT_VUINH BIT_ULL(58) +#define MHPMEVENTH_BIT_VUINH BIT(26) + +#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) +#define MHPMEVENT_IDX_MASK 0xFFFFF +#define MHPMEVENT_SSCOF_RESVD 16 + #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1a35ac48ccbe..888ddfc4dd4b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -75,7 +75,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); int ctr_index; - int base_csrno =3D CSR_HPMCOUNTER3; + int base_csrno =3D CSR_CYCLE; bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? true : false; =20 if (rv32 && csrno >=3D CSR_CYCLEH) { @@ -84,11 +84,18 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } ctr_index =3D csrno - base_csrno; =20 - if (!cpu->cfg.pmu_num || ctr_index >=3D (cpu->cfg.pmu_num)) { + if ((csrno >=3D CSR_CYCLE && csrno <=3D CSR_INSTRET) || + (csrno >=3D CSR_CYCLEH && csrno <=3D CSR_INSTRETH)) { + goto skip_ext_pmu_check; + } + + if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) { /* No counter is enabled in PMU or the counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } =20 +skip_ext_pmu_check: + if (env->priv =3D=3D PRV_S) { switch (csrno) { case CSR_CYCLE: @@ -107,7 +114,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - ctr_index =3D csrno - CSR_CYCLE; if (!get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -131,7 +137,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - ctr_index =3D csrno - CSR_CYCLEH; if (!get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -161,7 +166,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - ctr_index =3D csrno - CSR_CYCLE; if (!get_field(env->hcounteren, 1 << ctr_index) && get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -189,7 +193,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - ctr_index =3D csrno - CSR_CYCLEH; if (!get_field(env->hcounteren, 1 << ctr_index) && get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -241,6 +244,18 @@ static RISCVException mctr32(CPURISCVState *env, int c= srno) return mctr(env, csrno); } =20 +static RISCVException sscofpmf(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_sscofpmf) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +} + static RISCVException any(CPURISCVState *env, int csrno) { return RISCV_EXCP_NONE; @@ -683,9 +698,39 @@ static int read_mhpmevent(CPURISCVState *env, int csrn= o, target_ulong *val) static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) { int evt_index =3D csrno - CSR_MCOUNTINHIBIT; + uint64_t mhpmevt_val =3D val; =20 env->mhpmevent_val[evt_index] =3D val; =20 + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + mhpmevt_val =3D mhpmevt_val | + ((uint64_t)env->mhpmeventh_val[evt_index] << 32); + } + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + + return RISCV_EXCP_NONE; +} + +static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; + + *val =3D env->mhpmeventh_val[evt_index]; + + return RISCV_EXCP_NONE; +} + +static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong va= l) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; + uint64_t mhpmevth_val =3D val; + uint64_t mhpmevt_val =3D env->mhpmevent_val[evt_index]; + + mhpmevt_val =3D mhpmevt_val | (mhpmevth_val << 32); + env->mhpmeventh_val[evt_index] =3D val; + + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + return RISCV_EXCP_NONE; } =20 @@ -693,12 +738,20 @@ static int write_mhpmcounter(CPURISCVState *env, int = csrno, target_ulong val) { int ctr_idx =3D csrno - CSR_MCYCLE; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + uint64_t mhpmctr_val =3D val; =20 counter->mhpmcounter_val =3D val; if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { counter->mhpmcounter_prev =3D get_ticks(false); - } else { + if (ctr_idx > 2) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + mhpmctr_val =3D mhpmctr_val | + ((uint64_t)counter->mhpmcounterh_val << 32); + } + riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); + } + } else { /* Other counters can keep incrementing from the given value */ counter->mhpmcounter_prev =3D val; } @@ -710,11 +763,17 @@ static int write_mhpmcounterh(CPURISCVState *env, int= csrno, target_ulong val) { int ctr_idx =3D csrno - CSR_MCYCLEH; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + uint64_t mhpmctr_val =3D counter->mhpmcounter_val; + uint64_t mhpmctrh_val =3D val; =20 counter->mhpmcounterh_val =3D val; + mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { counter->mhpmcounterh_prev =3D get_ticks(true); + if (ctr_idx > 2) { + riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); + } } else { counter->mhpmcounterh_prev =3D val; } @@ -790,6 +849,32 @@ static int read_hpmcounterh(CPURISCVState *env, int cs= rno, target_ulong *val) return riscv_pmu_read_ctr(env, val, true, ctr_index); } =20 +static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val) +{ + int mhpmevt_start =3D CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT; + int i; + *val =3D 0; + target_ulong *mhpm_evt_val; + uint64_t of_bit_mask; + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + mhpm_evt_val =3D env->mhpmeventh_val; + of_bit_mask =3D MHPMEVENTH_BIT_OF; + } else { + mhpm_evt_val =3D env->mhpmevent_val; + of_bit_mask =3D MHPMEVENT_BIT_OF; + } + + for (i =3D mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) { + if ((get_field(env->mcounteren, BIT(i))) && + (mhpm_evt_val[i] & of_bit_mask)) { + *val |=3D BIT(i); + } + } + + return RISCV_EXCP_NONE; +} + static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) { @@ -969,7 +1054,8 @@ static RISCVException write_stimecmph(CPURISCVState *e= nv, int csrno, /* Machine constants */ =20 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) -#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) +#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP | \ + MIP_LCOFIP)) #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) =20 @@ -1010,7 +1096,8 @@ static const target_ulong vs_delegable_excps =3D DELE= GABLE_EXCPS & static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; -static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP; +static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP | + SIP_LCOFIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M= IP_VSEIP; static const target_ulong vsip_writable_mask =3D MIP_VSSIP; @@ -4071,6 +4158,65 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_mhpmevent, write_mhpmevent }, =20 + [CSR_MHPMEVENT3H] =3D { "mhpmevent3h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT4H] =3D { "mhpmevent4h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT5H] =3D { "mhpmevent5h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT6H] =3D { "mhpmevent6h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT7H] =3D { "mhpmevent7h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT8H] =3D { "mhpmevent8h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT9H] =3D { "mhpmevent9h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT10H] =3D { "mhpmevent10h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT11H] =3D { "mhpmevent11h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT12H] =3D { "mhpmevent12h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT13H] =3D { "mhpmevent13h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT14H] =3D { "mhpmevent14h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT15H] =3D { "mhpmevent15h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT16H] =3D { "mhpmevent16h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT17H] =3D { "mhpmevent17h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT18H] =3D { "mhpmevent18h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT19H] =3D { "mhpmevent19h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT20H] =3D { "mhpmevent20h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT21H] =3D { "mhpmevent21h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT22H] =3D { "mhpmevent22h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT23H] =3D { "mhpmevent23h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT24H] =3D { "mhpmevent24h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT25H] =3D { "mhpmevent25h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT26H] =3D { "mhpmevent26h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT27H] =3D { "mhpmevent27h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT28H] =3D { "mhpmevent28h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT29H] =3D { "mhpmevent29h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT30H] =3D { "mhpmevent30h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT31H] =3D { "mhpmevent31h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_hpmcounterh = }, [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_hpmcounterh = }, [CSR_HPMCOUNTER5H] =3D { "hpmcounter5h", ctr32, read_hpmcounterh = }, @@ -4159,5 +4305,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_mhpmcounterh }, [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", mctr32, read_hpmcounterh, write_mhpmcounterh }, + [CSR_SCOUNTOVF] =3D { "scountovf", sscofpmf, read_scountovf }, + #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 4ba55705d147..41098f6ad03a 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -356,6 +356,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, = 0, vmstate_pmu_ctr_state, PMUCTRState), VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENT= S), + VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVEN= TS), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 000fe8da45ef..a5f504e53c88 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -19,14 +19,378 @@ #include "qemu/osdep.h" #include "cpu.h" #include "pmu.h" +#include "sysemu/cpu-timers.h" + +#define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ +#define MAKE_32BIT_MASK(shift, length) \ + (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) + +static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) +{ + if (ctr_idx < 3 || ctr_idx >=3D RV_MAX_MHPMCOUNTERS || + !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) { + return false; + } else { + return true; + } +} + +static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx) +{ + CPURISCVState *env =3D &cpu->env; + + if (riscv_pmu_counter_valid(cpu, ctr_idx) && + !get_field(env->mcountinhibit, BIT(ctr_idx))) { + return true; + } else { + return false; + } +} + +static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx) +{ + CPURISCVState *env =3D &cpu->env; + target_ulong max_val =3D UINT32_MAX; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + bool virt_on =3D riscv_cpu_virt_enabled(env); + + /* Privilege mode filtering */ + if ((env->priv =3D=3D PRV_M && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) || + (env->priv =3D=3D PRV_S && virt_on && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) || + (env->priv =3D=3D PRV_U && virt_on && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VUINH)) || + (env->priv =3D=3D PRV_S && !virt_on && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) || + (env->priv =3D=3D PRV_U && !virt_on && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) { + return 0; + } + + /* Handle the overflow scenario */ + if (counter->mhpmcounter_val =3D=3D max_val) { + if (counter->mhpmcounterh_val =3D=3D max_val) { + counter->mhpmcounter_val =3D 0; + counter->mhpmcounterh_val =3D 0; + /* Generate interrupt only if OF bit is clear */ + if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) { + env->mhpmeventh_val[ctr_idx] |=3D MHPMEVENTH_BIT_OF; + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + } + } else { + counter->mhpmcounterh_val++; + } + } else { + counter->mhpmcounter_val++; + } + + return 0; +} + +static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx) +{ + CPURISCVState *env =3D &cpu->env; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + uint64_t max_val =3D UINT64_MAX; + bool virt_on =3D riscv_cpu_virt_enabled(env); + + /* Privilege mode filtering */ + if ((env->priv =3D=3D PRV_M && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || + (env->priv =3D=3D PRV_S && virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || + (env->priv =3D=3D PRV_U && virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || + (env->priv =3D=3D PRV_S && !virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || + (env->priv =3D=3D PRV_U && !virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { + return 0; + } + + /* Handle the overflow scenario */ + if (counter->mhpmcounter_val =3D=3D max_val) { + counter->mhpmcounter_val =3D 0; + /* Generate interrupt only if OF bit is clear */ + if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { + env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + } + } else { + counter->mhpmcounter_val++; + } + return 0; +} + +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) +{ + uint32_t ctr_idx; + int ret; + CPURISCVState *env =3D &cpu->env; + gpointer value; + + if (!cpu->cfg.pmu_num) { + return 0; + } + value =3D g_hash_table_lookup(cpu->pmu_event_ctr_map, + GUINT_TO_POINTER(event_idx)); + if (!value) { + return -1; + } + + ctr_idx =3D GPOINTER_TO_UINT(value); + if (!riscv_pmu_counter_enabled(cpu, ctr_idx) || + get_field(env->mcountinhibit, BIT(ctr_idx))) { + return -1; + } + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + ret =3D riscv_pmu_incr_ctr_rv32(cpu, ctr_idx); + } else { + ret =3D riscv_pmu_incr_ctr_rv64(cpu, ctr_idx); + } + + return ret; +} =20 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr) { - return (target_ctr =3D=3D 0) ? true : false; + RISCVCPU *cpu; + uint32_t event_idx; + uint32_t ctr_idx; + + /* Fixed instret counter */ + if (target_ctr =3D=3D 2) { + return true; + } + + cpu =3D RISCV_CPU(env_cpu(env)); + if (!cpu->pmu_event_ctr_map) { + return false; + } + + event_idx =3D RISCV_PMU_EVENT_HW_INSTRUCTIONS; + ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, + GUINT_TO_POINTER(event_idx))); + if (!ctr_idx) { + return false; + } + + return target_ctr =3D=3D ctr_idx ? true : false; } =20 bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) { - return (target_ctr =3D=3D 2) ? true : false; + RISCVCPU *cpu; + uint32_t event_idx; + uint32_t ctr_idx; + + /* Fixed mcycle counter */ + if (target_ctr =3D=3D 0) { + return true; + } + + cpu =3D RISCV_CPU(env_cpu(env)); + if (!cpu->pmu_event_ctr_map) { + return false; + } + + event_idx =3D RISCV_PMU_EVENT_HW_CPU_CYCLES; + ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, + GUINT_TO_POINTER(event_idx))); + + /* Counter zero is not used for event_ctr_map */ + if (!ctr_idx) { + return false; + } + + return (target_ctr =3D=3D ctr_idx) ? true : false; +} + +static gboolean pmu_remove_event_map(gpointer key, gpointer value, + gpointer udata) +{ + return (GPOINTER_TO_UINT(value) =3D=3D GPOINTER_TO_UINT(udata)) ? true= : false; +} + +static int64_t pmu_icount_ticks_to_ns(int64_t value) +{ + int64_t ret =3D 0; + + if (icount_enabled()) { + ret =3D icount_to_ns(value); + } else { + ret =3D (NANOSECONDS_PER_SECOND / RISCV_TIMEBASE_FREQ) * value; + } + + return ret; +} + +int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, + uint32_t ctr_idx) +{ + uint32_t event_idx; + RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + + if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map)= { + return -1; + } + + /* + * Expected mhpmevent value is zero for reset case. Remove the current + * mapping. + */ + if (!value) { + g_hash_table_foreach_remove(cpu->pmu_event_ctr_map, + pmu_remove_event_map, + GUINT_TO_POINTER(ctr_idx)); + return 0; + } + + event_idx =3D value & MHPMEVENT_IDX_MASK; + if (g_hash_table_lookup(cpu->pmu_event_ctr_map, + GUINT_TO_POINTER(event_idx))) { + return 0; + } + + switch (event_idx) { + case RISCV_PMU_EVENT_HW_CPU_CYCLES: + case RISCV_PMU_EVENT_HW_INSTRUCTIONS: + case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS: + case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS: + case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS: + break; + default: + /* We don't support any raw events right now */ + return -1; + } + g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx= ), + GUINT_TO_POINTER(ctr_idx)); + + return 0; +} + +static void pmu_timer_trigger_irq(RISCVCPU *cpu, + enum riscv_pmu_event_idx evt_idx) +{ + uint32_t ctr_idx; + CPURISCVState *env =3D &cpu->env; + PMUCTRState *counter; + target_ulong *mhpmevent_val; + uint64_t of_bit_mask; + int64_t irq_trigger_at; + + if (evt_idx !=3D RISCV_PMU_EVENT_HW_CPU_CYCLES && + evt_idx !=3D RISCV_PMU_EVENT_HW_INSTRUCTIONS) { + return; + } + + ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, + GUINT_TO_POINTER(evt_idx))); + if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) { + return; + } + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + mhpmevent_val =3D &env->mhpmeventh_val[ctr_idx]; + of_bit_mask =3D MHPMEVENTH_BIT_OF; + } else { + mhpmevent_val =3D &env->mhpmevent_val[ctr_idx]; + of_bit_mask =3D MHPMEVENT_BIT_OF; + } + + counter =3D &env->pmu_ctrs[ctr_idx]; + if (counter->irq_overflow_left > 0) { + irq_trigger_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + counter->irq_overflow_left; + timer_mod_anticipate_ns(cpu->pmu_timer, irq_trigger_at); + counter->irq_overflow_left =3D 0; + return; + } + + if (cpu->pmu_avail_ctrs & BIT(ctr_idx)) { + /* Generate interrupt only if OF bit is clear */ + if (!(*mhpmevent_val & of_bit_mask)) { + *mhpmevent_val |=3D of_bit_mask; + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + } + } +} + +/* Timer callback for instret and cycle counter overflow */ +void riscv_pmu_timer_cb(void *priv) +{ + RISCVCPU *cpu =3D priv; + + /* Timer event was triggered only for these events */ + pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES); + pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS); +} + +int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr= _idx) +{ + uint64_t overflow_delta, overflow_at; + int64_t overflow_ns, overflow_left =3D 0; + RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + + if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) { + return -1; + } + + if (value) { + overflow_delta =3D UINT64_MAX - value + 1; + } else { + overflow_delta =3D UINT64_MAX; + } + + /* + * QEMU supports only int64_t timers while RISC-V counters are uint64_= t. + * Compute the leftover and save it so that it can be reprogrammed aga= in + * when timer expires. + */ + if (overflow_delta > INT64_MAX) { + overflow_left =3D overflow_delta - INT64_MAX; + } + + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + overflow_ns =3D pmu_icount_ticks_to_ns((int64_t)overflow_delta); + overflow_left =3D pmu_icount_ticks_to_ns(overflow_left) ; + } else { + return -1; + } + overflow_at =3D (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + over= flow_ns; + + if (overflow_at > INT64_MAX) { + overflow_left +=3D overflow_at - INT64_MAX; + counter->irq_overflow_left =3D overflow_left; + overflow_at =3D INT64_MAX; + } + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + + return 0; +} + + +int riscv_pmu_init(RISCVCPU *cpu, int num_counters) +{ + if (num_counters > (RV_MAX_MHPMCOUNTERS - 3)) { + return -1; + } + + cpu->pmu_event_ctr_map =3D g_hash_table_new(g_direct_hash, g_direct_eq= ual); + if (!cpu->pmu_event_ctr_map) { + /* PMU support can not be enabled */ + qemu_log_mask(LOG_UNIMP, "PMU events can't be supported\n"); + cpu->cfg.pmu_num =3D 0; + return -1; + } + + /* Create a bitmask of available programmable counters */ + cpu->pmu_avail_ctrs =3D MAKE_32BIT_MASK(3, num_counters); + + return 0; } diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 58a5bc3a4089..036653627f78 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -26,3 +26,10 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *e= nv, uint32_t target_ctr); bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr); +void riscv_pmu_timer_cb(void *priv); +int riscv_pmu_init(RISCVCPU *cpu, int num_counters); +int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, + uint32_t ctr_idx); +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); +int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, + uint32_t ctr_idx); --=20 2.25.1 From nobody Mon May 13 13:25:30 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1661380400; cv=none; d=zohomail.com; s=zohoarc; b=RaMqByKmgBj4v8NqD81i32Idf0CSV05XnUZ/bxTFGj8TwIxS5KaBktZsFk3gr7lXieLidbuHPdWLqupL4cGErrVgU01V2e3SFDeByLa5fSN1CGHDl+InUSqhEsM93vUO5b+YVPBJZXPjQpqeU0M4R+2tqfiskYA501SB6lm0Jgo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661380400; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pkx1L04bX66E/ksRE+5gImHbvF3ng5yF46rSUHpQt+s=; b=ntjqr0m7iqUCPOWun8iysbP72p77uJBRBlkANjUF7bpgZlOE1mp0/zN6XXBsyUu0KEMxHleyp9bRpR7NWTnICUMI1ESkO3V6KSqhe/q8OuJlFDdKlR+UdiC7GQf8ly0ExpryPQudqiDVFmt9Jz1EEpX8osC3HY595RGKNPt7gls= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661380400378477.75034142529114; Wed, 24 Aug 2022 15:33:20 -0700 (PDT) Received: from localhost ([::1]:37432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQyw2-00062x-2l for importer2@patchew.org; Wed, 24 Aug 2022 18:33:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQyhC-0008Q0-L3 for qemu-devel@nongnu.org; Wed, 24 Aug 2022 18:18:01 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:55067) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQygz-0006bv-JD for qemu-devel@nongnu.org; Wed, 24 Aug 2022 18:17:57 -0400 Received: by mail-pj1-x102f.google.com with SMTP id bf22so18446254pjb.4 for ; Wed, 24 Aug 2022 15:17:45 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id h18-20020a170902f71200b0016909be39e5sm4243031plo.177.2022.08.24.15.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 15:17:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=pkx1L04bX66E/ksRE+5gImHbvF3ng5yF46rSUHpQt+s=; b=EKYM4jpVCVc1LdI0f9uNcH60GxLt2e6mMV28ZUCKqtdnEwYH4RyQFhiCAS1WlRefe0 +HGHYJd4YZ8rc9yOsAzVNcovlgnXZQe0wwY1hcUfd5Wg3FTLOdH1YTpSRjlrj4tZpCDP fzNSmCznv0+44G25R6qdYhkF+BsCE+OdWm7nzdrVLzQIAiOjlLF8EUJ8E9CTCQQiuUGl uHFGKrPlfTKZDqrpz3eeY6xwgMaRKGvaFRV8avVMJiKzBrk6Dw8GTdLFg/Bkgq9A5St5 SoAGO3wmnwgNaP7FLBEUfDI9ePqFiqrfZJzC4GG/cOCOXiknXB5Kfb39g8McogyDwSmh OHDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=pkx1L04bX66E/ksRE+5gImHbvF3ng5yF46rSUHpQt+s=; b=yXGbGyMLmadWJ5dgH/+upNEs+17KEkSpbIiRPhNu9DRiJYqx9ojReSV3UTODqz9e0w YW58hPvEXLPIN3jeqKXgCDwTukAoItEil0eGXt8eEmz1f/owYVYYpDue5wMq2ff6ot9k 32GEYRw0RUKAJVP9/tHTzDZqZcEXWMTVq9CeC8XXQUH0+E/YG0xHXFKp4UjopFb4RpiI ezDck06ZDQVmOFUx0XxTSOMoR5C9sXmcAbT43VpfN/6WglLp/6Ve8D7YuZX2vbbQTzqz f3jD2dNIvyA/fhIxLvVq1e+LdV7bdguNWZ3BLJ6fw0BuL6sSRSfiM5BVbbyj70r03VnL efRw== X-Gm-Message-State: ACgBeo1aD9FLLH0zlib29pmHJlWolBei4qiaZfvNPF5ijJpqMG33kvgL QVBBQ4seEA8X7shcTWE4GsV5RQFJ0dT0Ug== X-Google-Smtp-Source: AA6agR5cRT7fTtsaWWIMU/9Ry6wiBtfchrd6+0WC22qE8cpR//TposMQIawFw1Aaokhgr6LzkKPnCA== X-Received: by 2002:a17:90b:4d89:b0:1fb:1cf5:e23d with SMTP id oj9-20020a17090b4d8900b001fb1cf5e23dmr1164194pjb.133.1661379464196; Wed, 24 Aug 2022 15:17:44 -0700 (PDT) From: Atish Patra To: qemu-devel@nongnu.org Cc: Bin Meng , Alistair Francis , Atish Patra , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v14 2/5] target/riscv: Simplify counter predicate function Date: Wed, 24 Aug 2022 15:16:58 -0700 Message-Id: <20220824221701.41932-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220824221701.41932-1-atishp@rivosinc.com> References: <20220824221701.41932-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1661380401817100001 Content-Type: text/plain; charset="utf-8" All the hpmcounters and the fixed counters (CY, IR, TM) can be represented as a unified counter. Thus, the predicate function doesn't need handle each case separately. Simplify the predicate function so that we just handle things differently between RV32/RV64 and S/HS mode. Reviewed-by: Bin Meng Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 110 ++++----------------------------------------- 1 file changed, 9 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 888ddfc4dd4b..2151e280a868 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -75,6 +75,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); int ctr_index; + target_ulong ctr_mask; int base_csrno =3D CSR_CYCLE; bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? true : false; =20 @@ -83,122 +84,29 @@ static RISCVException ctr(CPURISCVState *env, int csrn= o) base_csrno +=3D 0x80; } ctr_index =3D csrno - base_csrno; + ctr_mask =3D BIT(ctr_index); =20 if ((csrno >=3D CSR_CYCLE && csrno <=3D CSR_INSTRET) || (csrno >=3D CSR_CYCLEH && csrno <=3D CSR_INSTRETH)) { goto skip_ext_pmu_check; } =20 - if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) { + if (!(cpu->pmu_avail_ctrs & ctr_mask)) { /* No counter is enabled in PMU or the counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } =20 skip_ext_pmu_check: =20 - if (env->priv =3D=3D PRV_S) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIME: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRET: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIMEH: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRETH: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - } + if (((env->priv =3D=3D PRV_S) && (!get_field(env->mcounteren, ctr_mask= ))) || + ((env->priv =3D=3D PRV_U) && (!get_field(env->scounteren, ctr_mask= )))) { + return RISCV_EXCP_ILLEGAL_INST; } =20 if (riscv_cpu_virt_enabled(env)) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIME: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRET: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIMEH: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRETH: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } + if (!get_field(env->hcounteren, ctr_mask) && + get_field(env->mcounteren, ctr_mask)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } } #endif --=20 2.25.1 From nobody Mon May 13 13:25:30 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1661380212; cv=none; d=zohomail.com; s=zohoarc; b=MX7bs6q0Umhv9lyS4ZEjIv7ALGOjj53Ezo4XZNqFCVnpRoya73SA/+n/B5axmhY0E4mzfzLoI9NH1pLSUuAKlwyYBSC+tQZlW35BeBp8UndKz9Jg3hfO6yLdXPGGlVoVbm7a0GGxmh0KgxRWvQpS1veHkPfFsP9KLJzJuwIIJA8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661380212; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gCjE3VT6UzdtMXrMkp8tiepgyAPqA6FlwcHDo01mpfw=; b=Fatr+huzkMrHlHv2rwGPWeQwEHrgK+BHcUeDin0eg/H1aOPV3Rn1AtX4SAKfWsbpeGLQInmQnSW4XvNla2qD+mqbrEsx4Bm9h6qrocuqzBT3AJLyYKC0WEJ9Eo1iBHxrb+yHkLjN0VoA9Ggj3YVL0A9WNbpewCmafWgmbgbedoo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661380212689582.4730576563335; Wed, 24 Aug 2022 15:30:12 -0700 (PDT) Received: from localhost ([::1]:53330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQyt1-0003PE-Kj for importer2@patchew.org; Wed, 24 Aug 2022 18:30:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQyh4-0008Pl-Ns for qemu-devel@nongnu.org; Wed, 24 Aug 2022 18:17:59 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:43863) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQyh1-0006cL-1h for qemu-devel@nongnu.org; Wed, 24 Aug 2022 18:17:50 -0400 Received: by mail-pj1-x102a.google.com with SMTP id c13-20020a17090a4d0d00b001fb6921b42aso2917016pjg.2 for ; Wed, 24 Aug 2022 15:17:46 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id h18-20020a170902f71200b0016909be39e5sm4243031plo.177.2022.08.24.15.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 15:17:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=gCjE3VT6UzdtMXrMkp8tiepgyAPqA6FlwcHDo01mpfw=; b=lyjWDFasCSZdkYkXa/J89iIgh6qsaZaPAWyzn5Yu0TVdGDfzLfqD/MDzFwdhm16ruc I07/O7fJ8mrtgS0qHZk4kWcM6DDlHz5AW+sO6BMhO+v3GnyHwnr/cbCH0DZLbKYFKJO7 lyd1YnM9aTZ10QAHwQ/H7lK+tSZulhLX62IKpu5PJNDWmhTzePNkOkvpMH2LcQuu4X3b JM7Jym+OKHY3mrvLpgNXEMnJk+tzq5q2WDsoBSzqq1uWp230vaSn0vFq84C1rhjevYJj LPaOb9TibCUpmckDbPu3QtvfwQeWIM94d3oTNtTrfPOQLtTZO5bF1EWurkFK/S/AHEh5 ezhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=gCjE3VT6UzdtMXrMkp8tiepgyAPqA6FlwcHDo01mpfw=; b=4iBtNZcaf4LnAbMyf9LfSVNvwWDoSpnieN6XBULtThMbL467mrTPH0+FYq5dWrnsEO X4PLaIAWBW/1xMAcsTe08IAvrAHr2wrZqP8WcSB8OJ2sWWsNwMfzJseSm4l5zpCGaUi0 dCOilDBmABPgZfenWq6i4KhwCHej/2MnAYNePRW2p3BgKnZ+qdxCwqATB6j2oYRW9tXH 0m7pG/O5IZrbc67qx5zpkhkbU298i3liXyBzz8en1YnZSW50/5iKHYlQGEN0tOc64MXs Uwe2NQdgYQEJrwKTGTeScfgMlUQ3kVc5HvZgK/SIV35bFesnlAtqHMfCPihl58ZqaCKI KMzQ== X-Gm-Message-State: ACgBeo0xg/mNliXVxa9SFbYsn0edI9yqBtptBZVCIc/N5QLiFqysQDl2 jg17NsRIi4z5T/+ErZRJHJ7RUVojMm7BXQ== X-Google-Smtp-Source: AA6agR6vvx+G5XihognC1kNu1r5JqkH1GNp6dnLKLOK5aCQjlJZAqsTEFMKqgsJeDebblp3dZQ9K9w== X-Received: by 2002:a17:90a:de96:b0:1fa:e427:e18e with SMTP id n22-20020a17090ade9600b001fae427e18emr10564910pjv.116.1661379465213; Wed, 24 Aug 2022 15:17:45 -0700 (PDT) From: Atish Patra To: qemu-devel@nongnu.org Cc: Alistair Francis , Heiko Stuebner , Atish Patra , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v14 3/5] target/riscv: Add few cache related PMU events Date: Wed, 24 Aug 2022 15:16:59 -0700 Message-Id: <20220824221701.41932-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220824221701.41932-1-atishp@rivosinc.com> References: <20220824221701.41932-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1661380214921100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Reviewed-by: Alistair Francis Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu_helper.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 719c5d5d0209..67e4c0efd216 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -21,11 +21,13 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "pmu.h" #include "exec/exec-all.h" #include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" +#include "cpu_bits.h" =20 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -1189,6 +1191,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vad= dr addr, cpu_loop_exit_restore(cs, retaddr); } =20 + +static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) +{ + enum riscv_pmu_event_idx pmu_event_type; + + switch (access_type) { + case MMU_INST_FETCH: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; + break; + case MMU_DATA_LOAD: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; + break; + case MMU_DATA_STORE: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; + break; + default: + return; + } + + riscv_pmu_incr_ctr(cpu, pmu_event_type); +} + bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -1287,6 +1311,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } } } else { + pmu_tlb_fill_incr_ctr(cpu, access_type); /* Single stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, NULL, access_type, mmu_idx, true, false, fals= e); --=20 2.25.1 From nobody Mon May 13 13:25:30 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1661380100; cv=none; d=zohomail.com; s=zohoarc; b=daaIEN0YoazyUnHcEROfHDk36woMg9030FAjUMgHTTnr5iU/yvBpT4CzT7ebBMypYlzh5GWO8es8paLUjqX/d5GLKFV2EFbhOsDyyOaBxpKraWM7WfWC2dgOJHvaVSCB5I5OUFlZ8fkxkDtL/l1wHt7i1PbtitcxI8EZS/SGhTg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661380100; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OmG1KkQAuW3Sra8rU8ttCLZoW+g0VRmMlyVWawrmTAY=; b=SAv2o65DCmfMrHWkk4pqd6yQ00mx5eRroWK2wx7IcFUbzO4yVfjeFRuLDTpCF90rAtfJgZAEbDlyLVYKpqkaDsnWH+mtf/yrW9MeK9wViGY3+JeAuVHI69VO6R6NrRgRl+mWCLO59E1smZVMaZwscoSS7oaBQbYgIw6u+UT9FhQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661380100858723.1496715086381; Wed, 24 Aug 2022 15:28:20 -0700 (PDT) Received: from localhost ([::1]:46996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQyrD-0001BT-RK for importer2@patchew.org; Wed, 24 Aug 2022 18:28:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39432) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQyh7-0008Pt-Lm for qemu-devel@nongnu.org; Wed, 24 Aug 2022 18:18:01 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:45875) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQyh1-0006cp-QZ for qemu-devel@nongnu.org; Wed, 24 Aug 2022 18:17:53 -0400 Received: by mail-pl1-x633.google.com with SMTP id u22so16878873plq.12 for ; Wed, 24 Aug 2022 15:17:47 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id h18-20020a170902f71200b0016909be39e5sm4243031plo.177.2022.08.24.15.17.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 15:17:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=OmG1KkQAuW3Sra8rU8ttCLZoW+g0VRmMlyVWawrmTAY=; b=aUceF0M0+u4zsPfO4b0/+Tt8Vw57D67K6GuCJVuA+djsOaohbfPNHnfRFiLvigplfh N0UFjkFoz3/3NjlEIHTAMiOK0CcfMd5ZAxV+mAb36+/PBfoK3ZnQeV+TjI/nie06wVdS cRj/1aStDV3lSdkl5Ei71JfxKGSHytBoegl2nWhs3YvHZdWvRTj3uMgBW8ZO2XtqlBLX W7CrTS0EtyTLQyblANEf3fpSFx7zXJ41efy1vhxlw4fDfIu6mDzzB9auTwOXRFaLu6QK IMKUCe9uv0BPQcQg8qE/wI1Q/4I/3QpO3du7ZoNVvDH8Q/2ac1jbh4J6cjzJRFvAGBAZ 5FIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=OmG1KkQAuW3Sra8rU8ttCLZoW+g0VRmMlyVWawrmTAY=; b=LGUUTgRAMnOGKAo8K6kaQVqVsmNHWgIwLlGg1lnVvePVD8QinjxMD0jh+ibte1V+E7 rtxL7AcyO/UwPKElPLKXCSYIp+PQsT3H0syx3KCzkVztw0Y3pS1KtRMrO8ufMYNf9WgZ aCUX2nhlM90Xwaro89FT4Z/pdfYvPYD4pTvJqtnBXAr07o3ny0BLntWqOfyXI6dY7Q/t 9bO3Ppj+IeZU1JKUEGVuC8LjGzm2EF2kDmqsOR1G9MSIdkNi4pRIabR1wdpsF7ZSj27t pX7e9lkQE57dCEykLpfXy5b4gqR7XelWlrq8HLab/Wjkwst4FF7y/pdnC7n6XZ5u24rm KBdA== X-Gm-Message-State: ACgBeo1LeBuJwlde3L4AeyjInQsQRMps9st4h8y416FuwGfL1+3mHI/a haCGLkVBNHVtocCDTxCvS5bxO7GRS6mvDw== X-Google-Smtp-Source: AA6agR4HkhQjQVN18dG+Wzr68ro0m2Xr2dEa5uft5bjX43a4ONipXWJGeADAX9/tq/im02axIcct7g== X-Received: by 2002:a17:903:2286:b0:172:f8e3:6f11 with SMTP id b6-20020a170903228600b00172f8e36f11mr817659plh.3.1661379466200; Wed, 24 Aug 2022 15:17:46 -0700 (PDT) From: Atish Patra To: qemu-devel@nongnu.org Cc: Alistair Francis , Atish Patra , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v14 4/5] hw/riscv: virt: Add PMU DT node to the device tree Date: Wed, 24 Aug 2022 15:17:00 -0700 Message-Id: <20220824221701.41932-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220824221701.41932-1-atishp@rivosinc.com> References: <20220824221701.41932-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=atishp@rivosinc.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1661380101762100001 Content-Type: text/plain; charset="utf-8" Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Acked-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- hw/riscv/virt.c | 16 +++++++++++++ target/riscv/pmu.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++ target/riscv/pmu.h | 1 + 3 files changed, 74 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ff8c0df5cd47..befa9d2c26ac 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -30,6 +30,7 @@ #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/core/sysbus-fdt.h" +#include "target/riscv/pmu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" @@ -708,6 +709,20 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_phandles[socket] =3D aplic_s_phandle; } =20 +static void create_fdt_pmu(RISCVVirtState *s) +{ + char *pmu_name; + MachineState *mc =3D MACHINE(s); + RISCVCPU hart =3D s->soc[0].harts[0]; + + pmu_name =3D g_strdup_printf("/soc/pmu"); + qemu_fdt_add_subnode(mc->fdt, pmu_name); + qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); + + g_free(pmu_name); +} + static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memma= p, bool is_32_bit, uint32_t *phandle, uint32_t *irq_mmio_phandle, @@ -1036,6 +1051,7 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap, =20 create_fdt_flash(s, memmap); create_fdt_fw_cfg(s, memmap); + create_fdt_pmu(s); =20 update_bootargs: if (cmdline && *cmdline) { diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index a5f504e53c88..b8e56d2b7b8e 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -20,11 +20,68 @@ #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" +#include "sysemu/device_tree.h" =20 #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ #define MAKE_32BIT_MASK(shift, length) \ (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) =20 +/* + * To keep it simple, any event can be mapped to any programmable counters= in + * QEMU. The generic cycle & instruction count events can also be monitored + * using programmable counters. In that case, mcycle & minstret must conti= nue + * to provide the correct value as well. Heterogeneous PMU per hart is not + * supported yet. Thus, number of counters are same across all harts. + */ +void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name) +{ + uint32_t fdt_event_ctr_map[20] =3D {}; + uint32_t cmask; + + /* All the programmable counters can map to any event */ + cmask =3D MAKE_32BIT_MASK(3, num_ctrs); + + /* + * The event encoding is specified in the SBI specification + * Event idx is a 20bits wide number encoded as follows: + * event_idx[19:16] =3D type + * event_idx[15:0] =3D code + * The code field in cache events are encoded as follows: + * event_idx.code[15:3] =3D cache_id + * event_idx.code[2:1] =3D op_id + * event_idx.code[0:0] =3D result_id + */ + + /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ + fdt_event_ctr_map[0] =3D cpu_to_be32(0x00000001); + fdt_event_ctr_map[1] =3D cpu_to_be32(0x00000001); + fdt_event_ctr_map[2] =3D cpu_to_be32(cmask | 1 << 0); + + /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ + fdt_event_ctr_map[3] =3D cpu_to_be32(0x00000002); + fdt_event_ctr_map[4] =3D cpu_to_be32(0x00000002); + fdt_event_ctr_map[5] =3D cpu_to_be32(cmask | 1 << 2); + + /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[6] =3D cpu_to_be32(0x00010019); + fdt_event_ctr_map[7] =3D cpu_to_be32(0x00010019); + fdt_event_ctr_map[8] =3D cpu_to_be32(cmask); + + /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[9] =3D cpu_to_be32(0x0001001B); + fdt_event_ctr_map[10] =3D cpu_to_be32(0x0001001B); + fdt_event_ctr_map[11] =3D cpu_to_be32(cmask); + + /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[12] =3D cpu_to_be32(0x00010021); + fdt_event_ctr_map[13] =3D cpu_to_be32(0x00010021); + fdt_event_ctr_map[14] =3D cpu_to_be32(cmask); + + /* This a OpenSBI specific DT property documented in OpenSBI docs */ + qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", + fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); +} + static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) { if (ctr_idx < 3 || ctr_idx >=3D RV_MAX_MHPMCOUNTERS || diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 036653627f78..3004ce37b636 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -31,5 +31,6 @@ int riscv_pmu_init(RISCVCPU *cpu, int num_counters); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); +void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char *pmu_na= me); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); --=20 2.25.1 From nobody Mon May 13 13:25:30 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1661380569; cv=none; d=zohomail.com; s=zohoarc; b=cyPihxS+pfMc6IOVEztjxrk9v7/RWKjlecyxsCWu7snR6VeU0ClQ4Cjn7LpAvz6wR0n07AWSTE1jpYwBFBWOCVX62ZP9giKk5/PseZIwxf8GvWKufdKewQ4DCOHFa0lvYDNkr+We0UciTwfUL6tjN4T3fbpicWoUxei5QX2ZnUc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661380569; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OY5+yeWkOpo9Rba6tuVCd+RI5nGnjSBhaNJjiqACgRs=; b=KQH4xoD7MvRtItjn3rGAtxU+KykRjrDCZlSlu7eCkbv6esjQUA2JEf6zTORo4HCXQgZVKTakKobGc+e7fsWLKbNz41XF5GUwCeLGTTnbcbHB8Zzt90EXtlAhkfBYOOSWGUeKMGPcf4InGJYsklyExvpcuE1lWYs2WpSk6P1gtFs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661380569651267.88299783422895; Wed, 24 Aug 2022 15:36:09 -0700 (PDT) Received: from localhost ([::1]:32996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQyyl-0008IT-Fj for importer2@patchew.org; Wed, 24 Aug 2022 18:36:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34106) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQyhC-0008Pz-Kt for qemu-devel@nongnu.org; Wed, 24 Aug 2022 18:18:01 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:46994) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQyh2-0006da-Ma for qemu-devel@nongnu.org; Wed, 24 Aug 2022 18:17:56 -0400 Received: by mail-pf1-x433.google.com with SMTP id p185so3373832pfb.13 for ; Wed, 24 Aug 2022 15:17:48 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id h18-20020a170902f71200b0016909be39e5sm4243031plo.177.2022.08.24.15.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 15:17:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=OY5+yeWkOpo9Rba6tuVCd+RI5nGnjSBhaNJjiqACgRs=; b=uZ/iAD865vaTdOi4WHcGJU3Bn1nBmJR4J2IOHltvWdmQujRzQcv98D/vj7sAeo6omg onRicteR61QSrSTwxYZIwE6fEsYVtej9GqoBr5P9zCFKj7pCZahALuy+/C9eNhrHS/JX HNH4YSapXEvzLTV39JiWS1GDRpWUiIxYJcz4J0YakVY8qgjeIqarkdumRFETZrveFxn4 gdGuZRMLr+rg+BN+32SW3cXpRQl2ralDJs5iMcnHYvQb8cb34pouer6rcixu0QyDWWzt 0zMXAjjmfzOqURovqfo1udCZz3Bv6aaUEMqWeJuQ4SA8NemxFYoPu/o78T/Q8D/pLSc6 4bsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=OY5+yeWkOpo9Rba6tuVCd+RI5nGnjSBhaNJjiqACgRs=; b=TihRbPu8Np2ZWlMdaXePoqpZTmwAGfYqQ0P7u/n1SbmDAqtUte43SCvCPQCMcu+74n iy9sWQdjjmdEDFycmwKI8G8Rn95l+9KGasvsIv2aUxeLz1RXPBYuWj6V9yBSddjPKHM5 /RAn6r4ijBE1EaTBbArDcFroxL5kS3Qn9rHMQpgCzVKcWerVH7a/3rYXvjNmjILe1vUi WN35+WKrrzV1A7pGxCTeGsqzmYUEbIaTa8ejqWHHqcDtbtiJs8w/2KNvYEWIAeGQsGal dnx5iJBNwbgtM+kE1COZOihdHI1FD9mL2iHFn9R46+86WzLTnGZjwyrsldZA8ZZrF4e0 hvgw== X-Gm-Message-State: ACgBeo0yLOjOziqo7sc4RlJsijXIH2Jb17i5wm3N7NPq8+LgdR6/zhbC AYflQCNhCXE07LvUYht1qhJR5qk/hj/etQ== X-Google-Smtp-Source: AA6agR7U5JP04IX7Ihf6mCnZUkJOYzNUGdnGpcrLXLgEBTvnSLAxykxuKskjb32m3FJD2C7bXaXJcw== X-Received: by 2002:a63:3489:0:b0:42b:1f9a:e620 with SMTP id b131-20020a633489000000b0042b1f9ae620mr780486pga.366.1661379467176; Wed, 24 Aug 2022 15:17:47 -0700 (PDT) From: Atish Patra To: qemu-devel@nongnu.org Cc: Weiwei Li , Alistair Francis , Atish Patra , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v14 5/5] target/riscv: Update the privilege field for sscofpmf CSRs Date: Wed, 24 Aug 2022 15:17:01 -0700 Message-Id: <20220824221701.41932-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220824221701.41932-1-atishp@rivosinc.com> References: <20220824221701.41932-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1661380570511100001 Content-Type: text/plain; charset="utf-8" The sscofpmf extension was ratified as a part of priv spec v1.12. Mark the csr_ops accordingly. Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 90 ++++++++++++++++++++++++++++++---------------- 1 file changed, 60 insertions(+), 30 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2151e280a868..b96db1b62b38 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -4067,63 +4067,92 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_mhpmevent }, =20 [CSR_MHPMEVENT3H] =3D { "mhpmevent3h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT4H] =3D { "mhpmevent4h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT5H] =3D { "mhpmevent5h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT6H] =3D { "mhpmevent6h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT7H] =3D { "mhpmevent7h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT8H] =3D { "mhpmevent8h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT9H] =3D { "mhpmevent9h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT10H] =3D { "mhpmevent10h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT11H] =3D { "mhpmevent11h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT12H] =3D { "mhpmevent12h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT13H] =3D { "mhpmevent13h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT14H] =3D { "mhpmevent14h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT15H] =3D { "mhpmevent15h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT16H] =3D { "mhpmevent16h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT17H] =3D { "mhpmevent17h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT18H] =3D { "mhpmevent18h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT19H] =3D { "mhpmevent19h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT20H] =3D { "mhpmevent20h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT21H] =3D { "mhpmevent21h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT22H] =3D { "mhpmevent22h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT23H] =3D { "mhpmevent23h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT24H] =3D { "mhpmevent24h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT25H] =3D { "mhpmevent25h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT26H] =3D { "mhpmevent26h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT27H] =3D { "mhpmevent27h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT28H] =3D { "mhpmevent28h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT29H] =3D { "mhpmevent29h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT30H] =3D { "mhpmevent30h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT31H] =3D { "mhpmevent31h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_hpmcounterh = }, [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_hpmcounterh = }, @@ -4213,7 +4242,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_mhpmcounterh }, [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_SCOUNTOVF] =3D { "scountovf", sscofpmf, read_scountovf }, + [CSR_SCOUNTOVF] =3D { "scountovf", sscofpmf, read_scountovf, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 #endif /* !CONFIG_USER_ONLY */ }; --=20 2.25.1