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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.09.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:09:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ee4ykpWvS9vCAX6jduEVuqgjn4tTXtGMZ/j/etyizQI=; b=Xciz4c5//fY9jmbrOEF5QX5b82dLRCI5F+p3/ta4URE5gBffRmwupyU0Wq+aWSzXHM 7PZoYri9UJAGP9ozujEbvWMdtBPzEhN8QIHiAlPWGdvq7KL0zuLV07npdIifrok86xKr S9T4Js8yoI2WDfW/raqdgPbg1hp48waIxB1UG1TnPyP7A2yo6AaTRnmCZROdIahnkDgI jNtNpyHg4WRVeUM1+dljIhpAJFnwbMgTnF3nQUUp/rFdeETTZ/84FSjDYACgG8VODPOD AJTYhuaFXD3YNlzc32b3OCAE/xZ7zcpQeycHZZl35pHDEhDt3hMYV9W0Fjij7nbLLxkA 9Agw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ee4ykpWvS9vCAX6jduEVuqgjn4tTXtGMZ/j/etyizQI=; b=RSZr/GR3pfb61iyW+l0HeIq3CnG7F2DAyUKdclm5JGY8gjYPsCRL6WjOfSLhZJ5GIn 9S5VSz9yCoGdKmBvrvSx49NYy/xYEB14rwji6VRO4h372ffHeGfCzVx9X4IZ9/Gjp8bU kfifiQu369Na5f6CFyJ/f0BZMRM3tKdXBu/wiVk0EyhcVLDfcZazBvalZ8U2wtQut5m/ WaXugT6ja0DvUguCYITiMsu6jOZdoxBBZygr/h8XOI0D0JFBaizdFbnWAJZemXQ0OzDk uDCDCK4dpMq3Vt8GR0fvgc2RS96lTNpvjRSItkQo+Zv+F6pC2389SIDlSk6c5QS4U/ZH pc+w== X-Gm-Message-State: AFqh2krhnWOqUW/Fcm9AMnBV2qinUtODYRN7Hwk4CmG1mdo8WeaGM4Z1 pq3K+IEVFjQOl1dIe3nSASnMUVhhUykHp5zGWk4= X-Google-Smtp-Source: AMrXdXuRKJEuzXU5ClXUt6z7xQTvD/jJq/aFi1pBpKC9s2BLFCsvzGgsNpZlmrRt+ERoEtBceyF4xA== X-Received: by 2002:a4a:3712:0:b0:4c9:f4e1:afe0 with SMTP id r18-20020a4a3712000000b004c9f4e1afe0mr16481964oor.1.1673456996582; Wed, 11 Jan 2023 09:09:56 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 01/10] hw/riscv/spike.c: simplify create_fdt() Date: Wed, 11 Jan 2023 14:09:39 -0300 Message-Id: <20230111170948.316276-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c29; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673457059278100001 Content-Type: text/plain; charset="utf-8" 'mem_size' and 'cmdline' are unused. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/spike.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index c517885e6e..4a66016d69 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -49,7 +49,6 @@ static const MemMapEntry spike_memmap[] =3D { }; =20 static void create_fdt(SpikeState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit, bool htif_custom_base) { void *fdt; @@ -299,8 +298,7 @@ static void spike_board_init(MachineState *machine) } =20 /* Create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0]), htif_custom_base); + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); =20 /* Load kernel */ if (machine->kernel_filename) { --=20 2.39.0 From nobody Fri Apr 26 18:32:57 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673457398; cv=none; d=zohomail.com; s=zohoarc; b=hHW+z5djZkDJMn/Fg7u9Xg7aRdzRMHmRQsz8FSZQMxcQ0yLiklZEBeXXxBu8ZFxKvu7SFwIy+cvaPdwGEk/n8RnTJW5wWWosum8S9vSA+2vx4K661weOIw0X1EqO3ScCnWGYjZxLIvVI3I/DPtCjA87mExTgL1GqesS1ChnY9kU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673457398; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H4dXSiAnits5ErKwehcEjsLRKL1HaEAOZOXpk41ZAWU=; b=fG7XCCAhY0jo8KnXGYv+faYYCGri8yceDROGbOppB7BuHRapzGUHHiBm49bwQ8ZDBIU02bY8IsvYH3SwrauEUoN0QYqZryGk7RvHO2B0VDkZArKnGdI28KHj8MEXLnSsDBT/0dLUFFBy2223ctry+EBBXGMZRUrX59abYjqBoNw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673457398747849.2166857757531; Wed, 11 Jan 2023 09:16:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFec1-0002hJ-4l; Wed, 11 Jan 2023 12:10:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFeby-0002bL-OI for qemu-devel@nongnu.org; Wed, 11 Jan 2023 12:10:02 -0500 Received: from mail-oo1-xc32.google.com ([2607:f8b0:4864:20::c32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFebw-00069N-A0 for qemu-devel@nongnu.org; Wed, 11 Jan 2023 12:10:02 -0500 Received: by mail-oo1-xc32.google.com with SMTP id s10-20020a4aa54a000000b004f240f120b3so380664oom.1 for ; Wed, 11 Jan 2023 09:09:59 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.09.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:09:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H4dXSiAnits5ErKwehcEjsLRKL1HaEAOZOXpk41ZAWU=; b=S2SERipg15y4IXl848CDa/ZgPj93Ezd31PiqNY6UifDVOKt8+PtFjIRJ+YFbmvlfMt ilfO0BKD7nA9BayltTgbkk6dzEuSzUX5LhX8pRAD/PwJpXV32u1N2xxQ7K/ceuSLicY5 pW0BDy6n1Mspx2zgytrAGJ3tUlubV/Gf3mc7VXukaD5ESQPF6pLiK/dpdq9/qS7kvZgK NhC4GPbl1YcjnrHWNfFtr0C4o5uyPpj+9usENog+pEGZUkMgUr0fOwxmIxLOdWqusD99 F3Oipcy30cfKR8s+RjrIGzES/UCipiEico6+BgW6VRizC3lgu6Fk8eURLWJD65kYAnXM vQYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H4dXSiAnits5ErKwehcEjsLRKL1HaEAOZOXpk41ZAWU=; b=RshvM/RVbU8jdj/tI9b33jS64CKfC96c+cAWECSBlP6qRUKEk/eQYyRld5VZQXLs6g Yz+hOwaOsOnnYXPA5VyZTYMpKxzdrnnt/Blb8cP1DjwMvFnE9FI9omzmcHlDzStDISHe MLB/LtlCocwIJkDE31NHwNuLvM12eJScTaTcawCEpYsv449/eEC+XuLDVsARLj0e9FCc NQP1q4BIe84kJOSqf0DxmUKvCvU+1asX+AZcWui2fWOuWTd/mSXo3bGqshgJFhA2ajGK hogi+igX5Q2tEKibC9MLN4ITrs3gpUTTCoTKP66NxL3baiZYzV2Km3D5z6vFHfOpFDtr EAcw== X-Gm-Message-State: AFqh2kqIJaldoNGjM50UDwRXY3Y4LELNF8/zAyNBRpiiar9MdKep54Yu GDvfOFsOpiIkzh5ymmObjndArgS6Nd0JNCmuSho= X-Google-Smtp-Source: AMrXdXvSNJiFv6PAv/N1Lp1vE3Zk7qxb0XYZV9mpGlEv1cDhWfkN6GxK1apcwCjsKnLiU0y12CIyjA== X-Received: by 2002:a4a:ca93:0:b0:49f:8720:d5b2 with SMTP id x19-20020a4aca93000000b0049f8720d5b2mr30777123ooq.8.1673456998770; Wed, 11 Jan 2023 09:09:58 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 02/10] hw/riscv/virt.c: simplify create_fdt() Date: Wed, 11 Jan 2023 14:09:40 -0300 Message-Id: <20230111170948.316276-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673457399670100001 Content-Type: text/plain; charset="utf-8" 'mem_size' and 'cmdline' aren't being used. Remove them. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a931ed05ab..89c99ec1af 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -999,7 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const = MemMapEntry *memmap) } =20 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_= bit) + bool is_32_bit) { MachineState *mc =3D MACHINE(s); uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; @@ -1499,8 +1499,7 @@ static void virt_machine_init(MachineState *machine) virt_flash_map(s, system_memory); =20 /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0])); + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); =20 s->machine_done.notify =3D virt_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); --=20 2.39.0 From nobody Fri Apr 26 18:32:57 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673457332; cv=none; d=zohomail.com; s=zohoarc; b=Fisn4tYxTkO/veTL7QsV/C3qb6LoAtqamFPaiA5sJ1X4Y9IWYlvNqQhEwI2bEhOStSW4KMlGhz4ioEdGBe3GpBSyTT0YRifAJjdLwyM8/isBtGsJYeWtUFpTnPXlWzQj7X4uPYRc3sWzIRoMg1a/e8EcWZFk9pqW8scKpZIGGsQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673457332; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DPONLIzIEy/3UQV9VjMXIl8RnUsRqK9vSoHXVRNeILc=; b=NGIgRF9hJkMwJzjKLSxMXdEEueyYTdXS9HlcllLkwzpF3Z/IIcARovil1KLyaOQsF6Imtkvqx7PastGd5YDI+fudmXXKKlWmgzhlvQEIY16cxxfdqeuGRivogBywXXWCVp2KzJZPOpEPB3j2OhQ4wC5rUyYetJyYhucpbEa/WTM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTP id 1673457332446889.3787795298349; Wed, 11 Jan 2023 09:15:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFecM-00032I-6E; Wed, 11 Jan 2023 12:10:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFec2-0002i8-Oa for qemu-devel@nongnu.org; Wed, 11 Jan 2023 12:10:07 -0500 Received: from mail-oo1-xc2c.google.com ([2607:f8b0:4864:20::c2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFec0-0006A7-GB for qemu-devel@nongnu.org; Wed, 11 Jan 2023 12:10:05 -0500 Received: by mail-oo1-xc2c.google.com with SMTP id x15-20020a4ab90f000000b004e64a0a967fso4200968ooo.2 for ; Wed, 11 Jan 2023 09:10:02 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DPONLIzIEy/3UQV9VjMXIl8RnUsRqK9vSoHXVRNeILc=; b=o4RMcKEM7PDjq66qO5ILPI4+50kxiFwI1Qe7/NK+PYZwMwomH1BdDsFsViq2FyUc7E 59G+XFjDpG5hRBhzORLsWsAD/FCVQ4mXTU6yuy/BoiuljzNNLZSfPrJU6FeWoL+MLdqe edOkc/X+gDqDkGCoOViLmIHU3k4XDVt01N5GawsbHz6sYp4GkiLrx/k28wd3hd90/+lW gGuYrPN4cLBXRfWXnF3zTDH1BiRD3FTrNccU4ucWBUxuu0QLfJvgJpRgpT6qcEaQBtbX Bs6WypDDjtA6P0jxh/3F8hFl2KIRhCOoeK13wcycemwIQewBbdjkQO9JBmACeopw4JLi Vzuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DPONLIzIEy/3UQV9VjMXIl8RnUsRqK9vSoHXVRNeILc=; b=O9HwbJyguaAMzH69bYUaWENRWW7urlOz3mJPnEKHI51riuySsd1/0k5AB0lHMe4zeR n0IQlpNQi1Hg69BsvAEIl3fiaeBHSpzRaL0RxfwpGscdrAswJASsVW+AVw9njdVeI0oJ ukJJrHUTVxEQt6XbJisawjrIUkbTrc7Erzuriz3jOZ38Y3UTwSPNEF6jGj7kN6i3sXjx /VtN6wXZzpkdr4cKhIyHP0ZkqvLbLfEnyqiY1z8vCtN7azlqvSubJNNIMGJ34YkYs35A jE2FD9bSVocBNI6KuPJeNVFIZF12XRVEvyM2BC3jsxts8tbnSEH2qktupNTzL6wOPLT4 fecA== X-Gm-Message-State: AFqh2kqbN/1b0vA7lvTtA+vOKwpDquOU4O9U74x4p7jIlcrDSMxIdEsc dG1B/TAVBIlF1cM2sLd3yb3zKT4k8Z9xJZbYEVU= X-Google-Smtp-Source: AMrXdXtkfl4QADQqITJKwHm1S6GlYPwmAjvPaTnw/pJumAF+OIalE1qpkaIG700gZO40KIBXte7erw== X-Received: by 2002:a4a:dbd8:0:b0:4a0:bc7f:462c with SMTP id t24-20020a4adbd8000000b004a0bc7f462cmr31480242oou.9.1673457001365; Wed, 11 Jan 2023 09:10:01 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH 03/10] hw/riscv/sifive_u.c: simplify create_fdt() Date: Wed, 11 Jan 2023 14:09:41 -0300 Message-Id: <20230111170948.316276-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673457332998100001 Content-Type: text/plain; charset="utf-8" 'cmdline' isn't being used. Remove it. A MachineState pointer is being retrieved via a MACHINE() macro calling qdev_get_machine(). Use MACHINE(s) instead to avoid calling qdev(). 'mem_size' is being set as machine->ram_size by the caller. Retrieve it via ms->ram_size. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_u.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9a75d4aa62..ccad386920 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -94,9 +94,10 @@ static const MemMapEntry sifive_u_memmap[] =3D { #define GEM_REVISION 0x10070109 =20 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_= bit) + bool is_32_bit) { - MachineState *ms =3D MACHINE(qdev_get_machine()); + MachineState *ms =3D MACHINE(s); + uint64_t mem_size =3D ms->ram_size; void *fdt; int cpu, fdt_size; uint32_t *cells; @@ -560,8 +561,7 @@ static void sifive_u_machine_init(MachineState *machine) qemu_allocate_irq(sifive_u_machine_reset, NULL, = 0)); =20 /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc.u_cpus)); + create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); =20 if (s->start_in_flash) { /* --=20 2.39.0 From nobody Fri Apr 26 18:32:57 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673457192; cv=none; d=zohomail.com; s=zohoarc; b=X6BpuZPC44pN1k9dTAk9qnzqrGV+A4HjIl6XHE5Sz0vPAtr8d5PX1lgQ3zuHEDu0gjADi7hWeeNg7SH7Ocd9/lKYXbCcmFwB6fGvoJ8l2fJN1T44/CsoPKaMKJb300HakS9lnIfQP9K/UlHyXxRfVaZofRdfoLmPdkape2JtaQs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673457192; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3Dkt8d3SpLodgKfYwmKReWsLo4BoLEeY7LR0KGeK3q0=; b=QHyI18tL4mSCFN7+Eehc8Wdo9khVoMA4T1ZO1pqqq1YBr+3YRa+IMy5csXpFLhVZdaCxmzzQ/GnGescXLq/upBcK/fDTNbm4EqXclnjAorLXoGS2LMkczfWxMbbW5LQPkkNLVxrOidC9pbg/Cy0ysfWLlI1T7/HxO/iZOYhrsv0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673457192025175.22349196719426; Wed, 11 Jan 2023 09:13:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFecG-0002qI-Cp; Wed, 11 Jan 2023 12:10:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFec4-0002in-6U for qemu-devel@nongnu.org; Wed, 11 Jan 2023 12:10:08 -0500 Received: from mail-oa1-x29.google.com ([2001:4860:4864:20::29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFec2-0006MI-Go for qemu-devel@nongnu.org; Wed, 11 Jan 2023 12:10:07 -0500 Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-12c8312131fso16216271fac.4 for ; Wed, 11 Jan 2023 09:10:04 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3Dkt8d3SpLodgKfYwmKReWsLo4BoLEeY7LR0KGeK3q0=; b=NlWShxDXsW+93CsfYq174mztRukMpbkfKqqgKWdMNucAqeovFx8qPOYlEXbDYV7biS ckttsNqmjrE3lwn9u4pZhuT8F70NxqwpjmP2P+9wvwq6aNW1OWYN4VmvmygpqHMZJJJT 8JtUPb57n/msVQ64XlqJ65g15vR8I8z8moGozxOdZP1YcE4CjB1mqmnSGmMdK67m4xRN EhWdweojEgyHysqqeP/SrTJrwSJzET3nch+vdAe0wEusU8Rf9WiMdmjaTYbJW455Lp8J XFgF3mAdGEWkzo1v1MywqV5PtZnQIdIuuQJ4qC5/kPXep5t5RmRU3ZQdibIyw81APsfh Ju/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Dkt8d3SpLodgKfYwmKReWsLo4BoLEeY7LR0KGeK3q0=; b=2YqpbWjjiRyh2scwXoq4ZEkyX62AuMz6eMn/ya1V+7McIOiq6pSjGJ1n55XZRK38xx AOiOOeVKXArP8Mb/6IRLnsJctPWL3FW4tL8Kctmcjdi6UmhAFrVG7Hvj33N6nmsOrdeO T6r1UpdDCGdVq/XKpCM8Gb0atb0yhz94sTe29r0hky+QbREI7EY9QbockQWU94GoMxY0 /P5BFq2PBKVRd0fV0K4r0kKfu7eBrgLaGcjd57lx5wilnlKp3gn5yA44H/7Uea1vsqEe atyqxS4yNM7QpJprnrBZGEZWkllNnmHaQdmsbyRUKC2RnYozJRrF7U7O+tGBNrMH0xN+ PaIQ== X-Gm-Message-State: AFqh2koH2UF9ZShExS22RWxYGMmgKmL+87mMs+ndgI4KYka6Kn7lu/QP OxB3jm9jTdXXLORq/zPMmdmW+Hx/gIlejql38U4= X-Google-Smtp-Source: AMrXdXsF08KcX6PHEOHd90nt35sn+52H1ZAiT3xeihfvSH/jQniOvnXYV6kPrBqvH+kwIWaoqr9GgA== X-Received: by 2002:a05:6870:9a14:b0:144:7a85:63ce with SMTP id fo20-20020a0568709a1400b001447a8563cemr42291578oab.54.1673457003354; Wed, 11 Jan 2023 09:10:03 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 04/10] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() Date: Wed, 11 Jan 2023 14:09:42 -0300 Message-Id: <20230111170948.316276-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673457193900100001 Content-Type: text/plain; charset="utf-8" create_fdt_socket_cpus() writes a different 'mmu-type' value if we're running in 32 or 64 bits. However, the flag is being calculated during virt_machine_init(), and is passed around in create_fdt(), then create_fdt_socket(), and then finally create_fdt_socket_cpus(). None of the intermediate functions are using the flag, which is a bit misleading. Remove 'is_32_bit' flag from create_fdt_socket_cpus() and calculate it using the already available RISCVVirtState pointer. This will also change the signature of create_fdt_socket() and create_fdt(), making it clear that these functions don't do anything special when we're running in 32 bit mode. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 89c99ec1af..99a0a43a73 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -223,12 +223,13 @@ static void create_pcie_irq_map(RISCVVirtState *s, vo= id *fdt, char *nodename, =20 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, char *clust_name, uint32_t *phandle, - bool is_32_bit, uint32_t *intc_phandles) + uint32_t *intc_phandles) { int cpu; uint32_t cpu_phandle; MachineState *mc =3D MACHINE(s); char *name, *cpu_name, *core_name, *intc_name; + bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); =20 for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { cpu_phandle =3D (*phandle)++; @@ -721,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s) } =20 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memma= p, - bool is_32_bit, uint32_t *phandle, + uint32_t *phandle, uint32_t *irq_mmio_phandle, uint32_t *irq_pcie_phandle, uint32_t *irq_virtio_phandle, @@ -750,7 +751,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, qemu_fdt_add_subnode(mc->fdt, clust_name); =20 create_fdt_socket_cpus(s, socket, clust_name, phandle, - is_32_bit, &intc_phandles[phandle_pos]); + &intc_phandles[phandle_pos]); =20 create_fdt_socket_memory(s, memmap, socket); =20 @@ -998,8 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const = MemMapEntry *memmap) g_free(nodename); } =20 -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - bool is_32_bit) +static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) { MachineState *mc =3D MACHINE(s); uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; @@ -1031,9 +1031,9 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap, qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); =20 - create_fdt_sockets(s, memmap, is_32_bit, &phandle, - &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, - &msi_pcie_phandle); + create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, + &irq_pcie_phandle, &irq_virtio_phandle, + &msi_pcie_phandle); =20 create_fdt_virtio(s, memmap, irq_virtio_phandle); =20 @@ -1499,7 +1499,7 @@ static void virt_machine_init(MachineState *machine) virt_flash_map(s, system_memory); =20 /* create device tree */ - create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); + create_fdt(s, memmap); =20 s->machine_done.notify =3D virt_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); --=20 2.39.0 From nobody Fri Apr 26 18:32:57 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673457146; cv=none; d=zohomail.com; s=zohoarc; b=MxFs/OKUDymMITDZcz9kR+6y/J0R3HOt24+HIqx+OPI7DCmoj0n3Yd4L/Q33p18WWwUCJY2Zim2P/40EGfri/Rt6xT7hIz4ZRBCWtletO5xW4YFPjGHSi/KaD9+EwKOsieudAJbkWrqQJRLz9os9OoNMULQX4Ej/UFLsQy3f5qI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673457146; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WXzmrToZZL5mmObYmkR3If3a0yo0qiD6+VD6xsglhGY=; b=hnym+eDyuOWmDeZ8nV+GxLAQJc4NNSqXX4gekPamWL1Og6oREyJDYHteSyWNsW51CFXBD7GuyDY7aBTF4BP+rqbT5GBWCkfFNIgUfiZ6uSSvV1eScQc7YDutnf7OhhG8Liw4HFuhvW+B2QWtogbZ4VN0+bTiAhSiO4jFk+X4oHg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTP id 1673457146101930.4918309634943; Wed, 11 Jan 2023 09:12:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFecL-0002yU-VA; Wed, 11 Jan 2023 12:10:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFec6-0002jb-Kg for qemu-devel@nongnu.org; Wed, 11 Jan 2023 12:10:12 -0500 Received: from mail-oo1-xc2a.google.com ([2607:f8b0:4864:20::c2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFec3-0006Mw-3q for qemu-devel@nongnu.org; Wed, 11 Jan 2023 12:10:09 -0500 Received: by mail-oo1-xc2a.google.com with SMTP id d2-20020a4ab202000000b004ae3035538bso4188821ooo.12 for ; Wed, 11 Jan 2023 09:10:06 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WXzmrToZZL5mmObYmkR3If3a0yo0qiD6+VD6xsglhGY=; b=S6ZItws+t5NWDN5NaOX9uqQjaUMjm8rGOUmM+x+Xd67Xh4T/02nivupy7TdswCDPBO 7Qlxr2cJblkG66LQQTplH22kmwZ+f7pbJEXlSwJfKbO4E4CzwZ3Me1ZsUFbTJVYZdnB9 81bxu3oUMG8Ur5IYrSwcNzTTiCuGG5wn8OJ2wztAEZPLypIktcVbEMUm8Qf+0GAAuySP 6P1bDqU2UqIY969pOnN+GounJtN1eHehr1oRyBj8l807U8piEVjDZH+B4vF7rHfymIyU GWrD6uWVqodKUtb9wlgOBHipE/2WNctswxAP+BrGnki5Q+IdnCq9g9MZ5tDv0T2qOcnI M31w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WXzmrToZZL5mmObYmkR3If3a0yo0qiD6+VD6xsglhGY=; b=h7ovFTxsgc5BP9IqnXNNOgP4nR8+uXaff4gip+eKRfCKSRqALPuEQ4upt6gJLkhAdM GgZ1uWNni4fEKuIHE7iRO/eiHd932AYwRaR8IFhBT5QVgE1VglQZFTmaQ75uuAkQQf2G te5DtsquzqXM+TImeABSZBOBtPGvD7eFQFFYjTc2kBfQnZieNPityVAlm/nL2FECPb4n nNP3NIRELwLOMgS0TvO6mRJV0ZNh66/AixddIRRbXklpyBU1MjqVcdMF/no+oLZXetIB izKMZuBqG1g3AmtxfrdHSawB+at94FpprH1pnb6r+42vtwqBhtK/t3ET+Q6CmzQuW5iK XDZQ== X-Gm-Message-State: AFqh2kok7SsxM7kpB8uJ/9vPoHF6DR/277OWlI/KsV0ZO+kHRXq5eBP1 aSfz0AK9PH6h9gGc1jMtf4RdoTDIK5u7AOrTixo= X-Google-Smtp-Source: AMrXdXs2E2ogIcWYYDOeVqK+Dxea9nQmd0USIj4shw3pzn3n24sKVRB3LK0QEYke7PBGaX/yPpMf5w== X-Received: by 2002:a4a:928f:0:b0:4f1:e1c7:2723 with SMTP id i15-20020a4a928f000000b004f1e1c72723mr8992048ooh.8.1673457005469; Wed, 11 Jan 2023 09:10:05 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 05/10] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() Date: Wed, 11 Jan 2023 14:09:43 -0300 Message-Id: <20230111170948.316276-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673457147610100001 Content-Type: text/plain; charset="utf-8" There's no need to use a MachineState pointer and a fdt pointer now that all RISC-V machines are using the FDT from the MachineState. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/numa.c | 6 +++--- hw/riscv/spike.c | 6 +++--- hw/riscv/virt.c | 18 +++++++++--------- include/hw/riscv/numa.h | 6 +++--- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c index 7fe92d402f..f4343f5cde 100644 --- a/hw/riscv/numa.c +++ b/hw/riscv/numa.c @@ -156,11 +156,11 @@ uint64_t riscv_socket_mem_size(const MachineState *ms= , int socket_id) ms->numa_state->nodes[socket_id].node_mem : 0; } =20 -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, - const char *node_name, int socket_id) +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_na= me, + int socket_id) { if (numa_enabled(ms)) { - qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id); + qemu_fdt_setprop_cell(ms->fdt, node_name, "numa-node-id", socket_i= d); } } =20 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 4a66016d69..05d34651cb 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, qemu_fdt_setprop_cell(fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); + riscv_socket_fdt_write_id(mc, cpu_name, socket); qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); =20 intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_n= ame); @@ -154,7 +154,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, qemu_fdt_setprop_cells(fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); + riscv_socket_fdt_write_id(mc, mem_name, socket); g_free(mem_name); =20 clint_addr =3D memmap[SPIKE_CLINT].base + @@ -167,7 +167,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); + riscv_socket_fdt_write_id(mc, clint_name, socket); =20 g_free(clint_name); g_free(clint_cells); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 99a0a43a73..1d3bd25cb5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -253,7 +253,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, i= nt socket, qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); + riscv_socket_fdt_write_id(mc, cpu_name, socket); qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); =20 intc_phandles[cpu] =3D (*phandle)++; @@ -291,7 +291,7 @@ static void create_fdt_socket_memory(RISCVVirtState *s, qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); + riscv_socket_fdt_write_id(mc, mem_name, socket); g_free(mem_name); } =20 @@ -327,7 +327,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s, 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); + riscv_socket_fdt_write_id(mc, clint_name, socket); g_free(clint_name); =20 g_free(clint_cells); @@ -372,7 +372,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, aclint_mswi_cells, aclint_cells_size); qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + riscv_socket_fdt_write_id(mc, name, socket); g_free(name); } =20 @@ -396,7 +396,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, 0x0, RISCV_ACLINT_DEFAULT_MTIME); qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", aclint_mtimer_cells, aclint_cells_size); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + riscv_socket_fdt_write_id(mc, name, socket); g_free(name); =20 if (s->aia_type !=3D VIRT_AIA_TYPE_APLIC_IMSIC) { @@ -412,7 +412,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, aclint_sswi_cells, aclint_cells_size); qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + riscv_socket_fdt_write_id(mc, name, socket); g_free(name); } =20 @@ -471,7 +471,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRT_IRQCHIP_NUM_SOURCES - 1); - riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); + riscv_socket_fdt_write_id(mc, plic_name, socket); qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", plic_phandles[socket]); =20 @@ -663,7 +663,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_s_phandle); qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); + riscv_socket_fdt_write_id(mc, aplic_name, socket); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); g_free(aplic_name); =20 @@ -691,7 +691,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); + riscv_socket_fdt_write_id(mc, aplic_name, socket); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); =20 if (!socket) { diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h index 1a9cce3344..634df6673f 100644 --- a/include/hw/riscv/numa.h +++ b/include/hw/riscv/numa.h @@ -90,10 +90,10 @@ bool riscv_socket_check_hartids(const MachineState *ms,= int socket_id); * @ms: pointer to machine state * @socket_id: socket index * - * Write NUMA node-id FDT property for given FDT node + * Write NUMA node-id FDT property in MachineState->fdt */ -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, - const char *node_name, int socket_id); +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_na= me, + int socket_id); =20 /** * riscv_socket_fdt_write_distance_matrix: --=20 2.39.0 From nobody Fri Apr 26 18:32:57 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673457828; cv=none; d=zohomail.com; s=zohoarc; b=AsueukjdK71rDvwjPiZeAGouIMPf5oeTBTvd9XDTdKY9tSfCSWJtUjzVbn53NICS2jspmWNVo0b5IUBIvR+UKL6ADHs3Ca0CIbpTkKiFBfVYS2yJ1yPScChSLtjFFxDqwIaebxI5941uAAax+a7jpRVb7OhH9SnTFhau6+0Qfp4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673457828; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wJyEstskuH3VB5vAnrT5gTar803EFvBC9v6S2B7z6CM=; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wJyEstskuH3VB5vAnrT5gTar803EFvBC9v6S2B7z6CM=; b=L2pFBYsb8J3paWXpLJNkVc1tBgbIiPh0tyuJkea24Z6f5UE1WmDF6/T5dAtxPrsMGW elJs6zyn4xW5hL4udW6yUMxJh0mpRQYM/dBe8nP9LG8C9USieuabHQTN00TtkUccRQHX ISfX69jIGr2YtqwQoxfm5T4FOKz30pKbYKtPrpgA9RplJD3t44x6nK9Q+d9B/watFB/T 48y0RHKMs0T55p9u4OkWx6QWyh7COmsbL3Si+e45ahwPQCtp5CxkKOmnVNEFwF8RwdYq mbMqx7SrUZOdgFK77xUzlh2/SYVBoGXN64EV8axAiT6r0W2luVDmobM3cvSSlnPz7vgN bKZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wJyEstskuH3VB5vAnrT5gTar803EFvBC9v6S2B7z6CM=; b=hD3B/AtgBL9brgAGuECn3pHFcNh0zJEqq7hsGtS7+ubyBLARfXgXo9m+PvSMKGFkkf 70X+ftqJ/rYWc1cX6mrSU5fofEOztJcmUJsiBQw3FVNf3ybHtHwp1zu2ecgunhfwKIgp OV2eCvpjr43Z8nGXGNXNxmUFmALLOrvpgjfgllwnP+qiHt/0dTmpyjtpKZnI5iYczRNF REB91zSlE+FuPfKVIBfY9LJUJNG5KI8UF/xO8krqYS70mnnzZulcChU3tWIR7bhbtGfm wbDyvTbu7ExtWnBMRed6XE+Vqo5Za+EJCxtoT64TUhM4eBZN5Gx5teMBFdNxXAgwlxVl sFaQ== X-Gm-Message-State: AFqh2kpPx2SEP1pbwQ0187hZ0zVU3td4BKh53Gp65UvYgrZ6VvTeuuPK 3/ew6/9n5vnfI/w9dDjEjshQluPx555sqLxDlYs= X-Google-Smtp-Source: AMrXdXsyyYqgbi9vnztN0qEJUh4sEMhVgpD0UW9FODp3c3sMvB7k9jMqwNHuHLS867xUDzKnfPJSpA== X-Received: by 2002:a4a:c54d:0:b0:4f2:ff6:6168 with SMTP id j13-20020a4ac54d000000b004f20ff66168mr3065732ooq.3.1673457007534; Wed, 11 Jan 2023 09:10:07 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 06/10] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() Date: Wed, 11 Jan 2023 14:09:44 -0300 Message-Id: <20230111170948.316276-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673457829947100001 Content-Type: text/plain; charset="utf-8" There's no need to use a MachineState pointer and a fdt pointer now that all RISC-V machines are using the FDT from the MachineState. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/numa.c | 8 ++++---- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- include/hw/riscv/numa.h | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c index f4343f5cde..4720102561 100644 --- a/hw/riscv/numa.c +++ b/hw/riscv/numa.c @@ -164,7 +164,7 @@ void riscv_socket_fdt_write_id(const MachineState *ms, = const char *node_name, } } =20 -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *= fdt) +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms) { int i, j, idx; uint32_t *dist_matrix, dist_matrix_size; @@ -184,10 +184,10 @@ void riscv_socket_fdt_write_distance_matrix(const Mac= hineState *ms, void *fdt) } } =20 - qemu_fdt_add_subnode(fdt, "/distance-map"); - qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", + qemu_fdt_add_subnode(ms->fdt, "/distance-map"); + qemu_fdt_setprop_string(ms->fdt, "/distance-map", "compatible", "numa-distance-map-v1"); - qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", + qemu_fdt_setprop(ms->fdt, "/distance-map", "distance-matrix", dist_matrix, dist_matrix_size); g_free(dist_matrix); } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 05d34651cb..91bf194ec1 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -174,7 +174,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, g_free(clust_name); } =20 - riscv_socket_fdt_write_distance_matrix(mc, fdt); + riscv_socket_fdt_write_distance_matrix(mc); =20 qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1d3bd25cb5..e374b58f89 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -805,7 +805,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, } } =20 - riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); + riscv_socket_fdt_write_distance_matrix(mc); } =20 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h index 634df6673f..8f5280211d 100644 --- a/include/hw/riscv/numa.h +++ b/include/hw/riscv/numa.h @@ -100,9 +100,9 @@ void riscv_socket_fdt_write_id(const MachineState *ms, = const char *node_name, * @ms: pointer to machine state * @socket_id: socket index * - * Write NUMA distance matrix in FDT for given machine + * Write NUMA distance matrix in MachineState->fdt */ -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *= fdt); +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms); =20 CpuInstanceProperties riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index); --=20 2.39.0 From nobody Fri Apr 26 18:32:57 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673457268; cv=none; d=zohomail.com; s=zohoarc; b=jMHEPN2KLaz0PRV+eAP7LsyrWi8aDFw3E04axZ7fLpTcByR5D49scDq52EDWtpzP8iRZPfg3BB3gZP0OPeNJdRGL8v/KAnwwu24u0t34sNhv1s0oNaR9qJ6VeL8sau/Tl+bztcpK7ZPp2cTbMymUJFknAPZyblQS8d+CVvoH3mk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673457268; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5LQXvUZ8MPXYbIKFJnWO4N2K/K8eQ/j7XzvKq374hKA=; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5LQXvUZ8MPXYbIKFJnWO4N2K/K8eQ/j7XzvKq374hKA=; b=l6BWGc83gLK/ZwVMGVb4jqEQEskLuYqSzYqQugPIrtprUWAuR93YHskwA+c/MWvYjM 1iMUQRdO8vmWb36jNk3uZ28rFQ18cKyc81AqXFkI6TffxkjguHjA/N0MuWyy7TUxdSUC U1ZNxu16jH/UfJR2Wf5kfkcRasuB5TxQGwd0lzHLrG5uUpMSpQFc8Iemb26ckZzoK4nc keudjdsuUhtzKADLSBMiip5fGuriBBqGzXzu/ZI+Sb2V3LZfNI11vGAkTGJDlwJ5WleQ 917Ki7bN1Wpa4Kxwu37GXm6iDLut9yoIE/0Z9fDHHoPcr8ow//mZsK2RdyUDnrgJhSjd JUDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5LQXvUZ8MPXYbIKFJnWO4N2K/K8eQ/j7XzvKq374hKA=; b=gUq+a5EnR8UbOjkk1xQoI8UNPR9hOxZFY24pMr7GJL6dk/ow1TcxH6a2rUJztdzJrw kQ+LM1KXI6TM9FHiypHw28y69o+Y1jdQTGLxiPW85ayoQ7umaHcvNiJey2553lbRqTP4 uXytnQJqjlGLRWe1xEj5EwJAezVKAIVznJWkDMD8pSO+hNKiUA37ytbkhWvWGHkAcyO1 c5s2vw3Ua6Rr3rci9zM/ar0lPxgw95E8rbdrGN7Ggq6l6PN1vapTt4mJ3Rh+pU3e7LtE oBIqXU9fGQ1XY285Lm7jR+lIVK0d60sxUw/+4b4qiSlt9etmQkId9NYVByBvFO61C3ea dtcw== X-Gm-Message-State: AFqh2kovECso3u/Cxejv6FP4mqTPHkwMNJxWUOayt40wX+xRvg1YsgeB xNzV7PZIJmoI5kYarSfV605GPfVD2aapkSqsU7I= X-Google-Smtp-Source: AMrXdXvT9Ul9DaaL20QIy6KYGLcJ7xRtMTqcR9EtJZSUw0L+myrwZM9ZRPVQZdFHUmkl0/ISpgCoEA== X-Received: by 2002:a05:6870:316:b0:13b:23e2:3c9a with SMTP id m22-20020a056870031600b0013b23e23c9amr40066849oaf.47.1673457009539; Wed, 11 Jan 2023 09:10:09 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 07/10] hw/riscv: simplify riscv_load_fdt() Date: Wed, 11 Jan 2023 14:09:45 -0300 Message-Id: <20230111170948.316276-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673457270265100001 Content-Type: text/plain; charset="utf-8" All callers of riscv_load_fdt() are using machine->ram_size as 'mem_size' and the fdt is always retrievable via machine->fdt. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/boot.c | 4 +++- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/sifive_u.c | 3 +-- hw/riscv/spike.c | 3 +-- hw/riscv/virt.c | 3 +-- include/hw/riscv/boot.h | 2 +- 6 files changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index e868fb6ade..21dea7eac2 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -265,10 +265,12 @@ out: return kernel_entry; } =20 -uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) +uint64_t riscv_load_fdt(MachineState *ms, hwaddr dram_base) { uint64_t temp, fdt_addr; + uint64_t mem_size =3D ms->ram_size; hwaddr dram_end =3D dram_base + mem_size; + void *fdt =3D ms->fdt; int ret, fdtsize =3D fdt_totalsize(fdt); =20 if (fdtsize <=3D 0) { diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index c45023a2b1..6bb08f66bd 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,8 +633,8 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) true, NULL); =20 /* Compute the fdt load address in dram */ - fdt_load_addr =3D riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].b= ase, - machine->ram_size, machine->fdt); + fdt_load_addr =3D riscv_load_fdt(machine, + memmap[MICROCHIP_PFSOC_DRAM_LO].bas= e); /* Load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_a= ddr, memmap[MICROCHIP_PFSOC_ENVM_DATA].base, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ccad386920..fc2a8a7af4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -609,8 +609,7 @@ static void sifive_u_machine_init(MachineState *machine) } =20 /* Compute the fdt load address in dram */ - fdt_load_addr =3D riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr =3D riscv_load_fdt(machine, memmap[SIFIVE_U_DEV_DRAM].ba= se); if (!riscv_is_32bit(&s->soc.u_cpus)) { start_addr_hi32 =3D (uint64_t)start_addr >> 32; } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 91bf194ec1..82093dd2cb 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -316,8 +316,7 @@ static void spike_board_init(MachineState *machine) } =20 /* Compute the fdt load address in dram */ - fdt_load_addr =3D riscv_load_fdt(memmap[SPIKE_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr =3D riscv_load_fdt(machine, memmap[SPIKE_DRAM].base); =20 /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e374b58f89..0a0252368e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1300,8 +1300,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) } =20 /* Compute the fdt load address in dram */ - fdt_load_addr =3D riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr =3D riscv_load_fdt(machine, memmap[VIRT_DRAM].base); /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, virt_memmap[VIRT_MROM].base, diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index cbd131bad7..3581bbe447 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -47,7 +47,7 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); +uint64_t riscv_load_fdt(MachineState *ms, hwaddr dram_start); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, hwaddr rom_base, hwaddr rom_size, --=20 2.39.0 From nobody Fri Apr 26 18:32:57 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673457323; cv=none; d=zohomail.com; s=zohoarc; b=dNr/Nn9kT2//w4YX/cFf7NQ9Uqi3s98oRObb3KY0JDpI6PDyyRUP4voenaecanMTsdR+QUZAck21dw54eGgK1S12d8E9pDofevb1/Eh3gufSGjPnbB6fpMD2bUwI9nYrbC0aBe4gBThY8hFAD3LQyoW9X2ZJRE7dZY82BWyvYQc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673457323; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nD7aC9DgA+b4W9/7h4R4JLYyeierlW3YAI6BlnUrPb4=; b=ifL1C94Ttt3ZY4J4dDn0JJHBiU1nsRrdhIPhfPVgWeXqCxQLlFtUl8lMBlNKz6dMNg FAsIYgS4RuEIs9dax/b7AJhuWVNWYEiamlyq3iMPEpQFr8Ml9h07LOdX1GN4tTnANGMp Hj5K8y+jTePrYMzViHoEWKkIBOhd89Z+xNN+CjSdaGROzWvJvt9T8+Ent9ALGlFyZszr 5m+7G+LfZO/iup73ZQCKXpXnEfZnkZ/GiB+pkTveQ5/PtiTbv8DT7QeidS6kT1BaHKcT 7BjbL6/fW7W/V5Y4eQVmV+0tuOGZtZrUKYdYaArksefDBXFqpusJb66ox5SDmkX38ZBa oMSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nD7aC9DgA+b4W9/7h4R4JLYyeierlW3YAI6BlnUrPb4=; b=xFI9RrrI8v/EIPGbNGxt6tXjT1CY9L5kjTFdxUt62lVpNLEoj1npzYqKG0PulF0Jli 7xn86b+VUv1xUzis3ZMlvtFN2E+eXnholYqmkuxuUzqB6zCWjnD/ppa2SDdvoNYGTpoO 4NX9PLxyQqd0sa3BpXm6afHTnxaDGHkz9FukA2ZwjTPDi/p0Lob/ZjEO3OQWew6gZ+eq p6jx48gpnF3sl7AQC8KVxclUru5jjPwe9jeReHCs3WpUN5tWpm3ctynGU74miBo1tQd/ 3WpJXGafLB8//W8SlEG1mwgIP29pfKAZOaqJcyt7zcyCGBncWAh80mcqgEKaF509vSiB CNcQ== X-Gm-Message-State: AFqh2koy7NI36f4w9szTMHQc0ry7rwsLWih2Oz3Y8ehnqF90FHG1c9zs SoBT08dxcentXdw2eCAArPIGanZjZORRMS3+iy8= X-Google-Smtp-Source: AMrXdXvHKjSXUNItqrNxSGZ6g/OXIPnLqjrDcZdm+ws7JM6x0BB9g4PDudATd10ma/IxCvnZqN733A== X-Received: by 2002:a4a:9613:0:b0:4a3:9f7a:add0 with SMTP id q19-20020a4a9613000000b004a39f7aadd0mr31930815ooi.5.1673457011612; Wed, 11 Jan 2023 09:10:11 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 08/10] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() Date: Wed, 11 Jan 2023 14:09:46 -0300 Message-Id: <20230111170948.316276-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c29; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673457324781100005 Content-Type: text/plain; charset="utf-8" riscv_socket_count() returns either ms->numa_state->num_nodes or 1 depending on NUMA support. In any case the value can be retrieved only once and used in the rest of the function. This will also alleviate the rename we're going to do next by reducing the instances of MachineState 'mc' inside hw/riscv/virt.c. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0a0252368e..f9bdf2a70b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -505,13 +505,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, int cpu, socket; char *imsic_name; MachineState *mc =3D MACHINE(s); + int socket_count =3D riscv_socket_count(mc); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; =20 *msi_m_phandle =3D (*phandle)++; *msi_s_phandle =3D (*phandle)++; imsic_cells =3D g_new0(uint32_t, mc->smp.cpus * 2); - imsic_regs =3D g_new0(uint32_t, riscv_socket_count(mc) * 4); + imsic_regs =3D g_new0(uint32_t, socket_count * 4); =20 /* M-level IMSIC node */ for (cpu =3D 0; cpu < mc->smp.cpus; cpu++) { @@ -519,7 +520,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const M= emMapEntry *memmap, imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); } imsic_max_hart_per_socket =3D 0; - for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { + for (socket =3D 0; socket < socket_count; socket++) { imsic_addr =3D memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size =3D IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; @@ -545,14 +546,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits= ", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shif= t", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -567,7 +568,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const M= emMapEntry *memmap, } imsic_guest_bits =3D imsic_num_bits(s->aia_guests + 1); imsic_max_hart_per_socket =3D 0; - for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { + for (socket =3D 0; socket < socket_count; socket++) { imsic_addr =3D memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size =3D IMSIC_HART_SIZE(imsic_guest_bits) * @@ -594,18 +595,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits= ", imsic_guest_bits); } - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits= ", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shif= t", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -733,6 +734,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, MachineState *mc =3D MACHINE(s); uint32_t msi_m_phandle =3D 0, msi_s_phandle =3D 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; + int socket_count =3D riscv_socket_count(mc); =20 qemu_fdt_add_subnode(mc->fdt, "/cpus"); qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", @@ -744,7 +746,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, intc_phandles =3D g_new0(uint32_t, mc->smp.cpus); =20 phandle_pos =3D mc->smp.cpus; - for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket--)= { + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { phandle_pos -=3D s->soc[socket].num_harts; =20 clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); @@ -775,7 +777,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, } =20 phandle_pos =3D mc->smp.cpus; - for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket--)= { + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { phandle_pos -=3D s->soc[socket].num_harts; =20 if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { @@ -790,7 +792,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, =20 g_free(intc_phandles); =20 - for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { + for (socket =3D 0; socket < socket_count; socket++) { if (socket =3D=3D 0) { *irq_mmio_phandle =3D xplic_phandles[socket]; *irq_virtio_phandle =3D xplic_phandles[socket]; @@ -1051,7 +1053,8 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap) =20 /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_= seed)); + qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + rng_seed, sizeof(rng_seed)); } =20 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, @@ -1326,9 +1329,10 @@ static void virt_machine_init(MachineState *machine) char *soc_name; DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; int i, base_hartid, hart_count; + int socket_count =3D riscv_socket_count(machine); =20 /* Check socket count limit */ - if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { + if (VIRT_SOCKETS_MAX < socket_count) { error_report("number of sockets/nodes should be less than %d", VIRT_SOCKETS_MAX); exit(1); @@ -1336,7 +1340,7 @@ static void virt_machine_init(MachineState *machine) =20 /* Initialize sockets */ mmio_irqchip =3D virtio_irqchip =3D pcie_irqchip =3D NULL; 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MachineClass pointers are usually called 'mc'. The 'virt' RISC-V machine has a lot of instances where MachineState pointers are named 'mc'. There is nothing wrong with that, but we gain more compatibility with the rest of the QEMU code base, and easier reviews, if we follow QEMU conventions. Rename all 'mc' MachineState pointers to 'ms'. This is a very tedious and mechanical patch that was produced by doing the following: - find/replace all 'MachineState *mc' to 'MachineState *ms'; - find/replace all 'mc->fdt' to 'ms->fdt'; - find/replace all 'mc->smp.cpus' to 'ms->smp.cpus'; - replace any remaining occurrences of 'mc' that the compiler complained about. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 434 ++++++++++++++++++++++++------------------------ 1 file changed, 217 insertions(+), 217 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f9bdf2a70b..3b73666d2a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -227,7 +227,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, i= nt socket, { int cpu; uint32_t cpu_phandle; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); char *name, *cpu_name, *core_name, *intc_name; bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); =20 @@ -236,40 +236,40 @@ static void create_fdt_socket_cpus(RISCVVirtState *s,= int socket, =20 cpu_name =3D g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); - qemu_fdt_add_subnode(mc->fdt, cpu_name); + qemu_fdt_add_subnode(ms->fdt, cpu_name); if (riscv_feature(&s->soc[socket].harts[cpu].env, RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", (is_32_bit) ? "riscv,sv32" : "riscv,sv= 48"); } else { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", "riscv,none"); } name =3D riscv_isa_string(&s->soc[socket].harts[cpu]); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); g_free(name); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, cpu_name, socket); - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); + riscv_socket_fdt_write_id(ms, cpu_name, socket); + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); =20 intc_phandles[cpu] =3D (*phandle)++; =20 intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_name); - qemu_fdt_add_subnode(mc->fdt, intc_name); - qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", + qemu_fdt_add_subnode(ms->fdt, intc_name); + qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", intc_phandles[cpu]); - qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", + qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", "riscv,cpu-intc"); - qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL,= 0); - qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); + qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL,= 0); + qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); =20 core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); - qemu_fdt_add_subnode(mc->fdt, core_name); - qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); + qemu_fdt_add_subnode(ms->fdt, core_name); + qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); =20 g_free(core_name); g_free(intc_name); @@ -282,16 +282,16 @@ static void create_fdt_socket_memory(RISCVVirtState *= s, { char *mem_name; uint64_t addr, size; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); =20 - addr =3D memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); - size =3D riscv_socket_mem_size(mc, socket); + addr =3D memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); + size =3D riscv_socket_mem_size(ms, socket); mem_name =3D g_strdup_printf("/memory@%lx", (long)addr); - qemu_fdt_add_subnode(mc->fdt, mem_name); - qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", + qemu_fdt_add_subnode(ms->fdt, mem_name); + qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); - qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mem_name, socket); + qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); + riscv_socket_fdt_write_id(ms, mem_name, socket); g_free(mem_name); } =20 @@ -303,7 +303,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s, char *clint_name; uint32_t *clint_cells; unsigned long clint_addr; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); static const char * const clint_compat[2] =3D { "sifive,clint0", "riscv,clint0" }; @@ -319,15 +319,15 @@ static void create_fdt_socket_clint(RISCVVirtState *s, =20 clint_addr =3D memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * so= cket); clint_name =3D g_strdup_printf("/soc/clint@%lx", clint_addr); - qemu_fdt_add_subnode(mc->fdt, clint_name); - qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, clint_name); + qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", (char **)&clint_compat, ARRAY_SIZE(clint_compat)); - qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, clint_name, socket); + riscv_socket_fdt_write_id(ms, clint_name, socket); g_free(clint_name); =20 g_free(clint_cells); @@ -344,7 +344,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, uint32_t *aclint_mswi_cells; uint32_t *aclint_sswi_cells; uint32_t *aclint_mtimer_cells; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); =20 aclint_mswi_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); aclint_mtimer_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); @@ -363,16 +363,16 @@ static void create_fdt_socket_aclint(RISCVVirtState *= s, if (s->aia_type !=3D VIRT_AIA_TYPE_APLIC_IMSIC) { addr =3D memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * sock= et); name =3D g_strdup_printf("/soc/mswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mswi"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_mswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, name, socket); + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); } =20 @@ -386,33 +386,33 @@ static void create_fdt_socket_aclint(RISCVVirtState *= s, size =3D memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; } name =3D g_strdup_printf("/soc/mtimer@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mtimer"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 0x0, RISCV_ACLINT_DEFAULT_MTIME); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_mtimer_cells, aclint_cells_size); - riscv_socket_fdt_write_id(mc, name, socket); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); =20 if (s->aia_type !=3D VIRT_AIA_TYPE_APLIC_IMSIC) { addr =3D memmap[VIRT_ACLINT_SSWI].base + (memmap[VIRT_ACLINT_SSWI].size * socket); name =3D g_strdup_printf("/soc/sswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-sswi"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_sswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, name, socket); + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); } =20 @@ -430,7 +430,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, char *plic_name; uint32_t *plic_cells; unsigned long plic_addr; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); static const char * const plic_compat[2] =3D { "sifive,plic-1.0.0", "riscv,plic0" }; @@ -456,27 +456,27 @@ static void create_fdt_socket_plic(RISCVVirtState *s, plic_phandles[socket] =3D (*phandle)++; plic_addr =3D memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socke= t); plic_name =3D g_strdup_printf("/soc/plic@%lx", plic_addr); - qemu_fdt_add_subnode(mc->fdt, plic_name); - qemu_fdt_setprop_cell(mc->fdt, plic_name, + qemu_fdt_add_subnode(ms->fdt, plic_name); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "#interrupt-cells", FDT_PLIC_INT_CELLS); - qemu_fdt_setprop_cell(mc->fdt, plic_name, + qemu_fdt_setprop_cell(ms->fdt, plic_name, "#address-cells", FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", + qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", (char **)&plic_compat, ARRAY_SIZE(plic_compat)); - qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", + qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", VIRT_IRQCHIP_NUM_SOURCES - 1); - riscv_socket_fdt_write_id(mc, plic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", + riscv_socket_fdt_write_id(ms, plic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", plic_phandles[socket]); =20 if (!socket) { - platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, + platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, memmap[VIRT_PLATFORM_BUS].base, memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); @@ -504,18 +504,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, { int cpu, socket; char *imsic_name; - MachineState *mc =3D MACHINE(s); - int socket_count =3D riscv_socket_count(mc); + MachineState *ms =3D MACHINE(s); + int socket_count =3D riscv_socket_count(ms); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; =20 *msi_m_phandle =3D (*phandle)++; *msi_s_phandle =3D (*phandle)++; - imsic_cells =3D g_new0(uint32_t, mc->smp.cpus * 2); + imsic_cells =3D g_new0(uint32_t, ms->smp.cpus * 2); imsic_regs =3D g_new0(uint32_t, socket_count * 4); =20 /* M-level IMSIC node */ - for (cpu =3D 0; cpu < mc->smp.cpus; cpu++) { + for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); } @@ -534,35 +534,35 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, } imsic_name =3D g_strdup_printf("/soc/imsics@%lx", (unsigned long)memmap[VIRT_IMSIC_M].base); - qemu_fdt_add_subnode(mc->fdt, imsic_name); - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (socket_count > 1) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits= ", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits= ", imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shif= t", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shif= t", IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle); =20 g_free(imsic_name); =20 /* S-level IMSIC node */ - for (cpu =3D 0; cpu < mc->smp.cpus; cpu++) { + for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_S_EXT); } @@ -583,34 +583,34 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, } imsic_name =3D g_strdup_printf("/soc/imsics@%lx", (unsigned long)memmap[VIRT_IMSIC_S].base); - qemu_fdt_add_subnode(mc->fdt, imsic_name); - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits= ", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits= ", imsic_guest_bits); } if (socket_count > 1) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits= ", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits= ", imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shif= t", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shif= t", IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle); g_free(imsic_name); =20 g_free(imsic_regs); @@ -629,7 +629,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, char *aplic_name; uint32_t *aplic_cells; unsigned long aplic_addr; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); uint32_t aplic_m_phandle, aplic_s_phandle; =20 aplic_m_phandle =3D (*phandle)++; @@ -644,28 +644,28 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_addr =3D memmap[VIRT_APLIC_M].base + (memmap[VIRT_APLIC_M].size * socket); aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(mc->fdt, aplic_name); - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,apli= c"); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,apli= c"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_m_phandle); } - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", aplic_s_phandle); - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, aplic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle); g_free(aplic_name); =20 /* S-level APLIC node */ @@ -676,27 +676,27 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_addr =3D memmap[VIRT_APLIC_S].base + (memmap[VIRT_APLIC_S].size * socket); aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(mc->fdt, aplic_name); - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,apli= c"); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,apli= c"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_s_phandle); } - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, aplic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle); =20 if (!socket) { - platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, + platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, memmap[VIRT_PLATFORM_BUS].base, memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); @@ -711,13 +711,13 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, static void create_fdt_pmu(RISCVVirtState *s) { char *pmu_name; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); RISCVCPU hart =3D s->soc[0].harts[0]; =20 pmu_name =3D g_strdup_printf("/soc/pmu"); - qemu_fdt_add_subnode(mc->fdt, pmu_name); - qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); - riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); + qemu_fdt_add_subnode(ms->fdt, pmu_name); + qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); =20 g_free(pmu_name); } @@ -731,26 +731,26 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, { char *clust_name; int socket, phandle_pos; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); uint32_t msi_m_phandle =3D 0, msi_s_phandle =3D 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; - int socket_count =3D riscv_socket_count(mc); + int socket_count =3D riscv_socket_count(ms); =20 - qemu_fdt_add_subnode(mc->fdt, "/cpus"); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", + qemu_fdt_add_subnode(ms->fdt, "/cpus"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); - qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); =20 - intc_phandles =3D g_new0(uint32_t, mc->smp.cpus); + intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); =20 - phandle_pos =3D mc->smp.cpus; + phandle_pos =3D ms->smp.cpus; for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { phandle_pos -=3D s->soc[socket].num_harts; =20 clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); - qemu_fdt_add_subnode(mc->fdt, clust_name); + qemu_fdt_add_subnode(ms->fdt, clust_name); =20 create_fdt_socket_cpus(s, socket, clust_name, phandle, &intc_phandles[phandle_pos]); @@ -776,7 +776,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, *msi_pcie_phandle =3D msi_s_phandle; } =20 - phandle_pos =3D mc->smp.cpus; + phandle_pos =3D ms->smp.cpus; for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { phandle_pos -=3D s->soc[socket].num_harts; =20 @@ -807,7 +807,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, } } =20 - riscv_socket_fdt_write_distance_matrix(mc); + riscv_socket_fdt_write_distance_matrix(ms); } =20 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, @@ -815,23 +815,23 @@ static void create_fdt_virtio(RISCVVirtState *s, cons= t MemMapEntry *memmap, { int i; char *name; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); =20 for (i =3D 0; i < VIRTIO_COUNT; i++) { name =3D g_strdup_printf("/soc/virtio_mmio@%lx", (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size= )); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"= ); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"= ); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 0x0, memmap[VIRT_VIRTIO].size); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_virtio_phandle); if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", VIRTIO_IRQ + i); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", VIRTIO_IRQ + i, 0x4); } g_free(name); @@ -843,29 +843,29 @@ static void create_fdt_pcie(RISCVVirtState *s, const = MemMapEntry *memmap, uint32_t msi_pcie_phandle) { char *name; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); =20 name =3D g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "pci-host-ecam-generic"); - qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); - qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); - qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, + qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); + qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); - qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { - qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandl= e); + qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandl= e); } - qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); - qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", + qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 1, FDT_PCI_RANGE_IOPORT, 2, 0, 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 1, FDT_PCI_RANGE_MMIO, @@ -875,7 +875,7 @@ static void create_fdt_pcie(RISCVVirtState *s, const Me= mMapEntry *memmap, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); =20 - create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); + create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); g_free(name); } =20 @@ -884,39 +884,39 @@ static void create_fdt_reset(RISCVVirtState *s, const= MemMapEntry *memmap, { char *name; uint32_t test_phandle; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); =20 test_phandle =3D (*phandle)++; name =3D g_strdup_printf("/soc/test@%lx", (long)memmap[VIRT_TEST].base); - qemu_fdt_add_subnode(mc->fdt, name); + qemu_fdt_add_subnode(ms->fdt, name); { static const char * const compat[3] =3D { "sifive,test1", "sifive,test0", "syscon" }; - qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", + qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", (char **)&compat, ARRAY_SIZE(compat)= ); } - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); - qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); - test_phandle =3D qemu_fdt_get_phandle(mc->fdt, name); + qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); + test_phandle =3D qemu_fdt_get_phandle(ms->fdt, name); g_free(name); =20 name =3D g_strdup_printf("/reboot"); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); g_free(name); =20 name =3D g_strdup_printf("/poweroff"); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"= ); - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"= ); + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); g_free(name); } =20 @@ -924,24 +924,24 @@ static void create_fdt_uart(RISCVVirtState *s, const = MemMapEntry *memmap, uint32_t irq_mmio_phandle) { char *name; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); =20 name =3D g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].b= ase); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_UART0].base, 0x0, memmap[VIRT_UART0].size); - qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phan= dle); + qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phan= dle); if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4= ); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4= ); } =20 - qemu_fdt_add_subnode(mc->fdt, "/chosen"); - qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); + qemu_fdt_add_subnode(ms->fdt, "/chosen"); + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); g_free(name); } =20 @@ -949,20 +949,20 @@ static void create_fdt_rtc(RISCVVirtState *s, const M= emMapEntry *memmap, uint32_t irq_mmio_phandle) { char *name; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); =20 name =3D g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "google,goldfish-rtc"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); } g_free(name); } @@ -970,68 +970,68 @@ static void create_fdt_rtc(RISCVVirtState *s, const M= emMapEntry *memmap, static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) { char *name; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; =20 name =3D g_strdup_printf("/flash@%" PRIx64, flashbase); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); - qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, flashbase, 2, flashsize, 2, flashbase + flashsize, 2, flashsize); - qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); + qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); g_free(name); } =20 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) { char *nodename; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); hwaddr base =3D memmap[VIRT_FW_CFG].base; hwaddr size =3D memmap[VIRT_FW_CFG].size; =20 nodename =3D g_strdup_printf("/fw-cfg@%" PRIx64, base); - qemu_fdt_add_subnode(mc->fdt, nodename); - qemu_fdt_setprop_string(mc->fdt, nodename, + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "qemu,fw-cfg-mmio"); - qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); - qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); g_free(nodename); } =20 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) { - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; uint32_t irq_pcie_phandle =3D 1, irq_virtio_phandle =3D 1; uint8_t rng_seed[32]; =20 - if (mc->dtb) { - mc->fdt =3D load_device_tree(mc->dtb, &s->fdt_size); - if (!mc->fdt) { + if (ms->dtb) { + ms->fdt =3D load_device_tree(ms->dtb, &s->fdt_size); + if (!ms->fdt) { error_report("load_device_tree() failed"); exit(1); } } else { - mc->fdt =3D create_device_tree(&s->fdt_size); - if (!mc->fdt) { + ms->fdt =3D create_device_tree(&s->fdt_size); + if (!ms->fdt) { error_report("create_device_tree() failed"); exit(1); } } =20 - qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); - qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); - qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); - qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); + qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); + qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); =20 - qemu_fdt_add_subnode(mc->fdt, "/soc"); - qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); - qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); + qemu_fdt_add_subnode(ms->fdt, "/soc"); + qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); + qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); =20 create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, @@ -1053,7 +1053,7 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap) =20 /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); } =20 @@ -1106,14 +1106,14 @@ static inline DeviceState *gpex_pcie_init(MemoryReg= ion *sys_mem, return dev; } =20 -static FWCfgState *create_fw_cfg(const MachineState *mc) +static FWCfgState *create_fw_cfg(const MachineState *ms) { hwaddr base =3D virt_memmap[VIRT_FW_CFG].base; FWCfgState *fw_cfg; =20 fw_cfg =3D fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, &address_space_memory); - fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); =20 return fw_cfg; } --=20 2.39.0 From nobody Fri Apr 26 18:32:57 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673457813; cv=none; d=zohomail.com; s=zohoarc; b=aH+X2trJTXvD/TIEMCVx9E62fq4kXur5Sdlhf83FHJ8j+7waM/UgYlJHZIn+ESSaxDErrugEAkDOmPT/x+PAlbanMPcy6Q4n1eq/9XHCwHGjeH0SJORam3ebMatyvYO+s2Re1EAQw86mwn9gjebg2Gb9xpJQliWxYnwojHWj/XQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673457813; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ncd/T/HTYU2+SGGnKfXa9OlGfj8OLblc1pqxQ33fLME=; b=LX/EAVSLCB0cN6yGOH1s3qiCmsk/WpaqwTBI1YsFAX4JPT8xo4FRkCFqFBSDhx0hst WJI2OMinY+7F7GMo+PRolm4g5E3H0Hca51ywjkEqQLLj9MivelV+206+hscUz44e02IP 1mCNHOF+nkFhpdKpVZGGaFBASDJOXabXj3clG8qE2e7gMs2ue2E0drporXLXh/3oBHgd gj/uTFgirIBGfogbSOfR4cRjsLLhjRVgd9A/akttc6P9AIqWSquHOgV1Ors9iWj/TQdL b4L4QMilJ3l9AUcUynKseiaP4Q5Ev7z4JF6g4FWa3on6W+Au/XZ0zSti/JJ6GaC2xmZM NC9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ncd/T/HTYU2+SGGnKfXa9OlGfj8OLblc1pqxQ33fLME=; b=CsGwqz427GLVr/gnUX5gjMRVAgGwIniMa+nG0BPiR20sX9uegZ69iqA2+E3SjqXMMi NvbALr7JZADTbGVj7I7JY3efBjI56YNnR4NXMz4+hEU3W3MzSOyes/SmGUwL/0a+YNK4 0F84OGWdVWNQb0FFedbWUyOZd9vq+KSO89/96wvmAJGRe4pKv8QkCKha583GWIRlHbCp BohopuEXTn+ABKNMgLMp71c//J512LusWzbGK3UbBxgneSiRMLfGHx9XsodT0ILIJsoJ EGgEaKZM8od7robRq3Z4/DvGIzbo72mwHRfurTEWNyQbCXQjKQsDxQF/JIcrvc7Bl6ln ailQ== X-Gm-Message-State: AFqh2kp6QHM18V5WYomriB75Fpj1uHMR3BcFKL1NVsak99trtKc98n5h qgFCyOfEnSiRmDzRyQVcPDtPq0uD6bJ3Ogb04uY= X-Google-Smtp-Source: AMrXdXsTdpf7lWzswffCunF8bDyR8JT+B5lvLZbJOLpLFTp7/tebdAVOwcFcD7laGcnUws1EwZsj1g== X-Received: by 2002:a4a:894f:0:b0:4f2:9e:3e9e with SMTP id g15-20020a4a894f000000b004f2009e3e9emr4480612ooi.5.1673457016297; Wed, 11 Jan 2023 09:10:16 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 10/10] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Date: Wed, 11 Jan 2023 14:09:48 -0300 Message-Id: <20230111170948.316276-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673457815842100001 Follow the QEMU convention of naming MachineState pointers as 'ms' by renaming the instances where we're calling it 'mc'. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/spike.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 82093dd2cb..d753fb1f31 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -56,7 +56,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *= memmap, uint64_t addr, size; unsigned long clint_addr; int cpu, socket; - MachineState *mc =3D MACHINE(s); + MachineState *ms =3D MACHINE(s); uint32_t *clint_cells; uint32_t cpu_phandle, intc_phandle, phandle =3D 1; char *name, *mem_name, *clint_name, *clust_name; @@ -65,7 +65,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *= memmap, "sifive,clint0", "riscv,clint0" }; =20 - fdt =3D mc->fdt =3D create_device_tree(&fdt_size); + fdt =3D ms->fdt =3D create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -96,7 +96,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *= memmap, qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); =20 - for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket--)= { + for (socket =3D (riscv_socket_count(ms) - 1); socket >=3D 0; socket--)= { clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); qemu_fdt_add_subnode(fdt, clust_name); =20 @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, qemu_fdt_setprop_cell(fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, cpu_name, socket); + riscv_socket_fdt_write_id(ms, cpu_name, socket); qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); =20 intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_n= ame); @@ -147,14 +147,14 @@ static void create_fdt(SpikeState *s, const MemMapEnt= ry *memmap, g_free(cpu_name); } =20 - addr =3D memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, soc= ket); - size =3D riscv_socket_mem_size(mc, socket); + addr =3D memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, soc= ket); + size =3D riscv_socket_mem_size(ms, socket); mem_name =3D g_strdup_printf("/memory@%lx", (long)addr); qemu_fdt_add_subnode(fdt, mem_name); qemu_fdt_setprop_cells(fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mem_name, socket); + riscv_socket_fdt_write_id(ms, mem_name, socket); g_free(mem_name); =20 clint_addr =3D memmap[SPIKE_CLINT].base + @@ -167,14 +167,14 @@ static void create_fdt(SpikeState *s, const MemMapEnt= ry *memmap, 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, clint_name, socket); + riscv_socket_fdt_write_id(ms, clint_name, socket); =20 g_free(clint_name); g_free(clint_cells); g_free(clust_name); } =20 - riscv_socket_fdt_write_distance_matrix(mc); + riscv_socket_fdt_write_distance_matrix(ms); =20 qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); --=20 2.39.0