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Tsirkin" , Marcel Apfelbaum , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Wainer dos Santos Moschetta , Beraldo Leal , Cleber Rosa , Laurent Vivier , Paolo Bonzini , Alexander Bulekov , Bandan Das , Stefan Hajnoczi , Darren Kenny , Qiuhao Li , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, devel@daynix.com, Yan Vugenfirer , Yuri Benditovich , Sriram Yagnaraman Subject: [PATCH 29/31] tests/qtest/libqos/igb: Transform to igb tests Date: Thu, 12 Jan 2023 18:57:41 +0900 Message-Id: <20230112095743.20123-30-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230112095743.20123-1-akihiko.odaki@daynix.com> References: <20230112095743.20123-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::62a; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1673517992920100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Akihiko Odaki --- tests/qtest/fuzz/generic_fuzz_configs.h | 5 + tests/qtest/igb-test.c | 67 ++++++------ tests/qtest/libqos/igb.c | 139 +++++++++--------------- tests/qtest/libqos/meson.build | 1 + tests/qtest/meson.build | 1 + 5 files changed, 90 insertions(+), 123 deletions(-) diff --git a/tests/qtest/fuzz/generic_fuzz_configs.h b/tests/qtest/fuzz/gen= eric_fuzz_configs.h index a825b78c14..50689da653 100644 --- a/tests/qtest/fuzz/generic_fuzz_configs.h +++ b/tests/qtest/fuzz/generic_fuzz_configs.h @@ -90,6 +90,11 @@ const generic_fuzz_config predefined_configs[] =3D { .args =3D "-M q35 -nodefaults " "-device e1000e,netdev=3Dnet0 -netdev user,id=3Dnet0", .objects =3D "e1000e", + },{ + .name =3D "igb", + .args =3D "-M q35 -nodefaults " + "-device igb,netdev=3Dnet0 -netdev user,id=3Dnet0", + .objects =3D "igb", },{ .name =3D "cirrus-vga", .args =3D "-machine q35 -nodefaults -device cirrus-vga", diff --git a/tests/qtest/igb-test.c b/tests/qtest/igb-test.c index 98706355e3..17d408f02a 100644 --- a/tests/qtest/igb-test.c +++ b/tests/qtest/igb-test.c @@ -1,10 +1,12 @@ /* - * QTest testcase for e1000e NIC + * QTest testcase for igb NIC * + * Copyright (c) 2022-2023 Red Hat, Inc. * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) * Developed by Daynix Computing LTD (http://www.daynix.com) * * Authors: + * Akihiko Odaki * Dmitry Fleytman * Leonid Bloch * Yan Vugenfirer @@ -34,16 +36,16 @@ #include "qemu/bitops.h" #include "libqos/libqos-malloc.h" #include "libqos/e1000e.h" -#include "hw/net/e1000_regs.h" +#include "hw/net/igb_regs.h" =20 static const struct eth_header test =3D { .h_dest =3D E1000E_ADDRESS, .h_source =3D E1000E_ADDRESS, }; =20 -static void e1000e_send_verify(QE1000E *d, int *test_sockets, QGuestAlloca= tor *alloc) +static void igb_send_verify(QE1000E *d, int *test_sockets, QGuestAllocator= *alloc) { - struct e1000_tx_desc descr; + union e1000_adv_tx_desc descr; char buffer[64]; int ret; uint32_t recv_len; @@ -54,12 +56,11 @@ static void e1000e_send_verify(QE1000E *d, int *test_so= ckets, QGuestAllocator *a =20 /* Prepare TX descriptor */ memset(&descr, 0, sizeof(descr)); - descr.buffer_addr =3D cpu_to_le64(data); - descr.lower.data =3D cpu_to_le32(E1000_TXD_CMD_RS | - E1000_TXD_CMD_EOP | - E1000_TXD_CMD_DEXT | - E1000_TXD_DTYP_D | - sizeof(buffer)); + descr.read.buffer_addr =3D cpu_to_le64(data); + descr.read.cmd_type_len =3D cpu_to_le32(E1000_TXD_CMD_RS | + E1000_TXD_CMD_EOP | + E1000_TXD_DTYP_D | + sizeof(buffer)); =20 /* Put descriptor to the ring */ e1000e_tx_ring_push(d, &descr); @@ -68,7 +69,7 @@ static void e1000e_send_verify(QE1000E *d, int *test_sock= ets, QGuestAllocator *a e1000e_wait_isr(d, E1000E_TX0_MSG_ID); =20 /* Check DD bit */ - g_assert_cmphex(le32_to_cpu(descr.upper.data) & E1000_TXD_STAT_DD, =3D= =3D, + g_assert_cmphex(le32_to_cpu(descr.wb.status) & E1000_TXD_STAT_DD, =3D= =3D, E1000_TXD_STAT_DD); =20 /* Check data sent to the backend */ @@ -82,9 +83,9 @@ static void e1000e_send_verify(QE1000E *d, int *test_sock= ets, QGuestAllocator *a guest_free(alloc, data); } =20 -static void e1000e_receive_verify(QE1000E *d, int *test_sockets, QGuestAll= ocator *alloc) +static void igb_receive_verify(QE1000E *d, int *test_sockets, QGuestAlloca= tor *alloc) { - union e1000_rx_desc_extended descr; + union e1000_adv_rx_desc descr; =20 struct eth_header test_iov =3D test; int len =3D htonl(sizeof(test)); @@ -110,7 +111,7 @@ static void e1000e_receive_verify(QE1000E *d, int *test= _sockets, QGuestAllocator =20 /* Prepare RX descriptor */ memset(&descr, 0, sizeof(descr)); - descr.read.buffer_addr =3D cpu_to_le64(data); + descr.read.pkt_addr =3D cpu_to_le64(data); =20 /* Put descriptor to the ring */ e1000e_rx_ring_push(d, &descr); @@ -135,7 +136,7 @@ static void test_e1000e_init(void *obj, void *data, QGu= estAllocator * alloc) /* init does nothing */ } =20 -static void test_e1000e_tx(void *obj, void *data, QGuestAllocator * alloc) +static void test_igb_tx(void *obj, void *data, QGuestAllocator * alloc) { QE1000E_PCI *e1000e =3D obj; QE1000E *d =3D &e1000e->e1000e; @@ -147,10 +148,10 @@ static void test_e1000e_tx(void *obj, void *data, QGu= estAllocator * alloc) return; } =20 - e1000e_send_verify(d, data, alloc); + igb_send_verify(d, data, alloc); } =20 -static void test_e1000e_rx(void *obj, void *data, QGuestAllocator * alloc) +static void test_igb_rx(void *obj, void *data, QGuestAllocator * alloc) { QE1000E_PCI *e1000e =3D obj; QE1000E *d =3D &e1000e->e1000e; @@ -162,11 +163,11 @@ static void test_e1000e_rx(void *obj, void *data, QGu= estAllocator * alloc) return; } =20 - e1000e_receive_verify(d, data, alloc); + igb_receive_verify(d, data, alloc); } =20 -static void test_e1000e_multiple_transfers(void *obj, void *data, - QGuestAllocator *alloc) +static void test_igb_multiple_transfers(void *obj, void *data, + QGuestAllocator *alloc) { static const long iterations =3D 4 * 1024; long i; @@ -182,13 +183,13 @@ static void test_e1000e_multiple_transfers(void *obj,= void *data, } =20 for (i =3D 0; i < iterations; i++) { - e1000e_send_verify(d, data, alloc); - e1000e_receive_verify(d, data, alloc); + igb_send_verify(d, data, alloc); + igb_receive_verify(d, data, alloc); } =20 } =20 -static void test_e1000e_hotplug(void *obj, void *data, QGuestAllocator * a= lloc) +static void test_igb_hotplug(void *obj, void *data, QGuestAllocator * allo= c) { QTestState *qts =3D global_qtest; /* TODO: get rid of global_qtest he= re */ QE1000E_PCI *dev =3D obj; @@ -198,8 +199,8 @@ static void test_e1000e_hotplug(void *obj, void *data, = QGuestAllocator * alloc) return; } =20 - qtest_qmp_device_add(qts, "e1000e", "e1000e_net", "{'addr': '0x06'}"); - qpci_unplug_acpi_device_test(qts, "e1000e_net", 0x06); + qtest_qmp_device_add(qts, "igb", "igb_net", "{'addr': '0x06'}"); + qpci_unplug_acpi_device_test(qts, "igb_net", 0x06); } =20 static void data_test_clear(void *sockets) @@ -225,18 +226,18 @@ static void *data_test_init(GString *cmd_line, void *= arg) return test_sockets; } =20 -static void register_e1000e_test(void) +static void register_igb_test(void) { QOSGraphTestOptions opts =3D { .before =3D data_test_init, }; =20 - qos_add_test("init", "e1000e", test_e1000e_init, &opts); - qos_add_test("tx", "e1000e", test_e1000e_tx, &opts); - qos_add_test("rx", "e1000e", test_e1000e_rx, &opts); - qos_add_test("multiple_transfers", "e1000e", - test_e1000e_multiple_transfers, &opts); - qos_add_test("hotplug", "e1000e", test_e1000e_hotplug, &opts); + qos_add_test("init", "igb", test_e1000e_init, &opts); + qos_add_test("tx", "igb", test_igb_tx, &opts); + qos_add_test("rx", "igb", test_igb_rx, &opts); + qos_add_test("multiple_transfers", "igb", + test_igb_multiple_transfers, &opts); + qos_add_test("hotplug", "igb", test_igb_hotplug, &opts); } =20 -libqos_init(register_e1000e_test); +libqos_init(register_igb_test); diff --git a/tests/qtest/libqos/igb.c b/tests/qtest/libqos/igb.c index 925654c7fd..12fb531bf0 100644 --- a/tests/qtest/libqos/igb.c +++ b/tests/qtest/libqos/igb.c @@ -1,6 +1,7 @@ /* * libqos driver framework * + * Copyright (c) 2022-2023 Red Hat, Inc. * Copyright (c) 2018 Emanuele Giuseppe Esposito * * This library is free software; you can redistribute it and/or @@ -17,7 +18,8 @@ */ =20 #include "qemu/osdep.h" -#include "hw/net/e1000_regs.h" +#include "hw/net/igb_regs.h" +#include "hw/net/mii.h" #include "hw/pci/pci_ids.h" #include "../libqtest.h" #include "pci-pc.h" @@ -29,47 +31,12 @@ #include "qgraph.h" #include "e1000e.h" =20 -#define E1000E_IVAR_TEST_CFG \ - (((E1000E_RX0_MSG_ID | E1000_IVAR_INT_ALLOC_VALID) << E1000_IVAR_RXQ0_= SHIFT) | \ - ((E1000E_TX0_MSG_ID | E1000_IVAR_INT_ALLOC_VALID) << E1000_IVAR_TXQ0_= SHIFT) | \ - E1000_IVAR_TX_INT_EVERY_WB) +#define IGB_IVAR_TEST_CFG \ + ((E1000E_RX0_MSG_ID | E1000_IVAR_VALID) << (igb_ivar_entry_rx(0) * 8) = | \ + ((E1000E_TX0_MSG_ID | E1000_IVAR_VALID) << (igb_ivar_entry_tx(0) * 8)= )) =20 #define E1000E_RING_LEN (0x1000) =20 -void e1000e_tx_ring_push(QE1000E *d, void *descr) -{ - QE1000E_PCI *d_pci =3D container_of(d, QE1000E_PCI, e1000e); - uint32_t tail =3D e1000e_macreg_read(d, E1000_TDT); - uint32_t len =3D e1000e_macreg_read(d, E1000_TDLEN) / E1000_RING_DESC_= LEN; - - qtest_memwrite(d_pci->pci_dev.bus->qts, - d->tx_ring + tail * E1000_RING_DESC_LEN, - descr, E1000_RING_DESC_LEN); - e1000e_macreg_write(d, E1000_TDT, (tail + 1) % len); - - /* Read WB data for the packet transmitted */ - qtest_memread(d_pci->pci_dev.bus->qts, - d->tx_ring + tail * E1000_RING_DESC_LEN, - descr, E1000_RING_DESC_LEN); -} - -void e1000e_rx_ring_push(QE1000E *d, void *descr) -{ - QE1000E_PCI *d_pci =3D container_of(d, QE1000E_PCI, e1000e); - uint32_t tail =3D e1000e_macreg_read(d, E1000_RDT); - uint32_t len =3D e1000e_macreg_read(d, E1000_RDLEN) / E1000_RING_DESC_= LEN; - - qtest_memwrite(d_pci->pci_dev.bus->qts, - d->rx_ring + tail * E1000_RING_DESC_LEN, - descr, E1000_RING_DESC_LEN); - e1000e_macreg_write(d, E1000_RDT, (tail + 1) % len); - - /* Read WB data for the packet received */ - qtest_memread(d_pci->pci_dev.bus->qts, - d->rx_ring + tail * E1000_RING_DESC_LEN, - descr, E1000_RING_DESC_LEN); -} - static void e1000e_foreach_callback(QPCIDevice *dev, int devfn, void *data) { QPCIDevice *res =3D data; @@ -77,21 +44,6 @@ static void e1000e_foreach_callback(QPCIDevice *dev, int= devfn, void *data) g_free(dev); } =20 -void e1000e_wait_isr(QE1000E *d, uint16_t msg_id) -{ - QE1000E_PCI *d_pci =3D container_of(d, QE1000E_PCI, e1000e); - guint64 end_time =3D g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; - - do { - if (qpci_msix_pending(&d_pci->pci_dev, msg_id)) { - return; - } - qtest_clock_step(d_pci->pci_dev.bus->qts, 10000); - } while (g_get_monotonic_time() < end_time); - - g_error("Timeout expired"); -} - static void e1000e_pci_destructor(QOSGraphObject *obj) { QE1000E_PCI *epci =3D (QE1000E_PCI *) obj; @@ -99,8 +51,9 @@ static void e1000e_pci_destructor(QOSGraphObject *obj) qpci_msix_disable(&epci->pci_dev); } =20 -static void e1000e_pci_start_hw(QOSGraphObject *obj) +static void igb_pci_start_hw(QOSGraphObject *obj) { + static const uint8_t address[] =3D E1000E_ADDRESS; QE1000E_PCI *d =3D (QE1000E_PCI *) obj; uint32_t val; =20 @@ -111,58 +64,65 @@ static void e1000e_pci_start_hw(QOSGraphObject *obj) val =3D e1000e_macreg_read(&d->e1000e, E1000_CTRL); e1000e_macreg_write(&d->e1000e, E1000_CTRL, val | E1000_CTRL_RST | E10= 00_CTRL_SLU); =20 + /* Setup link */ + e1000e_macreg_write(&d->e1000e, E1000_MDIC, + MII_BMCR_AUTOEN | MII_BMCR_ANRESTART | + (MII_BMCR << E1000_MDIC_REG_SHIFT) | + (1 << E1000_MDIC_PHY_SHIFT) | + E1000_MDIC_OP_WRITE); + + qtest_clock_step(d->pci_dev.bus->qts, 900000000); + /* Enable and configure MSI-X */ qpci_msix_enable(&d->pci_dev); - e1000e_macreg_write(&d->e1000e, E1000_IVAR, E1000E_IVAR_TEST_CFG); + e1000e_macreg_write(&d->e1000e, E1000_IVAR0, IGB_IVAR_TEST_CFG); =20 - /* Check the device status - link and speed */ + /* Check the device link status */ val =3D e1000e_macreg_read(&d->e1000e, E1000_STATUS); - g_assert_cmphex(val & (E1000_STATUS_LU | E1000_STATUS_ASDV_1000), - =3D=3D, E1000_STATUS_LU | E1000_STATUS_ASDV_1000); + g_assert_cmphex(val & E1000_STATUS_LU, =3D=3D, E1000_STATUS_LU); =20 /* Initialize TX/RX logic */ e1000e_macreg_write(&d->e1000e, E1000_RCTL, 0); e1000e_macreg_write(&d->e1000e, E1000_TCTL, 0); =20 - /* Notify the device that the driver is ready */ - val =3D e1000e_macreg_read(&d->e1000e, E1000_CTRL_EXT); - e1000e_macreg_write(&d->e1000e, E1000_CTRL_EXT, - val | E1000_CTRL_EXT_DRV_LOAD); - - e1000e_macreg_write(&d->e1000e, E1000_TDBAL, + e1000e_macreg_write(&d->e1000e, E1000_TDBAL(0), (uint32_t) d->e1000e.tx_ring); - e1000e_macreg_write(&d->e1000e, E1000_TDBAH, + e1000e_macreg_write(&d->e1000e, E1000_TDBAH(0), (uint32_t) (d->e1000e.tx_ring >> 32)); - e1000e_macreg_write(&d->e1000e, E1000_TDLEN, E1000E_RING_LEN); - e1000e_macreg_write(&d->e1000e, E1000_TDT, 0); - e1000e_macreg_write(&d->e1000e, E1000_TDH, 0); + e1000e_macreg_write(&d->e1000e, E1000_TDLEN(0), E1000E_RING_LEN); + e1000e_macreg_write(&d->e1000e, E1000_TDT(0), 0); + e1000e_macreg_write(&d->e1000e, E1000_TDH(0), 0); =20 /* Enable transmit */ e1000e_macreg_write(&d->e1000e, E1000_TCTL, E1000_TCTL_EN); =20 - e1000e_macreg_write(&d->e1000e, E1000_RDBAL, + e1000e_macreg_write(&d->e1000e, E1000_RDBAL(0), (uint32_t)d->e1000e.rx_ring); - e1000e_macreg_write(&d->e1000e, E1000_RDBAH, + e1000e_macreg_write(&d->e1000e, E1000_RDBAH(0), (uint32_t)(d->e1000e.rx_ring >> 32)); - e1000e_macreg_write(&d->e1000e, E1000_RDLEN, E1000E_RING_LEN); - e1000e_macreg_write(&d->e1000e, E1000_RDT, 0); - e1000e_macreg_write(&d->e1000e, E1000_RDH, 0); + e1000e_macreg_write(&d->e1000e, E1000_RDLEN(0), E1000E_RING_LEN); + e1000e_macreg_write(&d->e1000e, E1000_RDT(0), 0); + e1000e_macreg_write(&d->e1000e, E1000_RDH(0), 0); + e1000e_macreg_write(&d->e1000e, E1000_RA, + le32_to_cpu(*(uint32_t *)address)); + e1000e_macreg_write(&d->e1000e, E1000_RA + 4, + E1000_RAH_AV | E1000_RAH_POOL_1 | + le16_to_cpu(*(uint16_t *)(address + 4))); =20 /* Enable receive */ e1000e_macreg_write(&d->e1000e, E1000_RFCTL, E1000_RFCTL_EXTEN); - e1000e_macreg_write(&d->e1000e, E1000_RCTL, E1000_RCTL_EN | - E1000_RCTL_UPE | - E1000_RCTL_MPE); + e1000e_macreg_write(&d->e1000e, E1000_RCTL, E1000_RCTL_EN); =20 /* Enable all interrupts */ - e1000e_macreg_write(&d->e1000e, E1000_IMS, 0xFFFFFFFF); + e1000e_macreg_write(&d->e1000e, E1000_IMS, 0xFFFFFFFF); + e1000e_macreg_write(&d->e1000e, E1000_EIMS, 0xFFFFFFFF); =20 } =20 -static void *e1000e_pci_get_driver(void *obj, const char *interface) +static void *igb_pci_get_driver(void *obj, const char *interface) { QE1000E_PCI *epci =3D obj; - if (!g_strcmp0(interface, "e1000e-if")) { + if (!g_strcmp0(interface, "igb-if")) { return &epci->e1000e; } =20 @@ -171,12 +131,11 @@ static void *e1000e_pci_get_driver(void *obj, const c= har *interface) return &epci->pci_dev; } =20 - fprintf(stderr, "%s not present in e1000e\n", interface); + fprintf(stderr, "%s not present in igb\n", interface); g_assert_not_reached(); } =20 -static void *e1000e_pci_create(void *pci_bus, QGuestAllocator *alloc, - void *addr) +static void *igb_pci_create(void *pci_bus, QGuestAllocator *alloc, void *a= ddr) { QE1000E_PCI *d =3D g_new0(QE1000E_PCI, 1); QPCIBus *bus =3D pci_bus; @@ -196,18 +155,18 @@ static void *e1000e_pci_create(void *pci_bus, QGuestA= llocator *alloc, d->e1000e.rx_ring =3D guest_alloc(alloc, E1000E_RING_LEN); g_assert(d->e1000e.rx_ring !=3D 0); =20 - d->obj.get_driver =3D e1000e_pci_get_driver; - d->obj.start_hw =3D e1000e_pci_start_hw; + d->obj.get_driver =3D igb_pci_get_driver; + d->obj.start_hw =3D igb_pci_start_hw; d->obj.destructor =3D e1000e_pci_destructor; =20 return &d->obj; } =20 -static void e1000e_register_nodes(void) +static void igb_register_nodes(void) { QPCIAddress addr =3D { .vendor_id =3D PCI_VENDOR_ID_INTEL, - .device_id =3D E1000_DEV_ID_82574L, + .device_id =3D E1000_DEV_ID_82576, }; =20 /* @@ -219,8 +178,8 @@ static void e1000e_register_nodes(void) }; add_qpci_address(&opts, &addr); =20 - qos_node_create_driver("e1000e", e1000e_pci_create); - qos_node_consumes("e1000e", "pci-bus", &opts); + qos_node_create_driver("igb", igb_pci_create); + qos_node_consumes("igb", "pci-bus", &opts); } =20 -libqos_init(e1000e_register_nodes); +libqos_init(igb_register_nodes); diff --git a/tests/qtest/libqos/meson.build b/tests/qtest/libqos/meson.build index 32f028872c..cc209a8de5 100644 --- a/tests/qtest/libqos/meson.build +++ b/tests/qtest/libqos/meson.build @@ -30,6 +30,7 @@ libqos_srcs =3D files( 'i2c.c', 'i2c-imx.c', 'i2c-omap.c', + 'igb.c', 'sdhci.c', 'tpci200.c', 'virtio.c', diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index f0ebb5fac6..10279ed3bf 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -256,6 +256,7 @@ qos_test_ss.add( 'virtio-serial-test.c', 'virtio-iommu-test.c', 'vmxnet3-test.c', + 'igb-test.c', ) if config_host.has_key('CONFIG_POSIX') qos_test_ss.add(files('e1000e-test.c')) --=20 2.39.0