Hi,

These are the 2 remaining patches, patches 10 and 11, of:

"[PATCH v5 00/11] riscv: OpenSBI boot test and cleanups"

The first 9 patches are already available in riscv-to-apply.next. 

The only change made was in patch 10 where we're now handling the case
where load_elf_ram_sym is padding the resulting kernel_entry with 1s for
32 bits. Patch 11 is unchanged.

Changes from v5:
- former patches 1-9: already pushed to riscv-to-apply.next
- patch 10:
  - added an 'is_32bit' flag in riscv_load_kernel(). Use it to eliminate the
  sign-extension from load_elf() if we're running a 32-bit guest.
v5 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg00051.html

Daniel Henrique Barboza (2):
  hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
  hw/riscv/boot.c: make riscv_load_initrd() static

 hw/riscv/boot.c            | 98 ++++++++++++++++++++++++--------------
 hw/riscv/microchip_pfsoc.c | 12 +----
 hw/riscv/opentitan.c       |  3 +-
 hw/riscv/sifive_e.c        |  4 +-
 hw/riscv/sifive_u.c        | 13 ++---
 hw/riscv/spike.c           | 10 +---
 hw/riscv/virt.c            | 13 ++---
 include/hw/riscv/boot.h    |  3 +-
 8 files changed, 77 insertions(+), 79 deletions(-)

-- 
2.39.0