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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1673618823; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=M8GtUMzNwfhihhOG15xJRQ6eN0+OBvVcoq7KwxHxFAU=; b=M6KPQN+fP56lGXYn7/n2R0bl5TQj8VnHC9qfOdjJzCbSOCazvBf8ZEHDvLfSW2LS6MzqdG GtRbqoozQtGymHCA== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf Subject: [RFC PATCH v3 12/28] target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled Date: Fri, 13 Jan 2023 11:04:03 -0300 Message-Id: <20230113140419.4013-13-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230113140419.4013-1-farosas@suse.de> References: <20230113140419.4013-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.28; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1673623793172100001 Content-Type: text/plain; charset="utf-8" This is in preparation to moving the hflags code into its own file under the tcg/ directory. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- I extracted these into a separate patch so we can discuss. If I move the tcg_enabled check to a header that would add overhead for all the calls where we know for sure that the code is running with TCG. And I don't think we want a new arm_rebuild_hflags_foo to be used for common code. --- hw/arm/boot.c | 6 +++++- hw/intc/armv7m_nvic.c | 20 +++++++++++++------- target/arm/arm-powerctl.c | 7 +++++-- target/arm/cpregs.c | 2 +- target/arm/cpu.c | 3 ++- target/arm/helper.c | 16 ++++++++++++---- target/arm/machine.c | 5 ++++- 7 files changed, 42 insertions(+), 17 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 3d7d11f782..1e021c4a34 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -15,6 +15,7 @@ #include "hw/arm/boot.h" #include "hw/arm/linux-boot-if.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "sysemu/sysemu.h" #include "sysemu/numa.h" #include "hw/boards.h" @@ -827,7 +828,10 @@ static void do_cpu_reset(void *opaque) info->secondary_cpu_reset_hook(cpu, info); } } - arm_rebuild_hflags(env); + + if (tcg_enabled()) { + arm_rebuild_hflags(env); + } } } =20 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1f7763964c..74ac8f610c 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -18,6 +18,7 @@ #include "hw/intc/armv7m_nvic.h" #include "hw/irq.h" #include "hw/qdev-properties.h" +#include "sysemu/tcg.h" #include "sysemu/runstate.h" #include "target/arm/cpu.h" #include "exec/exec-all.h" @@ -2466,8 +2467,10 @@ static MemTxResult nvic_sysreg_write(void *opaque, h= waddr addr, /* This is UNPREDICTABLE; treat as RAZ/WI */ =20 exit_ok: - /* Ensure any changes made are reflected in the cached hflags. */ - arm_rebuild_hflags(&s->cpu->env); + if (tcg_enabled()) { + /* Ensure any changes made are reflected in the cached hflags. */ + arm_rebuild_hflags(&s->cpu->env); + } return MEMTX_OK; } =20 @@ -2648,11 +2651,14 @@ static void armv7m_nvic_reset(DeviceState *dev) } } =20 - /* - * We updated state that affects the CPU's MMUidx and thus its hflags; - * and we can't guarantee that we run before the CPU reset function. - */ - arm_rebuild_hflags(&s->cpu->env); + if (tcg_enabled()) { + /* + * We updated state that affects the CPU's MMUidx and thus its + * hflags; and we can't guarantee that we run before the CPU + * reset function. + */ + arm_rebuild_hflags(&s->cpu->env); + } } =20 static void nvic_systick_trigger(void *opaque, int n, int level) diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index b75f813b40..326a03153d 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -15,6 +15,7 @@ #include "arm-powerctl.h" #include "qemu/log.h" #include "qemu/main-loop.h" +#include "sysemu/tcg.h" =20 #ifndef DEBUG_ARM_POWERCTL #define DEBUG_ARM_POWERCTL 0 @@ -127,8 +128,10 @@ static void arm_set_cpu_on_async_work(CPUState *target= _cpu_state, target_cpu->env.regs[0] =3D info->context_id; } =20 - /* CP15 update requires rebuilding hflags */ - arm_rebuild_hflags(&target_cpu->env); + if (tcg_enabled()) { + /* CP15 update requires rebuilding hflags */ + arm_rebuild_hflags(&target_cpu->env); + } =20 /* Start the new CPU at the requested address */ cpu_set_pc(target_cpu_state, info->entry); diff --git a/target/arm/cpregs.c b/target/arm/cpregs.c index dee03f8a41..a353fb9b03 100644 --- a/target/arm/cpregs.c +++ b/target/arm/cpregs.c @@ -5179,7 +5179,7 @@ static void sctlr_write(CPUARMState *env, const ARMCP= RegInfo *ri, /* This may enable/disable the MMU, so do a TLB flush. */ tlb_flush(CPU(cpu)); =20 - if (ri->type & ARM_CP_SUPPRESS_TB_END) { + if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) { /* * Normally we would always end the TB on an SCTLR write; see the * comment in ARMCPRegInfo sctlr initialization below for why Xsca= le diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d7ceb626f0..ce1a425e10 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -539,8 +539,9 @@ static void arm_cpu_reset_hold(Object *obj) if (tcg_enabled()) { hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + + arm_rebuild_hflags(env); } - arm_rebuild_hflags(env); } =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0c3e72a266..5188d0ddbf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -340,7 +340,9 @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new, u= int64_t mask) memset(env->zarray, 0, sizeof(env->zarray)); } =20 - arm_rebuild_hflags(env); + if (tcg_enabled()) { + arm_rebuild_hflags(env); + } } #endif /* TARGET_AARCH64 */ =20 @@ -609,7 +611,7 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_= t mask, } mask &=3D ~CACHED_CPSR_BITS; env->uncached_cpsr =3D (env->uncached_cpsr & ~mask) | (val & mask); - if (rebuild_hflags) { + if (tcg_enabled() && rebuild_hflags) { arm_rebuild_hflags(env); } } @@ -1168,7 +1170,10 @@ static void take_aarch32_exception(CPUARMState *env,= int new_mode, env->regs[14] =3D env->regs[15] + offset; } env->regs[15] =3D newpc; - arm_rebuild_hflags(env); + + if (tcg_enabled()) { + arm_rebuild_hflags(env); + } } =20 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -1724,7 +1729,10 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *c= s) pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 =3D true; aarch64_restore_sp(env, new_el); - helper_rebuild_hflags_a64(env, new_el); + + if (tcg_enabled()) { + helper_rebuild_hflags_a64(env, new_el); + } =20 env->pc =3D addr; =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index fd6323f6d8..fc4a4a4064 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -871,7 +871,10 @@ static int cpu_post_load(void *opaque, int version_id) if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } - arm_rebuild_hflags(&cpu->env); + + if (tcg_enabled()) { + arm_rebuild_hflags(&cpu->env); + } =20 return 0; } --=20 2.35.3