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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673627009408100001 It is irrelevant to the API what the buffers to fill are made of. In particular, some MIPS ISA have 16-bit wide instructions. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20221211204533.85359-2-philmd@linaro.org> --- hw/mips/bootloader.c | 55 +++++++++++++++++++++--------------- hw/mips/boston.c | 2 +- hw/mips/fuloong2e.c | 2 +- hw/mips/malta.c | 19 +++++++------ include/hw/mips/bootloader.h | 10 +++---- 5 files changed, 50 insertions(+), 38 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index f5f42f2bf2..21ffd4d772 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -55,16 +55,20 @@ static bool bootcpu_supports_isa(uint64_t isa_mask) } =20 /* Base types */ -static void bl_gen_nop(uint32_t **p) +static void bl_gen_nop(void **ptr) { - stl_p(*p, 0); - *p =3D *p + 1; + uint32_t *p =3D *ptr; + + stl_p(p, 0); + p++; + *ptr =3D p; } =20 -static void bl_gen_r_type(uint32_t **p, uint8_t opcode, +static void bl_gen_r_type(void **ptr, uint8_t opcode, bl_reg rs, bl_reg rt, bl_reg rd, uint8_t shift, uint8_t funct) { + uint32_t *p =3D *ptr; uint32_t insn =3D 0; =20 insn =3D deposit32(insn, 26, 6, opcode); @@ -74,13 +78,16 @@ static void bl_gen_r_type(uint32_t **p, uint8_t opcode, insn =3D deposit32(insn, 6, 5, shift); insn =3D deposit32(insn, 0, 6, funct); =20 - stl_p(*p, insn); - *p =3D *p + 1; + stl_p(p, insn); + p++; + + *ptr =3D p; } =20 -static void bl_gen_i_type(uint32_t **p, uint8_t opcode, +static void bl_gen_i_type(void **ptr, uint8_t opcode, bl_reg rs, bl_reg rt, uint16_t imm) { + uint32_t *p =3D *ptr; uint32_t insn =3D 0; =20 insn =3D deposit32(insn, 26, 6, opcode); @@ -88,12 +95,14 @@ static void bl_gen_i_type(uint32_t **p, uint8_t opcode, insn =3D deposit32(insn, 16, 5, rt); insn =3D deposit32(insn, 0, 16, imm); =20 - stl_p(*p, insn); - *p =3D *p + 1; + stl_p(p, insn); + p++; + + *ptr =3D p; } =20 /* Single instructions */ -static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa) +static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa) { if (bootcpu_supports_isa(ISA_MIPS3)) { bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38); @@ -102,28 +111,28 @@ static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_r= eg rt, uint8_t sa) } } =20 -static void bl_gen_jalr(uint32_t **p, bl_reg rs) +static void bl_gen_jalr(void **p, bl_reg rs) { bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09); } =20 -static void bl_gen_lui(uint32_t **p, bl_reg rt, uint16_t imm) +static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm) { /* R6: It's a alias of AUI with RS =3D 0 */ bl_gen_i_type(p, 0x0f, 0, rt, imm); } =20 -static void bl_gen_ori(uint32_t **p, bl_reg rt, bl_reg rs, uint16_t imm) +static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm) { bl_gen_i_type(p, 0x0d, rs, rt, imm); } =20 -static void bl_gen_sw(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offs= et) +static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) { bl_gen_i_type(p, 0x2b, base, rt, offset); } =20 -static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offs= et) +static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) { if (bootcpu_supports_isa(ISA_MIPS3)) { bl_gen_i_type(p, 0x3f, base, rt, offset); @@ -133,13 +142,13 @@ static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_= t base, uint16_t offset) } =20 /* Pseudo instructions */ -static void bl_gen_li(uint32_t **p, bl_reg rt, uint32_t imm) +static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) { bl_gen_lui(p, rt, extract32(imm, 16, 16)); bl_gen_ori(p, rt, rt, extract32(imm, 0, 16)); } =20 -static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm) +static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) { bl_gen_li(p, rt, extract64(imm, 32, 32)); bl_gen_dsll(p, rt, rt, 16); @@ -148,7 +157,7 @@ static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_= t imm) bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); } =20 -static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm) +static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) { if (bootcpu_supports_isa(ISA_MIPS3)) { bl_gen_dli(p, rt, imm); /* 64bit */ @@ -158,14 +167,14 @@ static void bl_gen_load_ulong(uint32_t **p, bl_reg rt= , target_ulong imm) } =20 /* Helpers */ -void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr) +void bl_gen_jump_to(void **p, target_ulong jump_addr) { bl_gen_load_ulong(p, BL_REG_T9, jump_addr); bl_gen_jalr(p, BL_REG_T9); bl_gen_nop(p); /* delay slot */ } =20 -void bl_gen_jump_kernel(uint32_t **p, +void bl_gen_jump_kernel(void **p, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, bool set_a1, target_ulong a1, @@ -192,7 +201,7 @@ void bl_gen_jump_kernel(uint32_t **p, bl_gen_jump_to(p, kernel_addr); } =20 -void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val) +void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) { bl_gen_load_ulong(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); @@ -203,14 +212,14 @@ void bl_gen_write_ulong(uint32_t **p, target_ulong ad= dr, target_ulong val) } } =20 -void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val) +void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val) { bl_gen_li(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); } =20 -void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val) +void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val) { bl_gen_dli(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); diff --git a/hw/mips/boston.c b/hw/mips/boston.c index edda87e23c..b6dd9fb200 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -323,7 +323,7 @@ static void boston_register_types(void) } type_init(boston_register_types) =20 -static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr) +static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) { uint64_t regaddr; =20 diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 34befa5dd5..cfc8ca6ae4 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -179,7 +179,7 @@ static void write_bootloader(CPUMIPSState *env, uint8_t= *base, /* Second part of the bootloader */ p =3D (uint32_t *)(base + 0x040); =20 - bl_gen_jump_kernel(&p, + bl_gen_jump_kernel((void **)&p, true, ENVP_VADDR - 64, true, 2, true, ENVP_VADDR, true, ENVP_VADDR + 8, diff --git a/hw/mips/malta.c b/hw/mips/malta.c index f959bce673..b5b62e7245 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -844,6 +844,7 @@ static void write_bootloader(uint8_t *base, uint64_t ru= n_addr, uint64_t kernel_entry) { uint32_t *p; + void *v; =20 /* Small bootloader */ p =3D (uint32_t *)base; @@ -886,38 +887,39 @@ static void write_bootloader(uint8_t *base, uint64_t = run_addr, #else #define cpu_to_gt32 cpu_to_be32 #endif + v =3D p; =20 /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - bl_gen_write_u32(&p, /* GT_ISD */ + bl_gen_write_u32(&v, /* GT_ISD */ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), cpu_to_gt32(0x1be00000 << 3)); =20 /* setup MEM-to-PCI0 mapping */ /* setup PCI0 io window to 0x18000000-0x181fffff */ - bl_gen_write_u32(&p, /* GT_PCI0IOLD */ + bl_gen_write_u32(&v, /* GT_PCI0IOLD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), cpu_to_gt32(0x18000000 << 3)); - bl_gen_write_u32(&p, /* GT_PCI0IOHD */ + bl_gen_write_u32(&v, /* GT_PCI0IOHD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), cpu_to_gt32(0x08000000 << 3)); /* setup PCI0 mem windows */ - bl_gen_write_u32(&p, /* GT_PCI0M0LD */ + bl_gen_write_u32(&v, /* GT_PCI0M0LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), cpu_to_gt32(0x10000000 << 3)); - bl_gen_write_u32(&p, /* GT_PCI0M0HD */ + bl_gen_write_u32(&v, /* GT_PCI0M0HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), cpu_to_gt32(0x07e00000 << 3)); =20 - bl_gen_write_u32(&p, /* GT_PCI0M1LD */ + bl_gen_write_u32(&v, /* GT_PCI0M1LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), cpu_to_gt32(0x18200000 << 3)); - bl_gen_write_u32(&p, /* GT_PCI0M1HD */ + bl_gen_write_u32(&v, /* GT_PCI0M1HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), cpu_to_gt32(0x0bc00000 << 3)); =20 #undef cpu_to_gt32 =20 - bl_gen_jump_kernel(&p, + bl_gen_jump_kernel(&v, true, ENVP_VADDR - 64, /* * If semihosting is used, arguments have already b= een @@ -928,6 +930,7 @@ static void write_bootloader(uint8_t *base, uint64_t ru= n_addr, true, ENVP_VADDR + 8, true, loaderparams.ram_low_size, kernel_entry); + p =3D v; =20 /* YAMON subroutines */ p =3D (uint32_t *) (base + 0x800); diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index fffb0b7da8..c32f6c2835 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -11,16 +11,16 @@ =20 #include "exec/cpu-defs.h" =20 -void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr); -void bl_gen_jump_kernel(uint32_t **p, +void bl_gen_jump_to(void **ptr, target_ulong jump_addr); +void bl_gen_jump_kernel(void **ptr, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, bool set_a1, target_ulong a1, bool set_a2, target_ulong a2, bool set_a3, target_ulong a3, target_ulong kernel_addr); -void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val); -void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val); -void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val); +void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val); +void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val); +void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val); =20 #endif --=20 2.38.1