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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673625783713100001 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221220113436.14299-4-philmd@linaro.org> Reviewed-by: Richard Henderson --- hw/mips/gt64xxx_pci.c | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 7ba052a2e0..85bdf5279c 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qemu/units.h" #include "qemu/log.h" +#include "hw/registerfields.h" #include "hw/pci/pci_device.h" #include "hw/pci/pci_host.h" #include "hw/misc/empty_slot.h" @@ -41,6 +42,9 @@ #define GT_CPU (0x000 >> 2) #define GT_MULTI (0x120 >> 2) =20 +REG32(GT_CPU, 0x000) +FIELD(GT_CPU, Endianness, 12, 1) + /* CPU Address Decode */ #define GT_SCS10LD (0x008 >> 2) #define GT_SCS10HD (0x010 >> 2) @@ -210,6 +214,17 @@ #define GT_PCI0_CFGADDR (0xcf8 >> 2) #define GT_PCI0_CFGDATA (0xcfc >> 2) =20 +REG32(GT_PCI0_CMD, 0xc00) +FIELD(GT_PCI0_CMD, MByteSwap, 0, 1) +FIELD(GT_PCI0_CMD, SByteSwap, 16, 1) +#define R_GT_PCI0_CMD_ByteSwap_MASK \ + (R_GT_PCI0_CMD_MByteSwap_MASK | R_GT_PCI0_CMD_SByteSwap_MASK) +REG32(GT_PCI1_CMD, 0xc80) +FIELD(GT_PCI1_CMD, MByteSwap, 0, 1) +FIELD(GT_PCI1_CMD, SByteSwap, 16, 1) +#define R_GT_PCI1_CMD_ByteSwap_MASK \ + (R_GT_PCI1_CMD_MByteSwap_MASK | R_GT_PCI1_CMD_SByteSwap_MASK) + /* Interrupts */ #define GT_INTRCAUSE (0xc18 >> 2) #define GT_INTRMASK (0xc1c >> 2) @@ -1020,15 +1035,16 @@ static const MemoryRegionOps isd_mem_ops =3D { static void gt64120_reset(DeviceState *dev) { GT64120State *s =3D GT64120_PCI_HOST_BRIDGE(dev); +#if TARGET_BIG_ENDIAN + bool cpu_little_endian =3D false; +#else + bool cpu_little_endian =3D true; +#endif =20 /* FIXME: Malta specific hw assumptions ahead */ =20 /* CPU Configuration */ -#if TARGET_BIG_ENDIAN - s->regs[GT_CPU] =3D 0x00000000; -#else - s->regs[GT_CPU] =3D 0x00001000; -#endif + s->regs[GT_CPU] =3D cpu_little_endian ? R_GT_CPU_Endianness_MASK : 0; s->regs[GT_MULTI] =3D 0x00000003; =20 /* CPU Address decode */ @@ -1135,11 +1151,7 @@ static void gt64120_reset(DeviceState *dev) s->regs[GT_TC_CONTROL] =3D 0x00000000; =20 /* PCI Internal */ -#if TARGET_BIG_ENDIAN - s->regs[GT_PCI0_CMD] =3D 0x00000000; -#else - s->regs[GT_PCI0_CMD] =3D 0x00010001; -#endif + s->regs[GT_PCI0_CMD] =3D cpu_little_endian ? R_GT_PCI0_CMD_ByteSwap_MA= SK : 0; s->regs[GT_PCI0_TOR] =3D 0x0000070f; s->regs[GT_PCI0_BS_SCS10] =3D 0x00fff000; s->regs[GT_PCI0_BS_SCS32] =3D 0x00fff000; @@ -1156,11 +1168,7 @@ static void gt64120_reset(DeviceState *dev) s->regs[GT_PCI0_SSCS10_BAR] =3D 0x00000000; s->regs[GT_PCI0_SSCS32_BAR] =3D 0x01000000; s->regs[GT_PCI0_SCS3BT_BAR] =3D 0x1f000000; -#if TARGET_BIG_ENDIAN - s->regs[GT_PCI1_CMD] =3D 0x00000000; -#else - s->regs[GT_PCI1_CMD] =3D 0x00010001; -#endif + s->regs[GT_PCI1_CMD] =3D cpu_little_endian ? R_GT_PCI1_CMD_ByteSwap_MA= SK : 0; s->regs[GT_PCI1_TOR] =3D 0x0000070f; s->regs[GT_PCI1_BS_SCS10] =3D 0x00fff000; s->regs[GT_PCI1_BS_SCS32] =3D 0x00fff000; --=20 2.38.1