From nobody Mon Sep 16 19:02:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673627597; cv=none; d=zohomail.com; s=zohoarc; b=Mm3UG9qaLzyIkxmSf8xuOMeaRY2XP5noJAe8SyKiT3E33pK2b/IA7H2q3W1hn5s8x3AnSb6wu1hPiBfHYnVzMat7UYlDP6QOFIeNeM8owgPBcbB8L4ZOKwBatAq/hSSvWb8AwpHAtbWxwk94idGUXPCxlb08GWFtpMx91Ped+is= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673627597; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=TYm2hyCm8QieU7sfDgUKfEToMnreXHN/6tRbUsQunbI=; b=BIZptVgu8oejujJbTMIilXPeesz40QyUjbq1tYGoEU8VG6ZpFRD5ml3onJlqWc0WB5hdu/tYlN7gWBsSrk/XA9CfjafKYpPGUZh4NRf5AvHqf0psYAV23ctKwJyLV4DL81XAgcXkV+/0eSLdV2ZiMz9yKswMwf/ZCPB1+LWLcaY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTP id 167362759749534.30477506045577; Fri, 13 Jan 2023 08:33:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pGMlz-0004xa-JV; Fri, 13 Jan 2023 11:19:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGMlx-0004wi-2P for qemu-devel@nongnu.org; Fri, 13 Jan 2023 11:19:17 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGMlv-00051c-0G for qemu-devel@nongnu.org; Fri, 13 Jan 2023 11:19:16 -0500 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.226]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Ntmnf6mYmz6J8j8; Sat, 14 Jan 2023 00:19:02 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Fri, 13 Jan 2023 16:19:12 +0000 To: , Michael Tsirkin CC: Ben Widawsky , , , Dave Jiang , , , Shameerali Kolothum Thodi Subject: [PATCH 4/7] hw/pci-bridge/cxl_root_port: Wire up MSI Date: Fri, 13 Jan 2023 16:17:08 +0000 Message-ID: <20230113161711.7885-5-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230113161711.7885-1-Jonathan.Cameron@huawei.com> References: <20230113161711.7885-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml500006.china.huawei.com (7.191.161.198) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1673627623418100001 Content-Type: text/plain; charset="utf-8" Done to avoid fixing ACPI route description of traditional PCI interrupts o= n q35 and because we should probably move with the times anyway. Signed-off-by: Jonathan Cameron --- hw/pci-bridge/cxl_root_port.c | 61 +++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 00195257f7..7dfd20aa67 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -22,6 +22,7 @@ #include "qemu/range.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pcie_port.h" +#include "hw/pci/msi.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "qapi/error.h" @@ -29,6 +30,10 @@ =20 #define CXL_ROOT_PORT_DID 0x7075 =20 +#define CXL_RP_MSI_OFFSET 0x60 +#define CXL_RP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT +#define CXL_RP_MSI_NR_VECTOR 2 + /* Copied from the gen root port which we derive */ #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \ @@ -47,6 +52,49 @@ typedef struct CXLRootPort { #define TYPE_CXL_ROOT_PORT "cxl-rp" DECLARE_INSTANCE_CHECKER(CXLRootPort, CXL_ROOT_PORT, TYPE_CXL_ROOT_PORT) =20 +/* + * If two MSI vector are allocated, Advanced Error Interrupt Message Number + * is 1. otherwise 0. + * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number. + */ +static uint8_t cxl_rp_aer_vector(const PCIDevice *d) +{ + switch (msi_nr_vectors_allocated(d)) { + case 1: + return 0; + case 2: + return 1; + case 4: + case 8: + case 16: + case 32: + default: + break; + } + abort(); + return 0; +} + +static int cxl_rp_interrupts_init(PCIDevice *d, Error **errp) +{ + int rc; + + rc =3D msi_init(d, CXL_RP_MSI_OFFSET, CXL_RP_MSI_NR_VECTOR, + CXL_RP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, + CXL_RP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, + errp); + if (rc < 0) { + assert(rc =3D=3D -ENOTSUP); + } + + return rc; +} + +static void cxl_rp_interrupts_uninit(PCIDevice *d) +{ + msi_uninit(d); +} + static void latch_registers(CXLRootPort *crp) { uint32_t *reg_state =3D crp->cxl_cstate.crb.cache_mem_registers; @@ -183,6 +231,15 @@ static void cxl_rp_dvsec_write_config(PCIDevice *dev, = uint32_t addr, } } =20 +static void cxl_rp_aer_vector_update(PCIDevice *d) +{ + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(d); + + if (rpc->aer_vector) { + pcie_aer_root_set_vector(d, rpc->aer_vector(d)); + } +} + static void cxl_rp_write_config(PCIDevice *d, uint32_t address, uint32_t v= al, int len) { @@ -192,6 +249,7 @@ static void cxl_rp_write_config(PCIDevice *d, uint32_t = address, uint32_t val, =20 pcie_cap_slot_get(d, &slt_ctl, &slt_sta); pci_bridge_write_config(d, address, val, len); + cxl_rp_aer_vector_update(d); pcie_cap_flr_write_config(d, address, val, len); pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len); pcie_aer_write_config(d, address, val, len); @@ -220,6 +278,9 @@ static void cxl_root_port_class_init(ObjectClass *oc, v= oid *data) =20 rpc->aer_offset =3D GEN_PCIE_ROOT_PORT_AER_OFFSET; rpc->acs_offset =3D GEN_PCIE_ROOT_PORT_ACS_OFFSET; + rpc->aer_vector =3D cxl_rp_aer_vector; + rpc->interrupts_init =3D cxl_rp_interrupts_init; + rpc->interrupts_uninit =3D cxl_rp_interrupts_uninit; =20 dc->hotpluggable =3D false; } --=20 2.37.2